Xilinx Inc. recently announced Versal – the super FPGA. Versal is said to be the first adaptive compute acceleration platform (ACAP), a fully software-programmable, heterogeneous, compute platform.
Versal ACAP combines scalar engines, adaptable engines, and intelligent engines to achieve dramatic performance improvements of up to 20X over today’s fastest FPGA implementations, and over 100X over today’s fastest CPU implementations—for data center, wired network, 5G wireless, and automotive driver-assist applications.
Versal is the first ACAP by Xilinx. What exactly is an ACAP? For which applications does it work best?
Victor Peng, president and CEO, Xilinx, said: “An ACAP is a heterogeneous, hardware adaptable platform that is built from the ground up to be fully software programmable. An ACAP is fundamentally different from any multi-core architecture as it provides hardware programmability, but, the developer does not have to understand any of the hardware detail.
“From a software standpoint, it includes tools, libraries, run-time stacks and everything that you’d expect from a modern software-driven product. The tool chain, however, takes into account every type of developer—from the hardware developer, to embedded developer, to data scientist, and to framework developer.
Differences from classic FPGA and SoC
Now, that means there are technical differences in the Versal from a classic FPGA and to an SoC.
He said: “A Versal ACAP is significantly different than a regular FPGA or SoC. Zero hardware expertise is required to boot the device. Developers can connect to a host via CCIX or PCIe and get memory-mapped access to all peripherals (e.g., AI engines, DDR memory controllers).
“The Network-on-Chip is at the heart of what makes this possible. It provides ease-of-use, and makes the ACAP inherently SW programmable—available at boot and without any traditional FPGA place-and-route or bit stream. No programmable logic experience is required to get started, but designers can design their own IP or add from the large Xilinx ecosystem.
“With regard to Xilinx’s hardware programmable SoCs (Zynq-7000 and Zynq UltraScale+ SoCs), the Zynq platform partially integrated two out of the three engine types (Scalar Engines and Adaptable Hardware Engines).
“Versal devices add a third engine type (intelligent engines). More importantly, the ACAP architecture tightly couples them together, via the Network on Chip (NOC) to enable each engine type to deliver 2-3x the computational efficiency of a single engine architecture, such as a SIMT GPU.”
Does this mean that Xilinx will address, besides the classic hardware designers, the application engineers in the future?
He noted: “Xilinx has been addressing software developers with design abstraction tools as well as its hardware programmable SoC devices (Zynq-7000 and Zynq UltraScale+) for multiple generations. However, with ACAP, software programmability is inherently designed into the architecture itself for the entire platform, including its hardware adaptable engines and peripherals.”
Achronix Semiconductor Corp. recently announced the immediate availability of its Speedcore Gen4 embedded FPGA (eFPGA) IP.
Speedcore Gen4 is said to increase performances by 60 percent, reduces die area by 65 percent, and power by 50 percent. In addition, the new Machine Learning Processor (MLP) blocks deliver 300 percent higher performance for AI/ML applications. This is a remarkable improvement across, performance, power, and die area which will help Speedcore users develop significantly better AI/ML applications.
So, what is this proven methodology used to deliver Speedcore Gen4 eFPGA?
Steve Mensor, Achronix VP of Marketing, said: “Achronix has shipped multiple Speedcore 16t (16nm) eFPGA instances. Our customers have:
- integrated their Speedcore eFPGA instance in their SoC
- closed timing
- taped out
- brought up their SoC silicon with the Speedcore eFPGA
- completed ATE testing with over 99 percent coverage
- completed HTOL testing, and
- began production.
“The methodology that we use is proven by the fact that all of the deliveries of our Speedcore eFPGA IP to customers have worked and are fully functionaly.”
These can be licensed to FinFET processes such as the TSMC 16FF+ and now TSMC n7.
Can these be licensed to other processes as well? Mensor said: “Other nodes and other foundries can be supported. Achronix delivers Speedcore as a hard macro as a GDSII. This means that it is optimized for a given node and metal stack. Achronix would need to port Speedcore in order for it to be supported on other process technologies and other foundries. It takes Achronix 4 months to port to a new process node on TSMC and 9 months to port to a new foundry.”
The Speedcore Gen4 eFPGA IP is for integration into users’ SoCs. Mensor said: “This simply means that Speedcore is IP that companies can integrate into their SoC. Speedcore is an all digital IP (no mixed signal / analog functionality). Companies integrate it just like they would integrate any other digital IP. “
I am really intrigued by this headline! First, SEMI, and now, The Information Network, are making the forecast for China!! However, what has been India doing? Nothing!!
Massive investments in Mainland China are finally showing benefits as the ratio of ICs made in China versus those imported into China increased from 27 percent in 2015 to 29.1 percent in 2016, according to the annual update of The Information Network report entitled “Mainland China’s Semiconductor and Equipment Markets: A Complete Analysis of the Technical, Economic, and Political Issues.” Driving the growth of ICs made in China are a large number of fabs that are in construction and planning production over the next few years, said Robert Castellano, president, The Information Network.
Next, most of the advanced semiconductor packaging is done in China. There are over 150 foreign and domestic packaging companies based in China. Tied to the packaging industry is the need for back-end semiconductor equipment. With its robust IC program, China represents a strong growth area for advanced packages, used to house and protect the ICs. These advanced packages include 3D, TSV (through silicon vias), FOWLP (fan-out wafer level packaging) and flip chip.
According to The Information Network:
* Investments by the Chinese government and foreign semiconductor manufacturers have started having an impact on meeting China’s internal IC semiconductor needs.
* A surge in semiconductor growth in China merely means these same number of chips won’t be made elsewhere — a buying opportunity for semiconductor manufacturer stocks.
* Large equipment companies will benefit from new fabs built but will face increased pricing pressure from new semi manufacturers because their traditional customer base has changed.
* Smaller semiconductor equipment suppliers will benefit from a new customer base that had been traditionally buying from the same vendor.
* Rudolph Technology is an example that benefited last year, positioning itself with its product line and strategic focus on building a sales infrastructure in China.
According to SEMI, USA, China is projected to be the top spending region for fab equipment in 2019 and 2020. Of the 20 more fab projects, SEMI is tracking up to 16 potential 300mm fabs to be constructed or beginning to ramp up throughout the forecast, with the investment targeted for the memory and foundry sectors.
Is India even listening?
Friends, I just learnt that Pradeep’s Point has been selected as the Top Blog for Design and Verification by Bucharest, Romania-based firm AMIQ Consulting. Once again, I am extremely grateful to all of you for helping me achieve this awesome distinction!
This recognition is now my 20th overall, and 16th, including one national recognition, for all of my blogs. That 19 such recognitions are from the overseas, is probably evident of the fact that electronics and semiconductors are well read, followed and even written overseas.
Am I wrong? I sincerely hope not, as there is a lot of work being done in electronics and semiconductors within India. The one thing missing from all of this is the presence of leading Indian firms — origin or based — in electronics and semiconductors. I hope that changes in future. And, till that happens, all of those studies depicting India as an electronics hub, are wasted.
As for the blog awards, I’ve mentioned that it’s my 16th recognition, including one national recognition, for all of my blogs. I have now completed a decade of writing (or blogging), and that’s a great result, won’t you all agree? 🙂 I didn’t even know that the blogs will help me achieve so much international (and national) recognition back in 2007, when I returned to India, from Hong Kong.
I started these blogs, back in 2007, to assist my friends, Kevin Ho Fai Lau, Zoe Lam, Alfred Cheng, Yashan Jo Kuo, John Ng, Claudius Chan, Kittie Wong, Len Sangalang, and some others.
Later, Usha Prasad (who was with me till 2012), S. Uma Mahesh, S. Janakiraman, Anand Anandkumar, Jaswinder Ahuja, Montu Makadia, Veeresh Shetty, Raghu Panicker, Dr Pradip Dutta, Vivek Sharma, Vivek Saxena, Sanjeev Keskar, Sathya Prasad, Dr. Satya Gupta, Rahul Arya, Malcolm Penn, Dr Walden Rhines, Dr Aart de Geus, Shinto Joseph, as well as late Ms Tarana Uthayya, Sanjana Shetty, Varsha Poonacha, Padmini Hegde, my niece, Aanchal Ghatak, my son, Prateek Chakraborty, and several others joined the fray.
A decade of winning awards and titles has been a tremendous journey. Thank you to all of you who have made this possible! 🙂 Thanks are due to my wife, Shima Chakraborty, for putting up with me! 🙂
Intel has begun sampling 14nm Stratix 10 FPGAs to customers. The Stratix 10 is the 14nm FPGA that was built as a result of Intel and Altera’s foundry agreement in 2013. Stratix 10 is the industry’s highest performance, highest capacity FPGA ever built.
How is the Intel 14nm FPGA superior to that of Xilinx? According to a spokesman, Stratix 10 FPGAs provides a first to node advantage for Intel, in that Stratix 10 are the first true 14nm FPGAs, delivering the performance and density advantage of a true process shrink.
How are memory and programmable solutions delivering new classes of products for the data center and the IoT ?
IoT is said to be bringing online billions of new smart and connected devices that are generating a tremendous amount of data. This data must be processed, analyzed and acted upon in real time within the cloud and data centers.
FPGAs, like Stratix 10, are built to support this demand by delivering high-performance, multi-function acceleration to the data center. Microsoft and their use of FPGAs to power Azure and to accelerate Bing are great examples of this acceleration today.
Broadcom did announce 5G a couple of years ago. Is Intel’s 5G any different?
According to Intel, FPGAs will be a key enabler in driving 5G deployments. “As we are in the early stages of 5G where standards are being finalized, the flexibility of FPGAs are invaluable to developers of wireless infrastructure, as the FPGA can be re-programmed as standards are adopted and finalized,” he added.
What is Intel doing in memory and programmable solutions that will make it different?
5G represents a significant shift for the industry, and requires an unprecedented integration of wireless connectivity, computing intelligence, and distributed cloud resources. It will fundamentally transform our lives, bringing us a society that is smarter and more connected.
To realize this potential for the IoT and enable richer experiences throughout daily life, wireless networks must transform to become more powerful, agile and intelligent. Intel is transforming the wireless networks and infrastructure to lay the path to 5G. FPGAs like Stratix 10 and memory are key enabling technologies for Intel.
If you look at some of Stratix 10’s capabilities vs. the prior generation, which companies like Microsoft are using to power its data centers, you get a clear picture of how developers of high-end networking gear, communications infrastructure and data centers will benefit from these high-performance, multi-function accelerators.
* 2X higher performance.
* 5X higher capacity.
* 8X higher TFLOPS.
* Integrated of high-bandwidth memory (HBM2).
* Integrated ARM A53 quad core processor.