Xilinx Adapt: Vivado conference began in the USA today. There are sessions on verification IPs, traffic generators, simulation models in RTL and transaction level, etc.
Satyam Jani, Senior Product Manager, Xilinx, presented the simulation scope, such as AIE simulation, HLS co-simulation, QEMU, and hardware emulation. The Xilinx Versal ACAP simulation allows simulating invidual blocks or the entire system. The simulation choice is based on scope and abstraction. There are supported flows in Vitis and Vivado.
Verification IPs and traffic generators are used extensively. There is AXI VIP and AXI Stream VIP protocol checker support. Versal CIPS VIPs allow functional verification of control interfaces, and processing system (CIPS). It allows verifying PS-PL interfaces and OCM memories. Simulation libraries are for behavioral, functional and timing simulation. There are pre-compiled simulation libraries for XSIM. TLM model support is meant to reduce the simulation time.
Xilinx simulator (XSIM) is a home-grown simulator with no design size limitation. There is support for UVM 1.2 and functional coverage. XSIM SystemC is a mixed language simulation support for SystemVerilog and SystemC. There are pre-compiled SystemC models.
The integrated simulation flow covers from behavior to timing simulation. Compilation and simulation time are important. YOu can expand the verification environment with VIPs and TCL store apps.
Matt Piazza, Senior Product Management Engineer, Xilinx, presented on hardware debugging. There are fabric debug and hard block debug. UltraScale+ has new entrants such as IBERT GTM that debugs and characterizes for 58Gbps PAM4 transceivers. HBM monitor is also present. There are debug objectives for Versal, such as system-level visibility, higher performance, and flexibility. Debug packet controller (DPC) enables multiple access options.
Takayuki Ikushima, Market Development Director, Industrial & Automotive Business Unit, Programmable Solutions Group, Intel, presented a session on Intel FPGAs enabling industrial automation and Industry 4.0, at the Intel FPGA Technology Day 2020.
Industries are going through transformation. There is now an evolution to smart factories. These are enabling downtime reduction, improved product quality and optimized operations. As per a Capgemini study over 70 percent of manufacturers have a smart factory initiative. FPGA flexibility, connectivity, and performance enable smart factory applications.
FPGA in Industry 4.0
Industry 4.0 presents more flexible and connected architecture. This opens the opportunities for implementing intelligence. Evolution to smart factories are happening in multiple phases. You need to connect the unconnected, be smart and connected, and move on to autonomous. Smart and connected devices are making their way to the factories.
Intel CPU is a major player in the industrial IT market. Intel FPGA is a market leader in industrial OT market. Together, they are driving IIoT transformation for Industry 4.0.
There is a role for FPGAs in the Industry 4.0 paradigm. Applications exist for vison-based, robotics, motion control, sensors, etc. Intel FPGA can provided TSN switch implementation. Many industrial apps now connect to the cloud for data logging, analytics, remote management, etc. Over things, edge, and cloud, FPGAs can combine many apps.
The Edge AI acceleration solutions from Intel include Corerain Nebula accelerator and the ATUS, or CVDL-m9A miniPCIe card. Cirerain is a high-performance, low-latency, and high-cost efficient AI acceleration solution. ATUS is a deep learning-based edge vision AI inference accelerator using Cyclone V FPGA.
An MLOps demo was done with AWS and LeapMind. Sample MLOps system was used to prove remotely-managed AI service for embedded IoT apps. LeapMind’s Blueoil and AWS components, such as AWS IoT Greengrass and Amazon SageMaker. It enabled multiple FPGA-based AI devices on the field to be managed and remotely updated by AWS Cloud.
Intel offers the portfolio for all three robotics activities, sense, plan, and act. At the sense stage, there is the depth camera and workload/AI accelerators. At the plan stage, Intel processor family is used. At the act stage, there are embedded FPGAs. There is also a drive-on-a-chip for robotics and drives. The reference design is an integrated drive system of single- and multi-axis field-oriented control (FOC), supporting concurrent control of upto four permanent magnet synchronous motors.
There is the TUV-certified IEC1508 functional safety data package. You can now reduce the time for functional safety certification. This includes devices, docs, IPs, and tools. A success story was the Yaskawa YRC1000 robot controller in Japan.
Among the reasons for selecting Intel FPGA were integration of custom logic, PCIe, and software applications, low-power for fanless system, monitoring position data of the encoders and cross-checking by FPGAs, reduced development time compared with ASIC, with programmability, shorter certification turnaround time, etc.
Intel offers supported protocols and IP partners. There are Intel FPGA-based time-sensitive networking (TSN) solutions, along with off-the-shelf solutions. There is the IIoT edge controller and gateway, as well, such as the eXware 707T. There are system-on-module (SoM) offerings, as well. Intel also offers the FPGA cloud connectivity kit. The base kit is certified for Microsoft Azure and qualified for AWS Greengrass.
There is the TLS 1.3 hardware security IP core from Xiphera in Finland. The cryptographic computations and key management are entirely FPGA-based, enables complete independence from software for security-critical apps.
Another solution is DOME, the IoT secure ownership management solution, from Veridify Security, USA. It offers low-touch onboarding and the end-to-end blockchain ownership management for globally distributed devices at the edge.
Let us all make smart factory for real!
Day 2 of the Xilinx Adapt: 5G event began with a presentation by Brendan Farley, VP Wireless Engineering & MD EMEA, Xilinx. He spoke about the future technologies of 5G wireless.
There is the disaggregated 5G radio access network, by 3GPP and O-RAN. If we look at the new radio units, mmWave technology is very sensitive to the channel. It needs to be easy installation, with low costs from the operational side. The hardware needs to be cost effective. On the DU side, operators are tied into OEMs. The objective is to move to a server-controlled open approach. The partitioning between the DU and radio unit is key.
The view from the base station gives one of massive MIMO. Viewing the city scape, there is direct line-of-sight access available in most areas. We get the capacity increase by re-using the frequency. Beam forming gets visualized. Services such as video streaming, AR/VR. remote health consultation, etc. are being offered.
There is need to upgrade the existing 4G sites with 5G mMIMO panels. You need to minimize the hardware TCO. This can be done by virtualizing the baseband and centralize to support multiple radios. Advanced silicon technology and integration will be needed. You also minimize the opex. There is need to maximize the RAN performance and capacity. You can also increase the bandwidth, optimize baseband with radio partitioning, and optimize the 5G operator services through acceleration, virtualization, and O-RAN.
In terms of the radio panel power, weight and cost optimization, there is the 320W 64TRX mMIMO panel. It can host increasingly powerful DPD algorithms to linearize the power efficient GaN PAs. GaN has been used successfully in China. You can also reduce the panel heatsink weight through RF power reduction. You can also drive lower TCO by utilizing the most advanced silicon technology with flexibility to enable future 5G/O-RAN system evolution.
GaN power amplifier (PA) technology has been linearized with the Xilinx digital pre-distortion (DPD). We have created powerful PA algorithms that run on the Xilinx FPGAs. The issue with GaN is long-term memory effect.
Although, the improvements in LDMOS amplifier characteristics allow for frequency ranges up to 22 GHz, GaN-based amplifiers achieve frequencies up to 30 GHz at power densities up to five times higher, although at higher prices than LDMOS devices.
As for the form factor/weight of O-RU design, Xilinx lidless yields 28-degrees C improvement over traditional lidded design. Chinese OEMs are now incorporating lidless technology in 5G mMIMO panels.
Advanced silicon integration
Advanced silicon integration is done on Xilinx Zynq RFSoC DFE (digital front-end). There is over 2X compute for powerful DPD and upto 400MHz bandwidth. There are hardened and configurable functions for power and cost. Programmable logic also enables customization and future adaptability.
There is increased flexible compute, while reducing TCO. Use cases will definitely evolve over time. Base stations can adapt with the Zynq RFSoC DFE. There can be hardened DFE cores in 5G phase 2. Rel 18 will have adaptable logic as the standards evolve.
You can also scale for capacity. There are studies conducted by Ericsson. In India, the 32TRX seems to have found a sweet spot. The 64TRX has found space in China and Korea.
For O-RAN and O-DU virtualization, the O-RAN defines the functional splits between O-DU (baseband) and O-RU (radio). We anticipate the further migration of functionality to O-RU. Equalization, channel estimation, etc., are associated.
There is the 5G mMIMO UL performance challenge. MIMO decoder channel correction performance is dependent on factors. There is the beamformer discrimination performance. There will be future UL performance solution. There will be improved UL beamformer performance. It is essential to have a system that is adaptable and programmable.
The Xilinx 7nm Versal ACAP platform is adaptable technology for next-gen 5G beamforming systems. The capacity, compute and performance is 5X than the 16nm device.
In conclusion, the first wave of 5G has provided a clear picture of success metrics and challenges for the next wave. Advanced technology is essential to realize the 5G vision of higher capacity and improved services in an economically viable manner. Next-gen Xilinx technology provides an adaptable platform.
Intel organized the Intel FPGA Technology Day 2020, titled: Accelerating a smart and connected world.
David J. Moore, Corporate VP and GM, Intel Programmable Solutions Group, along with Patrick Dorsey, VP & GM, FPGA and Power Products Group, Programmable Solutions Group, Intel, presented the opening session.
David J. Moore said there has been great change due to the global pandemic. Together, we can re-imagine how people and data can change our world for the better. The potential for data to transform businesses and markets has never been greater. We have seen several examples of how we use data.
Data is projected to reach 175 ZB by 2025. Mobile and cloud have changed the way we live, and the way we create and use data. We are now looking at the next era of disruption. With the exponential amount of connectivity, we are generating an exponential amount of data. There is a huge data opportunity for innovation. We are generating data at a faster rate than our ability to analyze, understand, transmit, secure, and reconstruct in real time.
There are key technology inflections. 5G will enable rich, new data experiences. There will be 5G network transformation. AI is a fundamental driver. It will convert data into an opportunity. Machine learning and range of developments continue to occur. The edge is necessary to become more intelligent. The levels of efficiency will increase with the cloudification of everything.
Intel is also unleashing the full potential of data. Software and system level approaches are also getting optimized. Storage efficiency is also growing in importance. We have a wide range of processing architectures. We have the Intel Ethernet, Intel Silicon Photonics, and Intel Tofino Switch. We are also finding ways to optimize and lower the TCO.
Intel FPGAs provide the flexibility for a rapidly transforming world. We are extending platform capabilities, intercepting evolving requirements, and enabling agile innovation. FPGAs are also ideal for agile innovation. The range of challenges that FPGAs can unlock continues to expand broadly. We are working with a range of partners. FPGAs are also powering the next-gen infrastructure, accelerating the analytics processing, etc.
At the edge, FPGAs find apps in a diverse range, from smart factory and Industry 4.0, to next-gen vision systems, aerospace, etc. Ability to process data at the source is critical to the intelligent edge.
Patrick Dorsey said that the global pandemic has not stopped innovation at Intel. Intel’s product focus is on being developer first, leadership in FPGA and custom logic silicon, and delivering end-to-end heterogenous platform. We are developing compute, connectivity and data access platforms with partners.
The Intel Quartus Prime is the FPGA design software tool. It has a comprehensive developer support, ease of use with Design Assistant, and provides upto 40 percent higher performance or 40 percent lower power with Intel Agilex FPGA designs.
For the software developers, there is the Intel oneAPI Base Toolkit. It has a unified programming model for XPUs, open specifications and standards, and ease of use.
Intel is now announcing the Intel Open FPGA Stack (IOFS), the second generation of FPGA software platform. There is faster time to innovation and accelerated deployments. There will be more details on IOFS in a separate session.
Intel also has the Custom Logic Continuum. It has the fastest time to market and highest flexibility. There is the highest performance, and lowest power and cost. There is flexible, re-usable, and agile optimization across the product lifecycle.
Intel has rapid silicon innovation that allow any compute, any connection, and any developer. There is the FPGA chiplet library. It started with the Intel Stratix. In production now is Intel’s first AI-optimized FPGA for high-bandwidth, low-latency AI acceleration.
The Intel Agilex series FPGAs with 10nm SuperFin technology offer upto 40 percent higher performance, upto 40 percent lower power, PCI Express Gen5, Compute Express Link (CXL), 116Gbps transceiver, and next-gen HBM2e.
Edge-optimized FPGAs are always going to be a focus area for Intel. They have long product lifecycle, continuous software support, and continuing IP and solution development.
Intel is also announcing the industry’s newest structured ASIC. We are introducing the Intel eASIC N5X device family. It is the first structured ASIC with Intel innovations. There is the FPGA-compatible hard processor system. It has upto 50 percent lower core power compared to the FPGAs. There are smaller form factor custom packages. The optimized TCO supports Intel’s custom logic continuum from FPGA to structured ASIC, on to ASIC platforms and solutions.
Intel has also invested in growing their leadership in the SmartNIC market. Intel FPGA-based SmartNIC products include the Intel FPGA SmartNIC C5000X platform architecture, which helps you to supercharge your cloud data center, and the Silicom FPGA SmartNIC N5010 that allows multi-workload acceleration for the network core. These are transforming the network and the cloud.
These are just some of the many innovations Intel has developed this year. We are solving many real-world challenges together. Intel FPGAs are accelerating key transitions. Accelerate the future with Intel.
The Xilinx Adapt:5G event started in the USA today. Liam Madden, EVP and GM, Wired and Wireless Group, Xilinx, rolled off proceedings with the session: Aligning to 5G Trends and Winning the Race.
Many 5G networks are becoming saturated, as of Sept. 2020. Korea saw 2X increase in data consumption, relative to 4G. We expect the lifetime of 5G to be much more than 4G. There are more 5G use cases evolving, with IIoT, Industry 4.0, CV2X (cellular-vehicle to everything), etc., leading the way.
Nearly half of the world is still not connected to the Internet. The 5G market disruptions are also enabling new operators and providers.
There are new operators, such as Rakuten, in Japan. It is also scalable from massive-MIMO macrocell to small cell. Xilinx has partnered with TI for SoC devices. Xilinx is an active member of the O-RAN Alliance and the Open RAN Policy Coalition.
Recently, Vodafone ran the OpenRAN hardware radio RF results. We are also selected by KMW, South Korea, for its future products. KMW was responsible for the 5G rollout in South Korea. Also, Samsung and Xilinx engineers used high-level compliers. For the Zynq from Xilinx, the RF SoC DFE, we got valuable feedback from customers. There is also the 5G Xilinx telco card, which is being evaluated.
Xilinx solutions include SDSoC and SDAccel Environments, Vivado HLS, Multi-level security, Zynq UltraScale+ MPSoC, and UltraScale. The 5G apps targeted are CloudRAN, massive MIMO, backhaul, fronthaul, baseband, and small cell.
5G big picture
Joe Madden, Founder and Chief Analyst, Mobile Experts Inc., presented on The 5G Big Picture: What It Is Really For, and How It Changes the World.
He said that it is difficult to use 10MB speed on cell phones. Things changed when faster clock speed didn’t drive user experience anymore. It’s really about the cost of computing today. The cost per GB of data has been decreasing per generation.
With 5G, we are getting much more. Money is spent on more and more GB. Wireless has been a little expensive than wired alternatives.
Now, cost difference does not really matter. With 5G, wireless is at the crossover point. At least 70-80 percent of traffic on the network is now video. People can stream information at a reasonable price.
Enterprise automation has the potential to grow to the trillion-dollar level. IoT, Industry 4.0, etc., will be among the drivers. There needs to be some maturity in the edge computing and software platforms.
In 5G network deployment, Korea, Japan, and USA, are driving solid growth based on real customer demand. China represents a surge in 5G in the short-term period. The peak is currently surging through. China’s MIT is delaying the 5G deployment.
In Covid-19, cloud saved the world, while mobile saved the cloud. There was 770 percent increase in cloud instances, and 23X increase in Webex sessions.
There was 10 percent to 50 percent in mobile data traffic. Wireless has picked up the slack. Mobile has accelerarted the attack on fixed broadband.
The O-RAN Alliance is now helping to get the Open RAN gain traction. Rakuten network in Japan has demonstrated how it works. We expect the high-capacity performance to improve. There is going to be some fragmentation with more radio vendors.
There is also the chaos of the trade war between China and USA. Huawei is cut off from American semiconductor shipments, and also from TSMC. SMIC is not a viable solution. Qualcomm has been asking for a waiver to ship SoCs to Huawei. The Chinese government has also delayed 5G build-outs, perhaps, for the next two years, to allow for negotiations at the political level. Overall, 2020 has been a good year, but China has not been surging, as expected. The economics of ASICs vs FPGAs are also changing.
5G enables ‘true cord cutting’. It is convenient, and is also about cutting the TV bundle. We will see different kinds of market growth in the future.
Xilinx is launching the industry’s first 20nm radiation tolerant FPGA for space applications.
Minal Sawant, Space System Architect, Xilinx, based out of San Jose, USA, said that designers face challenges such as limited downlink bandwidth, low latency and high orbit, ML in orbit, there are SWaP (size, weight, and power trade-offs), flexible system architecture, reliable components for extreme environments and mission life, and need for capability to process on board a satellite vs. ground station.
ML is going to become dominant in the space industry. There are key target markets and applications for reconfigurable payloads. There are communication payloads, earth observation payloads and space 2.0 constellations.
Xilinx is introducing the 20nm RT Kintex UltraScale FPGA. It can handle adaptive computing for ultra-high throughput, high bandwidth satellite apps. There is true unlimited on-orbit reconfigurable solution. There is >10X DSP compute increase for processing intensive algorithms and analytics. ML ecosystem enables high performance edge interference in space. There is full radiation tolerance across all orbits.
The RT Kintex UltraScale platform with high bandwidth compute capability has features such as 2760 DSP slices in multi-precision fixed and floating point modes, 32 high-speed SERDES (12.5Gbps) and 400 Gbps aggregate bandwidth,, radiation tolerance across all orbits, TID >100Krad/si and SEL >80MeV-cm2/mg,1 as well as a robust 40x40mm ceramic column grid array packaging. It meets the next generation on-orbit processing needs. Production of class B and class Y units will be in Sept. 2020.
Software has a simplified development environment, based on the Vivado Design Suite. There is redesigned routing architecture and 2X routing resources, and also eliminates congestion. There is an ASIC-like clocking with flexibility for clock placement and balances skews. It is also space resilient. As you move away from the earth, the radiation changes. There is radiation tolerance and reliability across all orbits. There is also the unlimited on orbit configuration, with change-on-the-fly capability. Sensors process data and send it for the on-board processing.
She said that Xilinx is also bringing ML to space. You can process and analyze with real-time on-board processing. There is dense, power-efficient compute with scalable precision and large on-chip memory. There is 5.7TOPs INT8 performance and a triple modular redundant MicroBlaze supported by Xilinx Vitis tools for ML-centric work. ML on the RT Kintex UltraScale gives high-performance neural network inference acceleration. There are available flows within the open source compilers (FINN, etc.).
There are payload use cases with an unlimited on-orbit reconfiguration. You can do reconfiguration by storage of multiple bitstreams in NVM. You can also do this via the on-board computer and the ground station as well. Future roll out for space applications include Xilinx Class B and Class Y, by Sept. 2020.
Some really interesting news is coming out from the global semiconductor and telecom industries!
First, TSMC has plans to construct an advanced semiconductor plant in Arizona, USA. TSMC Chairman, Mark Liu has reportedly said the company is actively evaluating the US fab plan.
Ok! It is confirmed!! TSMC has announced its intention to build and operate an advanced semiconductor fab in the United States with the mutual understanding and commitment to support from the U.S. federal government and the State of Arizona.
This facility, which will be built in Arizona, will utilize TSMC’s 5-nanometer technology for semiconductor wafer fabrication, have a 20,000 semiconductor wafer per month capacity, create over 1,600 high-tech professional jobs directly, and thousands of indirect jobs in the semiconductor ecosystem. Construction is planned to start in 2021 with production targeted to begin in 2024. TSMC’s total spending on this project, including capital expenditure, will be approximately US$12 billion from 2021 to 2029.
A statement says: “This U.S. facility not only enables us to better support our customers and partners, it also gives us more opportunities to attract global talents. This project is of critical, strategic importance to a vibrant and competitive U.S. semiconductor ecosystem that enables leading U.S. companies to fabricate their cutting-edge semiconductor products within the United States and benefit from the proximity of a world-class semiconductor foundry and ecosystem.”
TSMC holds a distinct technical advantage in terms of advanced process technology, which has encouraged the U.S. government to give TSMC priority as a potential semiconductor partner, according to TrendForce, Taiwan.
TSMC recently announced net revenues for April 2020. On a consolidated basis, revenues for April 2020 were approximately NT$96 billion, a drop of 15.4 percent from March 2020, and an increase of 28.5 percent from April 2019. Revenues for January through April 2020 were NT$406.60 billion, an increase of 38.6 percent, compared to the same period in 2019.
Next, Applied Materials announced Q2 2020 results where it reported a generated revenue of $3.96 billion. On a GAAP basis, the company recorded gross margin of 44.2 percent, an operating income of $932 million or 23.6 percent of net sales, and earnings per share (EPS) of $0.82.
“As we navigate the challenges created by Covid-19, we have rallied the company around safety, productivity and keeping our customers and the industry moving forward,” said Gary Dickerson, president and CEO. “While the situation remains fluid, based on the visibility we have today, our supply chain is recovering, and underlying demand for our semiconductor equipment and services remains robust.”
Samsung Electronics reported financial results for Q1 ended March 31, 2020. The total revenue was KRW 55.33 trillion, a decrease of 7.6 percent from the previous quarter, mainly due to weak seasonality for Samsung’s display business and Consumer Electronics Division, and partially due to effects of Covid-19. From a year earlier, revenue rose 5.6% due to increasing demand for server and mobile components.
Another major, an unnamed player (see name after May 20) is launching the industry’s first 20nm radiation tolerant FPGA for space applications.
Intel Capital has announced new investments totaling $132 million in 11 technology startups. These companies are in AI, autonomous computing and chip design. The companies are: Anodot, Astera Labs, Axonne, Hypersonix, KFBIO, Lilt, MemVerge, ProPlus Electronics, Retrace, Spectrum Materials and Xsight Labs.
Elsewhere, GlobalData reports that some regulators have recognized the need to move forward with 5G spectrum allocation. In New Zealand, for example, the regulator has decided to direct allocate 5G spectrum in the 3.5GHz band to three operators — Dense Air, Spark and 2degrees, without conducting an auction. Perhaps, India can learn from this!
In the USA, the FCC has allowed major operators, Verizon, AT&T, T-Mobile and US Cellular, to temporarily borrow spectrum from the existing licensees in the 600 MHz and AWS frequency bands (1700 MHz / 2100 MHz) for a 60-day period.
Well, keep watching, folks! There may just may be more good news to share!
Achronix Semiconductor Corp. recently announced the Speedster7t FPGA+ family for AI/ML and high bandwidth data acceleration applications. FPGA+ is new class of technology. There is FPGA adaptability with ASIC performance. The architecture and ACE software further enables a new ease of use design paradigm.
This announcement comes closely on the heels of an earlier FPGA launch, based on TSMC’s 7nm.
Ground-breaking FPGA family
So, why does Achronix have a ground-breaking FPGA family? Steve Mensor, VP of marketing, Achronix, said: “Speedster7t is the first FPGA with a 2D NoC (network-on-chip) for enabling high-performance data paths and it will fundamentally change the design methodology for FPGA design by eliminating the challenges of creating switch networks between accelerator functions and the FPGA high-performance interfaces. Additionally, Speedster7t is the first FPGA with machine learning processors (MLP) optimised for AI/ML applications.”
Aren’t there other devices available as well? He said: “Intel AgileX does not have NoC or AI/ML-optimised DSP blocks. Xilinx Versal has a NoC that has approximately 1/10 the bandwidth, but it is not part of the FPGA fabric. It is made to move data between the ARM CPU complex, the vector engines and the FPGA fabric.
“Versal does not have AI/ML-optimised DSP blocks. Instead, they have the vector engines that are called AI engines. These are not part of the FPGA — they are separate functions located near the FPGA fabric. The AI engines will require an entirely new design framework, which may to be useful for companies that use FPGAs.”
Blending FPGA with ASIC
How has the it blended FPGA programmability with ASIC routing structures and compute engines? He added: “The 2D NoC is an ASIC function and so is the MLP. The NoC moves data at ASIC rates and the MLP completes AI/ML processing at ASIC rates.”
Elaborating on how Achrinix rethought the entire FPGA architecture, he said: “Speedster7t is the first FPGA that has a new hierarchy of routing structure, which is the NoC. The NoC allows for ASIC bandwidth performance and fundamentally simplifies the design methodology for creating accelerator functions in FPGAs.”
How are MLPs delivering the industry’s highest FPGA-based compute density, and what is the number, if any?
According to him:”The MLPs include up to 32 MAC functions per MLP. Additionally, they run at 750 MHz for AI/ML functions. Other FPGAs do not have the equivalent MAC count or performance. The mid-sized 7t1500 Speedster7t is capable of 86 TOps (tera-operations per second) and 8,600 images per second for ResNet-50.”
The Achronix 7t1500 and PCIe-based accelerator board with the 7t1500 will available in Q4 2019.
— By Ms Aanchal Ghatak & Pradeep Chakraborty
Intel Corp. has announced a brand-new product family, the Agilex FPGAs. It will provide customized solutions to address the unique data-centric business challenges across embedded, network and data-center markets.
Intel Agilex FPGAs and SoCs harness the power of 10nm technology, 3D heterogeneous SiP integration and chiplet-based architecture to provide the agility and flexibility required to deliver customized connectivity and acceleration for compute and data intensive applications.
Intel Agilex FPGA highlights are:
- Compute Express Link: Industry’s first FPGA to support Compute Express Link, a cache and memory coherent interconnect to future Intel Xeon Scalable processors.
- 2nd Generation HyperFlex: There is up to 40 percent higher performance, or up to 40 percent lower total power, compared with the Intel Stratix 10 FPGAs.
- DSP innovation: Only FPGA supporting hardened BFLOAT16 and up to 40 teraflops of digital signal processor (DSP) performance (FP16).
- PCIe Gen 5: Higher bandwidth compared with PCIe Gen 4.
- Transceiver data rates: Support up to 112 Gbps data rates.
- Advanced memory support: DDR5, HBM, Intel Optane DC persistent memory support.
Problems it is solving
So far, so good. Now, what are the problem that it is solving?
Data-centric problems require solutions with the ability to aggregate and process increasing amounts of data traffic to enable transformative applications in the emerging, data driven industries like edge computing, networking and cloud.
Whether it’s through edge analytics for low-latency processing, virtualized network functions to improve performance, or datacenter acceleration for greater efficiency, Intel Agilex FPGAs are built to deliver customized solutions for applications from the edge to the cloud.
Advances in artificial intelligence (AI) analytics at the edge, network and the cloud are compelling hardware systems to cope with evolving standards, support varying AI workloads, and integrate multiple functions. Intel Agilex FPGAs provide the flexibility and agility required to meet these challenges and deliver gains in performance and power.
Different from competition
How is this different than what the competition provides?
According to a spokesperson, the Intel Agilex FPGA family brings together the power of Intel’s 10nm process technology, 3D heterogeneous System-in-package (SiP) integration with Intel’s proprietary Embedded Multi-Die Interconnect Bridge (EMIB) and an innovative chiplet-based architecture to deliver customized connectivity and coherent acceleration.
The benefits from these unique architecture and technology elements are that in the data-centric world, where there is a need to process, store, and move data, Intel Agilex FPGAs provide the agility and flexibility with improvements in performance and power efficiency across a variety of markets.
Process data: Intel Agilex FPGA leverages a second generation HyperFlex architecture to deliver up to 40 percent higher performance, or up to 40 percent lower power, compared to prior Intel FPGAs. The enhancements in the DSP block architecture enable Agilex to deliver up to 40 TFLOPs of floating point performance.
Data storage: Intel Agliex FPGAs support the most advanced memories, including DDR5, and high bandwidth memory (HBM). Intel Agilex FPGA is also the only FPGA to support Intel Optane DC Persistent memory.
Moving data: Intel Agilex FPGAs support Compute Express link, a cache-coherent interface to future Intel Xeon processors and PCIe Gen5, providing high bandwidth for processor communication. Intel Agilex FPGAs also support up to 112G XCVR data rates.
Finally, what is the status of the MCP announced in May 2018, which integrates the Intel Xeon Gold 6138P processor with a built-in Altera Arria 10 GX 1150 FPGA? Intel is currently shipping this product and partnering with Fujitsu on their solution development.
— By Pradeep Chakraborty & Aanchal Ghatak