FPGAs
Road to ‘Beyond Moore’ with heterogenous integration for next-gen computing
Heterogeneous integration is paving the way for microelectronics resurgence, stated Dr. William Chen, ASE, and co-chair of the IEEE/ASME/SEMI Heterogeneous Integration Roadmap at the 2023 Heterogeneous Integration Symposium organized by IEEE Santa Clara Valley Electronics Packaging Chapter, Milpitas, USA.
2023 is the 75th anniversary of the transistor. On December 16, 1947, John Bardeen and Walter Houser Brattain at Bell Labs NJ, demonstrated the first working transistor, now know as the point-contact. William Shockley, invented junction transistor in 1948. They initiated the first stone for the foundation of the Smart or Intelligent Society.
Next are inventions of integrated circuits (independently by Jack Kilby and Robert Noyce, 1958 and 1959). Moore’s Law progress and 50+ years of scientific and technological progress by scientists and technologists still going strong today. Semiconductor and electronics are now recognized as foundation pillars for digital transformation in service to society and humanity.
In 1991, the world’s first Open-Source Technology Roadmap, the National Technology Roadmap for Semiconductors (NTRS) sponsored by US Semiconductor Industry Association (SIA). In 1998, NTRS expanded forming the first Global Technology Roadmap. Europe, Japan, Taiwan, and Korea joined. It was renamed International Technology Roadmap for Semiconductors (ITRS). In 2014, benefits of Moore’s Law scaling started diminishing, and a decision was made to end ITRS. The last edition of the ITRS was published July 8, 2016.
HI provides future directions
HI articulates state‐of‐the‐art advances in technology and science, and provides future directions, significant roadblocks and potential solutions. We have a roadmap for the next era of Moore’s Law. We are seeing the electronics industry resurgence, and that is decades into the future.
From 2022-2026, the total semiconductor market will grow almost 1.8x from 2019‐2026. It will be primarily fueled by server/storage/communications infrastructure and mobile phone/tablet segments. We will have advanced nodes for silicon. Chip architectures are dis-aggregating for cost and yield management. Silicon chiplet integration is enabled by advanced packaging technology.
HI is defined as the integration of separately manufactured components into a higher-level assembly (chiplets, SiPs, modules) that, in the aggregate, provides enhanced functionality and improved operating characteristics. Chiplet integration is becoming mainstream for HPC via advanced packaging platforms.
Today, we are at unique point in time when there is global recognition on critical roles of semiconductor and microelectronics as foundational pillars to the various nations economies. Heterogeneous integration through advanced packaging for chiplets and system-in package is crucial to achieve best optimal systems: performance, power, cost, reliability, time-to-market, and market penetration, paving the way for microelectronics resurgence for decades to come.
HIR twenty-three technical working groups, represent broad-based ecosystem for advanced packaging innovations. These range from package architecture and design, assembly, test, materials, equipment, tools, encompassing AI and ML. Basic research and collaboration across disciplines in HI (e.g. SiP and chiplets, and more) lays foundation for renaissance in science and technology, and microelectronics resurgence, in service to society and humanity.
HI interdisciplinary innovations
Dr. Xin Wu, Corporate VP, AMD presented on HI interdisciplinary innovations. Moore’s Law was designed to rebut contemporary claims that ICs were expensive and unreliable. FPGA capacity grew ~680x in 10 nodes, benefiting from Moore’s Law, hetero-integration, packaging, and new technologies.
Moore’s Law has since slowed down significantly. We need expensive solutions to keep it alive. We now have gate-all-around, EUV double patterning, SiGe channel, etc. Node-to-node mask/wafer cost increase can be > 30 percent. There is high design cost for new technology nodes. Advanced packaging and 3D integration can provide new opportunities.
Let’s look at semiconductor technology. Although silicon node advances continue, scaling has slowed down. Standard-cell-based library design kept (almost kept) node scaling. SRAM and customized design scaling has reduced to about half (or less) per node. Economic benefit of Moore’s Law was reduced significantly. Cost of manufacture and design increased from node to node. Hetero-integrations (HI) provide a chance to advance the semiconductor industry further for certain products and applications. Unlike Moore’s Law, HI provides many varieties of technology, each associated with its cost and suitable to certain kinds of applications. HI development requires multi-disciplinary innovations.
There remain key challenges of HI product. First, we have 3D stack technology itself. Next, architecture that benefited from HI connections and mitigates. We also have HI design, CAD, simulation flow and PDKs (including 3D modeling). Some other issues include software, pkg (I/Os) routability, signal and power integrity (SIPI), and power delivery. We also have to deal with thermal solutions, multi-chip production flow and testing, reliability, etc.
He gave an example of AMD CPU with 3D V-Cache using hybrid bond stacking. Design innovations and CAD flow for HI have continually progressed, but still have a long way to go.
Thermo-mechanical engineering is critical part of HI. Power consumption is also a leading cost factor in data centers. Thermal and mechanical solutions directly affect performance and power efficiency. It is one of the key STCOs or system technology co-optimization concept. SoC type system is dis-aggregated, or partitioned, into smaller modules (or chiplets) that can be asynchronously designed by dispersed teams, and later combined into a larger, highly flexible system using chiplet-based package design.
In summary, silicon scaling has been slowing. Costs continually increase from node to node. Hetero-integrations (HI) provide new opportunities. HI is not another Moore’s Law. They fit distinct applications differently, and also come with a cost. IC industry will continue to grow, especially in data processing areas (data centers, auto drive, 5G, AI) etc. Those who can target these areas to specific customers and applications and can provide solutions at better cost will fare better. Future success requires more inter-disciplinary knowledge and engineering.
Beyond Moore with HI
Dr. Moonsoo Kang, EVP, Advanced Package (AVP) Business, Samsung Electronics, presented the road to Beyond Moore with heterogenous integration for next-gen computing.
Why do we need ‘Beyond Moore’? There is an increased need for new solutions due to the slowdown of Moore’s Law, and computing power solutions. There are three challenges:
- Cost: Moore’s law slowdown caused by technical difficulty, while cost continue to increase.
- Performance: Power efficiency and bandwidth are limited by physical constraint of chiplets.
- Memory bandwidth: Bottleneck of system performance is memory bandwidth.
We need ‘Beyond Moore’ and heterogeneous integration to mitigate development cost, and to improve performance. Moore’s Law slowdown was caused by technical difficulty, while costs continue to increase. We can have cost reduction with high yielding smaller chips and optimal process selection. We also have die size challenge. Increases of die size are done for needs of high performance. ‘Beyond Moore’ can make it better!
Samsung has launched a new advanced package (AVP) business unit to meet the increasing importance of advanced packaging. It provides flexible services to customers leveraging Samsung Semiconductor’s synergy platform. Samsung AVP heterogeneous integration platform is key here.
Low-power memory integration platform fan-out package provides size, thickness, and thermal performance benefits. It enables smaller form factor with fine pitch interconnection. It is minimizing PKG thickness without substrate, and enhancing thermal performance with thicker die. Samsung provides both panel and wafer level fan-out package solutions. FOPLP has been in mass production since 2018. FOWLP will be in mass production from Q4-23.
Samsung provides wide I/O memory integration platform. These are used in LLW DRAM application, and RDL-based lateral multi-chiplet integration. Samsung also provides high bandwidth memory integration platforms I and II. I-Cube (Si-interposer or embedded Si-bridge RDL interposer) enables larger interposer, more HBMs. and multi multi-die for AI/data center applications.
Samsung also has the Integrated Silicon Capacitor (ISC) solution. ISC leads to decoupling capacitor competitiveness in component level. ISC production ramp-up with capacitor density (1,350nF/mm 2) is expected in Q3-24.
Future will have high-bandwidth memory integration platform. Memory and logic will be in highly-integrated SiP for next generation of HPC applications. Samsung’s logic 3D IC platform roadmap has X-cube that can integrate any configurations of logic-logic stacking optimized for performance.
Now, there are technical challenges, such as power and signal integrity (PSI). Power integrity challenges are jitter noise due to power coupling noise, and IR drop by high-power logic operation ( >1kW). A solution is integrated silicon capacitor, and integrated VR. Next, signal integrity challenges are signal degradation for higher speed IP (SerDes 112Gbps), and cross-talk noise by design complexity. A solution is the design methodology, and low-loss material.
We also have thermal congestion issue. For multi-chip implementations, there is thermal cross-talk and different thermal limits as challenges. A solution can be thermal-aware design. 3D multi-stack implementation issue is next. There can be accumulated heat and resistance. A solution can be joint thermal enhancement, and thermal-aware design.
Collaboration among partners’ specialty and Samsung AVP’s HI platform to overcome rising challenges of semiconductors is necessary.
Xilinx intros industrial and healthcare IoT solutions stack
Xilinx Inc. announced the industrial and healthcare IoT solutions stack today. It is a leader in scalable industrial IoT platforms, offering heterogeneous embedded processing, I/O flexibility, hardware-based deterministic control, and comprehensive solutions for lowest total cost of ownership. It powers intelligent and adaptive assets in harsh environments over industrial lifecycles.
Chetan Khona, Director of Industrial, Vision, Healthcare & Sciences, Xilinx, talked about building intelligent and adaptive assets. Xilinx is world’s first fabless semiconductor company. The industrial business has been growing quite steadily over the last few quarters. He gave an example of Siemens Gamesa. Xilinx is also looking at adaptable, intelligent hospitals and labs. Xilinx also supports the core technology of Olympus’ endoscopes.
More ISM customers are choosing Xilinx, with explosive Zynq SoC design win activity. Traditional role of Xilinx FPGAs are as companion chips for interfaces, such as custom I/O and industrial communications. It has since moved to Zynq UltraScale. An example is Sick AG, Central Europe, with sensor intelligence. Zynq SoCs enable total cost savings through substantial component integration and design re-use.
ISM market trends are industrial, vision, healthcare, and sciences that are embedded IoT and edge AI focused. There are connected factories and hospitals for electrification and efficiency. Also, smart cities for health and safety. ML for cameras, predictive maintenance, medical diagnostics, etc. Scalable platforms with scalable stacks, etc. IT-OT convergence, compute and control, etc.
Xilinx has evolved to an SoC company, and has not forgotten about FPGAs. It has the new UltraScale+ FPGA and SoC cost-optimized portfolio. There is new small form-factor packaging for industry’s highest compute density. An example is Triton Edge.
Xilinx is now seeing industrial and healthcare customers adopting scalable platforms and solutions to keep up with IoT timelines. It developed a one-stop-shop for all solutions needed for industrial and healthcare IoT design. It moved toward simplifying embedded design, and expanding deployment methods. Xilinx also have an app store.
Kria system-on-modules (SoMs) revolutionized edge vision AI inference. It is now expanding into smart cities, robotics, etc. Pantherun, a customer in India, uses own TCP/IP encryption chip IP on Xilinx FPGA with wire speed hardware security to provide rugged solution. Another company, Optimized Solutions Ltd, uses AI-based vision for multi-object detection, recognition, and identification.
There is an increasing role of AI in industrial, vision, and healthcare. Xilinx also has strengths in AI inference deployment, and industrial.
Looking back at semicon / tech in 2021!
We have finally reached the end of 2021! Let’s have a look at some of the breath-taking moments from the global semiconductor and technology industry during the year.
In January 2021, Dr. Anthony Fauci called for remembering Covid-19 lessons at PMWC 2021. I was invited by Dr. Leroy Hood, SVP and Chief Science Officer, Providence St. Joseph Health, Chief Strategy Officer, Co-founder, and Professor, Institute for Systems Biology (ISB), and Co-Program Chair, PMWC 2021. Dr. Fauci was presented the luminary award.
Malcolm Penn, Future Horizons, UK, predicted the global semiconductor market to grow 18 percent in 2021. Scotten Jones, President, IC Knowledge LLC, presented on logic leadership in PPAC era at ISS 2021. AI processors were said to be driving innovations in advanced packaging, as per Jean-Christophe Eloy, CEO and President, Yole Développement. At ISS 2021, semiconductor and equipment recovery were said to be on track for 2021.
Come February 2021, and Semiconductor Industry Association (SIA) had a session on memory semiconductors market and technology trends. At SEMI Flex 2021, there was a panel discussion on sustainability and power for batteries. There was a session on electronics for the brain, and another on liquid electronics for stretchable conductors. Next, European 5G Conference 2021 had a session on key drivers for 6G. IHS Markit presented on autonomous sensors and future apps. Erik Collart, Edwards, came up with an enlightening talk on smart manufacturing in More-than-Moore era at the SEMI Technology Unites summit. Embedded computing with image sensors was another.
Dr. Wally Rhines, CEO, Cornami gave his views on why FHE was ultimate for cyber security. Quantum computing is going to be next game changer. At an SIA summit, it was predicted that the global semiconductor industry could be worth trillion dollars by 2036. Elsewhere, in Europe, CEA-Leti has big bets on silicon-based quantum computing. It was announced IEEE International Reliability Physics Symposium (IRPS), will be held virtually in March 2021.
Bill Gates said green premium is metric that says you are on to success in 2050 at CERAWeek by IHS Markit 2021. In March 2021, there was a conference on RISC-V, and how China can reduce risks. Semiconductor outlook 2021 — navigating through turbulent times, came next, by SEMI. At the Technology Week Summit organized by SEMI, SAW/BAW filters, and future materials technology for new filters were discussed, which took me back to my days at Global Sources, Hong Kong, as were technological challenges for MOS HEMT GaN power devices. IRPS 2021 discussed memory’s journey towards future ICT world, and reliability of SiC MOSFETS. SEMI organized a conference on semiconductor outlook 2021 — navigating through turbulent times.
In April, I received shocking news. We lost Shankar Ghosh, or Keshtoda, to Covid-19! He was my guru from my young days. I recall my first ever article, at 14, published by him at Pragati Manjusha, Allahabad. Just a week back, we had lost Bachchu, or Subhash Ghosh, his younger brother. There was another very sad loss of Buluda, or Arun Chakravorty, our brother-in-law and a very close friend, due to Covid-19.
Next, USA started strengthening microelectronics supply chains, and with the CHIPS Act in place, looks well set to do so. The White House said: Resilient American supply chains will revitalize and rebuild domestic manufacturing capacity, maintain America’s competitive edge in research and development, and create well-paying jobs. Also, e-Estonia Digital provided masterplans on mobility.
6G’s chance for semiconductors, and skills for a digitalized Europe were also discussed at the SEMI ISS 2021 conference. Sensors and software were enabling autonomy for urban air mobility at the SEMI MSTC 2021 conference. Rockwell Automation discussed how Industry 4.0 can strengthen India’s pharmaceuticals sector. Cedrik Neike, Siemens, called for Industry 4.0 in silos needs to be brought together. At ISQED 2021, there was a session on the confluence of AI/ML with EDA and software engineering. Yole Développement, France, came up with global technology trends impacting optical transceivers market.
In May 2021, Arvind Krishna, Chairman and CEO, IBM, announced a major breakthrough on world’s first 2nm technology. It was built at the Innovation Lab in Albany, New York fab. At Display Week 2021, there was an engrossing Women in Tech panel on leadership skills. JS Choi, Samsung Display, talked about the metaverse and great future of display. Every display that maximizes immersion is part of the metaverse. Another interesting session was on start-manage-exit option for CEOs. Guillaume Chansin, Director of Display Research, presented on the opportunities in AR/VR for display manufacturers. Next, 6GHz emerged as the new spectrum battleground.
SEMI ASMC 2021 began with continuing Moore’s Law! Center for the Study of the Presidency & Congress (CSPC), USA, organized a conference on semiconductor shortage lessons for US innovation leadership. Digital Twin Consortium organized a webinar on how digital twin is making the vision come to life. Experts at INDIAai discussed the race to AI is just beginning.
Come June, and Ericsson UnBoxed Office had a session on the importance of network reliability from telco’s perspective. GSEF 2021 held a panel discussion around the generation and use of data in fab processing. There was the spectrum roadmap for Europe laid out. At the Leti Innovation Days, hardware is back, encapsulates role of microelectronics. At the VLSI Technology & Circuits 2021 conference, there was a panel discussion around new generation chip makers vs. incumbents. Here, Tesla made the first appearance. There was another discussion around 3D/heterogeneous integration: Are we running towards a thermal crisis?
At VLSI Technology & Circuits 2021 conference, Spintronics workshop suggested a gateway to green society. Hexa-X defining blueprint for 6G was hot topic at EuCNC 6G summit. Acellera and Electronic System Design (ESD) Alliance (EDA Alliance) co-hosted a conference on Remote work, remote chip design: Building chips during a pandemic. China Tech Threat’s co-founder, Dr. Roslyn Layton, hosted a virtual panel: Let the Chips Fall at BIS? It was also stated that real men own fabs that can re-invent the future! At the European Commission (EC) conference, there was the inauguration of the EllaLink optical submarine cable linking the European and South American continents.
In July 2021, the Center for the Study of Presidency and Congress (CSPC), USA, and National Security Space Program, organized a session on building space capabilities over the horizon. Cadence Design Systems introduced the Cerebrus intelligent chip explorer to revolutionize intelligent chip design. Elon Musk spoke at MWC21 Barcelona how SpaceX was keen on landing people on Mars. Antler Southeast Asia introduced 14 new startups at its demo day. Asia Tech X Singapore organized a panel discussion on deep tech for global good, at the accelerateHER Asia. There was a panel discussion on planes, trains, automobiles and ships: satcoms-on-the-move.
Islam Salama, VP, Intel, discussed more than Moore and heterogeneous integration through packaging at Global Semiconductor & Electronics Forum (GSEF) 2021. Dr. Wally Rhines presented the strong growth in EDA and trends in semiconductor design ecosystem at the SEMI Innovation for a Transforming World. Marco Chisari, Bank of America, Merrill Lynch, presented golden age or short-term cycle for global semiconductor market. There was Ericsson, scaling with 5G and edge computing.
In August 2021, there was a very painful and shocking development. My eldest sister, Ms. Shukla Mukerjee, lost her battle with the dreaded cancer, leaving us extremely distressed. Meanwhile, Ericsson was unlocking potential of 5G for consumers. There was SIA’s session on modern hardware and measurable security. There was a panel discussion on monetizing satellite apps, new business model with innovative use cases in connectivity at the Satcom Industry Association (India) conference.
In September 2021, Vladimir Roznyatovskiy, Lux Research, presented innovations in emergent displays at SEMI, Strategic Materials Conference (SMC) 2021. Role of innovations enabling consumer AR technologies was another. Chuck Byers, Industry IoT Consortium, presented top 10 disruptive new technologies for industrial and IoT networks. SIA had a session on US semiconductor industry facing challenges, and historic opportunities. Xecs Eureka cluster showed support for RD&I in the electronic components and systems. NASA’s flight to Mars via Ingenuity was showcased at Sensors Converge 2021. Lip Bu-Tan, CEO, Cadence, discussed harnessing analytics for electronics industry renaissance. Future Horizons predicted the global semiconductor industry to grow 24.5 percent in 2021. Ms. Taguhi Yeghyan, Market and Technology Analyst, Yole Developpement, presented MEMS and CIS: lithography and bonding equipment market state and outlook, at the Connecting Heterogeneous Systems summit, organized by SEMI Europe.
In October 2021, EMSNow India was launched, carrying my article on how the Indian electronics manufacturing is in a boom period. My blog was featured alongside Forbes and BusinessKorea on China Tech Threat! My thanks to China Tech Threat. SEMI organized a session on challenges in metrology and analysis for next-generation semiconductors.
CASPA, USA, discussed the semiconductor chip shortage, impact, and solutions. Ms. Carlista Redmond, CEO, talked about how RISC-V means an open era of computing! At MEMS & Sensors Executive Congress (MSEC) 2021, iSono Health gave an update on the increasing access to breast cancer screening. European Technology Platform for High Performance Computing (ETP4HPC) organized a session on how EU HPC centres are transforming industries. Yole Developpment, France, organized a conference on supply chain disruption and other MCU market trends.
SIA had a panel discussion on race for semiconductor supremacy: China vs. emerging democratic technology alliance. Indian Space Association (ISpA) was formally launched October 11, 2021. Tech women in space paving way for next generation was organized by Satcom Industry Association (SIA) India. Hydrogen producer, Lhyfe, from city of Nantes, France, started producing green hydrogen for life from seawater. Challenges in metrology and analysis for next-gen semiconductors was discussed at a SEMI conference. Indian Space Association (ISpA) announced its launch.
Following the USA’s Chips for Americas Act, now, Europe also joined the bandwagon with its Chips Act. EU is home to leading global semiconductor research institutions, such as IMEC in Belgium, CEA-Leti in France, and Fraunhofer-Gesellschaft in Germany. The US Chips Act also calls for the creation of a National Semiconductor Technology Center (NSTC), and an advanced packaging research institute.
SEMI, USA organized the Global Smart Manufacturing Conference 2021, where digital twins and software-defined manufacturing were discussed. SIA, USA organized another conference on catalyzing US semiconductor design ecosystem. This was followed by CAR-SEMI conference on chip shortage impact on automotive. The month closed with the state of AI in Estonia, and Global Semiconductor Alliance event on future of automotive computing: cloud vs. edge. Also, Semiconductor Research Corp. (SRC) and SIA discussed new trajectories for communication.
My article: It takes pure brains to work in semiconductor industry, generated lot of interest in Nov. 2021. EV World Congress 2021 looked at rEV index accelerating EC adoption. The cities of Madrid and Helsinki continued to ride ahead with e-mobility and EVs. At SEMI, USA conference, the global semiconductor market was predicted to cross $600 billion in 2022. Another session tried to address what’s behind the chip shortages, and what’s driving the current semiconductor markets?
December began with SEMI’s future of computing in 2040. At, Semicon West 2021, there were some interesting sessions. Rick Bergman, AMD, spoke about innovation beyond Moore’s Law: new era in gaming graphics. Kai Beckmann at Merck talked about shaping the future of electronics. VLSIresearch, presented on the state of the semiconductor market in 2022. Nanotronics unveiled the nSpec Turbo inspection tool at Semicon West 2021.
Next, SRC-SIA looked at the new trajectories for memory and storage. DVCon India 2021 looked at whether respins were a fact of life. The year closed out with Leti’s devices workshop in France, which looked at semiconductor solutions to speed up telecom revolution. There was a session on innovative BAW filters for 5G sub-6GHz. How I miss electronic components! I was probably the best editor at Global Sources for electronic components, visiting Shenzhen, Taiwan, etc., multiple times.
There you go! Let us hope that the semiconductor chip shortage will finally go away this year, and the semiconductor industry continues its onward march in 2022. We may get to hear more about FHE in the coming year. Perhaps, Tesla will come up with new factories, pursue energy and software, and grow even bigger.
Xilinx intros Alveo U55C data center accelerator
Xilinx Inc. has introduced the Alveo U55C data center accelerator today.
Neeraj Varma, Director, APAC and Japan Sales, Global Datacenter Business, Xilinx, said they are the inventors of FPGA. India operations were started in 2005. Xilinx has since grown significantly, with nearly 1,000 people based in India. It is currently no. 1 FPGA/SoC provider for aerospace and defense, no. 1 in FPGA-as-a-service on Amazon Cloud, no. 1 logic IC vendor in T&M, and has world’s first commercial new radio deployment in 5G.
Xilinx has adaptable hardware architectures. It introduced RF SoCs in 2017, and moved to adaptive compute accelerator platforms (ACAP) in 2018. It has had a track record of innovation over the years in hardware and software. The platforms are accessible to all developers. There are a range of deployment methods for customers, such as hardware adaptable devices, deployable end-systems, and FPGA-as-a-service (FaaS).
Xilinx is seeing evolution of the data center. There are rapidly evolving workloads and algorithms. Compute is moving closer to data with storage and network controllers. There is the adaptable acceleration for the data center. It has comprehensive software and hardware stack for all developers. There is a rapidly growing ecosystem.
Nathan Chang, HPC Product Manager, Data Center Group, Xilinx, said that as HPC pushes toward the exascale threshold, power consumption will be the next barrier. Typical HPC architectures will be hard pressed to deliver acceptable performance/watt. There are limitations with CPU and GPU Von Neumann architectures. Data movement challenges cause performance degradation. Data must be prepared in transit between functions to maximize performance. Rigid memory hierarchies create inefficiencies. The net result: wasted clock cycles, less work, more power consumption.
Breakthrough HPC architecture
Today, Xilinx is announcing a breakthrough HPC architecture. It is the most capable Alveo HPC accelerator card ever. It has a groundbreaking HPC clustering solution that enables massive scale-out across existing customer infrastructure and network. Full high-level programmability of both application and cluster is available. There is scale-out architecture on RoCE v2 and DCBx with existing data center server infrastructure. There is shared workload and shared memory across multiple cards. MPI enables hyper-parallelism of Xilinx adaptive compute across nodes.
Vitis unified software platform has domain-specific development environment, Vitis accelerated libraries and APIs, and Vitis core development kit. It enables the data scientists to create recommendation engines with lowtouch/no-touch coding. APIs for FEM developers help leverage custom data movement, with no hierarchical memory lock-in, and no cache misses. It is enabling scale out across converged Ethernet.
The Alveo U55C is purpose built for HPC and Big Data workloads. Many HPC workloads are either compute or memory bandwidth bound. I/O requirements expand exponentially over time. Power consumption is a huge issue in the data center. HPC needs gravity of compute and high-bandwidth memory. In response, Xilinx built the most powerful accelerator ever, and made sure it scaled easily.
There is more parallelism of data pipelines, superior memory management, optimized data movement throughout the pipeline, and best performance-per-watt. Xilinx adaptive computing for HPC involves clustering at massive scale, built for software developers, and has powerful accelerators.
HPC signal processing is via CSIRO, in Australia, the world’s largest radio astronomy antenna array. It is built to catalog the origins of the universe, requiring terabits/s of sensor data to be processed in real time. The solution: distributed processing across hundreds of Xilinx Alveo accelerators in real-time.
CSIRO is completing reference design to help other organizations achieve the same success. HPC also involves CAE Ansys LS-DYNA. LS-DYNA is the finite element program (FEM). It uses FEM to simulate real-world product performance. LS-DYNA allows designers and engineers the ability to create simulations with an infinite amount of complexity.
Large scale simulations take weeks on a CPU. The x86 architectures aren’t equipped to provide the high I/O and bandwidth required. CPU memory hierarchies are inflexible and that creates unnecessary overhead. The x86 architectures are inherently inefficient at handling data movement.
There is U55C hyperparallel data pipelining for LS-DYNA. Data is pipelined to simply stream between functions. Data is prepared in transit to achieve the maximum throughput. There are highly composable memory hierarchies — 16GB HBM2 memory, 32 HBM channels @ 460GB/s, etc. Workload is partitioned across multiple Alveo U55C cards. The result: 5x performance vs. CPU. U55C real-time graph insights indicated that real-time results demanded Xilinx acceleration. Tuned algorithms are required for important real-time graph use cases. The Xilinx U55C is available now.
The new Xilinx HPC clustering solution enables massive scale-out across existing customer infrastructure and network. The Xilinx Alveo U55C accelerator card, now shipping, brings superior performance per watt to HPC and database workloads, and easily scales through Xilinx clustering. Software developers and data scientists can unlock the benefits of Xilinx adaptive computing through high-level programmability of application and cluster.
Adaptive computing, with innovation accelerated @ Xilinx
Xilinx Adapt 2021 was held recently. Ivo Bolsens, Senior VP and CTO, Xilinx, presented on adaptive computing, with innovation accelerated, and shared the vision for an adaptable, intelligent world.
Adaptive computing is proliferating today. It is driving life-changing innovations across many areas. Hardware is adapted and optimized to the app. We embrace the concept of domain-specific architecture, and have an app acceleration. There is the growth of compute requirements. It has been doubling every 3.4 months since 2012. There is growth of memory requirements. New apps fuel model size growth to trillions of parameters. Larger models can solve more challenging tasks.
There is growth in communications requirements. There are high-level targets for 6G, such as 100Gbps-1Tbps peak data rates, 0.1ms radio latency, connected density of 100 devices per cubic meter, 100-fold increase in traffic, and 10 times more energy efficient.
Xilinx has evolved to a platform company. It has evolved to an adaptive compute acceleration platform (ACAP). It has now moved to peer processing. Onramp for all developers is now available. Eg., Vivado ML is helping increase levels of abstraction, and 10 percent average QoR gain. There is 5X average hierarchical compile time reduction. There have been 23,000 Xilinx Vitis AI downloads, and 76,000 Vitis downloads.
Computing has evolved to be deterministic, real-time, distributed, etc. Platforms are the key, covering data center, edge, and embedded. You can accelerate storage and networking. Data at rest looks at the SmartSSDs, while data in motion looks at the SmartNICs. FPGA-equipped devices can solve data-centric challenges. Xilinx is enabling the composable data center, with an adaptable intelligent fabric. Eg., today, Microsoft has deployed Xilinx across its cloud.
Xilinx AI engine is at the forefront of the adaptive revolution. The AI engine array has helped extend both multi-threaded and data flow architecture. It represents the next generation of adaptive technology. He also gave an example of Samsung, with whom it is in partnership. The AI engine has domain-specific variants. Xilinx has also worked with Pacific National Northwest Lab. James Ang, PNNL, gave a talk about E3SM or Energy Exascale Earth System Model.
Xilinx is now accelerating the whole app. In automotive, there is FPGA fabric for sensor fusion and pre-processing, AI engines for signal conditioning and low latency AI, and scalar engine for decision making and vehicle control. Xilinx is increasing access at the edge and endpoint. An example is the Kria SOM launch momentum. The demand was overwhelming.
Developer accessibility and productivity is essential. Software development platform for heterogenous systems is critical for broad adoption. Xilinx has announced extensions for Vitis and Vivado. We are driving our innovation to accelerate your innovation. These are being done across multiple areas, such as robotics surgery, gene sequencing, Mars Rover, etc.
Xilinx intros Versal AI edge ACAP series
Xilinx Inc. has announced the Versal AI edge ACAP series. Versal is an adaptive compute acceleration platform (ACAP). It is designed to enable AI innovation from the edge to the endpoint. With 4X the AI performance per watt and 10X greater compute density, the Versal AI Edge series is said to be the world’s most scalable and adaptable portfolio for next-generation distributed intelligent systems.
Rehan Tahir, Senior Product Line Manager, Xilinx, said there are things happening at the edge, such as low latency, AI compute, low power, and safety and security. Latency is the no. 1 reason, and compute has shifted a bit. There is also hypergrowth at the edge. Edge AI chipset opportunity is 3X that of a data center, that is, around $65 billion in 2025.
Xilinx is now bringing Versal ACAPs to the edge. Versal ACAP introduced the breakthrough compute for the cloud and the network. With the edge series, we are miniaturing the technology for performance/watt. Versal AI edge series brings intelligence to the edge. This can be used across smart vision, unmanned aerial vehicles, collaborative robotics, ADAS and automated drive, endoscopy, and ultrasound. We are in full production with TSMC, at 7nm.
Intelligence unleashed
Intelligence has been unleashed! There is 4X AI performance/watt vs. GPUs. There is 10X compute density with the highest levels of security and safety, and the world’s most scalable and adaptable platform for the edge and endpoint.
There is proven AI engine architecture. There is an array of compute core. Flexible compute is possible, with fixed- and floating-point vector processors. The hardware is adaptable to evolving algorithms. There is tightly coupled memory, with cacheless memory hierarchy, and flexible interconnect with high bandwidth.
There are optimized AI engines with ML. Xilinx has optimized the compute core for ML, doubling the multipliers and INT8 performance. There is native support for INT4 and BFLOAT16. We have doubled the data memory and added new memory tile. AIE-ML complements the AI engines for diverse workloads.
Another innovation is the innovations in memory hierarchy, the accelerator RAM. There is 4MB on-chip RAM for massive bandwidth. It is part of the adaptable memory hierarchy. You can select the right memory for bandwidth requirement. There is also 4X performance/watt improvement vs. GPUs. AI is part of the whole app, so there are adaptable, intelligent, and scalar engines.
An example of Versal AI edge ACAP in ADAS and automated driving was shown. Adaptable engines are used for sensor fusion and pre-processing. Intelligent engines take care of signal conditioning and low-latency AI, etc. Versal is architectured to meet the stringent ISO 26262 requirements. Besides, there are IEC 61508 and DO-254/178 certifications, as well.
Another example was of collaborative robots, where AI-based systems need to be secure and safe, especially in the Industry 4.0 scenario. There is real-time precision and control to augment AI, environmental awareness and perception, and predictive maintenance. Safety and security are connected matters. The market-specific app stacks include automotive, robotics, and multi-mission payload apps. There is one platform for market-specific libraries, frameworks, etc.
There are domain-specific architectures (DSAs) adapting to the dynamic function exchange. Through DSAs, you can update your algorithms. An example of dynamic function exchange (DFx) was shown for automotive. There are fewer devices to reduce system-wide power and cost.
Finally, you can also scale from the edge sensor to the CPU accelerator. Versal AI edge is the only AI platform that scales from sensor to accelerator on a single architecture. You can also scale for different requirements and product features. Tools for Versal AI edge portfolio will be available in H2-2021. End silicon and production silicon will be available in H1-2022. You can start now with the Versal AI core ACAP VCK190 evaluation kit, and migrate later to Versal AI edge device.
USA strengthening microelectronics supply chains
Semiconductor Industry Association (SIA) and Intelligence & National Security Alliance (INSA) hosted a session on the threat of foreign interference with microelectronics supply chains. They looked the ways in which defense and intelligence agencies work with the US companies to mitigate the supply chain risks posed by imported microelectronics components, and the merits of increasing computer chip manufacturing in the United States.
Opening the conference, Chuck Schumer (D-NY), Senate Majority Leader, and member of the Democratic Party, USA, said this is a time of profound challenge. Vaccines are now making their way across the country, and more people are getting vaccinated. However, we cannot be satisfied with business as usual any more. USA has been is a leader in scientific research, and is under pressure from nations, such as China.
We are trying to solidify USA’s leadership in science and technological leadership in the years to come. We are also pushing thousands of dollars for semiconductor R&D and manufacturing. All of you can reach out to Senators and Members of Congress for action and guidance.
Mike Orlando, Acting Director of the National Counterintelligence and Security Center (NCSC), delivered the keynote remarks focused on supply chain threats. Covid-19 posed a wake-up call for the supply chain. It is the network of people, process, technology and information that deliver a product. Components have to be moved from factory to factory.
There are thousands of parts that also get into a jet. F-35 has a supply chain challenge that is being overcome. Covid-19 pandemic caused shortage of PPE equipment for healthcare works. Suez Canal blocked global shipping that caused considerable damage to shipping. There are folks who pump malware into network so they can sabotage them. We’ve seen Chinese hackers target a cloud service provider. Russia has also used supply chain attacks vs. the US energy sector. Cyber and supply chains are two areas we are concerned about. Those are the threats we need to focus on. Besides China and Russia, there are other nations such as Iran and North Korea who also can do cyber attacks.
Maintaining access to companies
Semiconductors are touching all aspects of our lives. They are also instrumental in transformational technology. We have a global supply chain. This has, however, created some vulnerabilities. There is also some loss of trust.
Compromised and counterfeit chips have appeared in the past in the USA. We have had cyber IP theft. A Chinese chipmaker hired several guys from a competitor. There was a massive IP theft, thereafter. The Chinese can become self-sufficient! However, you need to ensure that your cyber defenses are very strong. The global semiconductor supply chain also runs through many countries. Unless the US maintains the access to companies, we cannot maintain our position. There was an executive order recently. A number of government departments also came up with their recommendations.
We can take a number of steps. We can also build diversity, resiliency, etc., in our supply chains. You also need to also understand the security of your partners. You need to train your employees to have greater awareness about security. This problem will only get worse if we do not act now. Our nation depends on it.
Diverse supply chains also mean finding new suppliers. We need to have conversations with trusted overseas partners. We also need to ensure that semiconductors in critical setups are not compromised. There are also a number of issues with supply chains in some countries.
Migration of manufacturing from China to Vietnam and other countries is interesting. We need to define what should be made in America. We also need to have trusted allies. We are looking at critical infrastructure. We need to ensure that we are protecting those. The US government also needs to do a better job of sharing information with the private sector. We brought in some companies from quantum computing. Private sector has their concerns about sharing their information, as well. China still has a lead in lot of key components. We need to look at the alternate sources.
Supply chain reliability for microelectronics
There was a panel discussion regarding the supply chain reliability for the microelectronics industry. The participants were Cameron Chehreh, CTO and VP Pre-Sales Engineering, Dell Technologies Federal, Russell Ellwanger, CEO, Tower Semiconductor, Dr. Carl McCants, Technical Director, Supply Chain and Cyber Directorate, NCSC, and Ms. Claire Sanderson, Legislative Assistant, Office of Sen. John Cornyn. John Neuffer, President and CEO, Semiconductor Industry Association, was the moderator.
Neuffer said that there have been disruptions caused by the pandemic. Chips have a role to play across all sectors of our economy.
Dr. Carl McCants said there was an event 9-1/2 years ago regarding counterfeit parts. These were parts that don’t operate as they should. We have a global interconnected supply chain. We are also seeing the interest from China. Any challenges to the national security are a problem.
Russell Ellwanger said that the USA can lead via technical leadership. We must have US domestic R&D capabilities led by US citizens. Foundry capability is paramount. At foundries, great ideas are taken and put into practice. We need to have IP capabilities. The DARPA awards were held recently. Tower won two of those awards. We need to have R&D tied to domestic advanced facility. We can also talk about IP protection. When you have a high-tech company, you can really drive the dreams of the middle class. You also allow them to grow and thrive.
Cameron Chehreh added supply chain is paramount. A lot of the unclassified trade craft have had critical value proposition. Pandemic saw the global shutdown. We were able to get 90 percent of our facilities back online within a month. Today, we are transitioning to work from anywhere scenario. Supply chain is the key for us. We have to build resilience in the supply chain.
Encourage semiconductors production in USA
Ms. Claire Sanderson said the pandemic illuminated the many supply chain shortages. Eg., PPE equipment. We need to encourage the semiconductors production in the USA. CHIPS for America allows $3 billion grant to companies. We targeted the vulnerabilities with semiconductors. There are also lab-to-fab investments that need to find the way into the commercial sector. There is lot of bipartisan support. Republicans and Democrats can come together to address the national security issue regarding semiconductors.
By enacting the CHIPS for America Act in the FY 2021 National Defense Authorization Act (NDAA), the Congress recognized the critical role the US semiconductor industry plays in America’s future. The Administration and the Congress must fully fund the semiconductor manufacturing and research provisions authorized by the NDAA — and enact an investment tax credit — to strengthen America’s global leadership in chip technology for years to come.
The White House has done a supply chain review. On February 24, 2021, Joe Biden, US President, signed an Executive Order on America’s Supply Chains. The opening paragraph states: The United States needs resilient, diverse, and secure supply chains to ensure our economic prosperity and national security. Pandemics and other biological threats, cyber-attacks, climate shocks and extreme weather events, terrorist attacks, geopolitical and economic competition, and other conditions can reduce critical manufacturing capacity and the availability and integrity of critical goods, products, and services.
Resilient American supply chains will revitalize and rebuild domestic manufacturing capacity, maintain America’s competitive edge in research and development, and create well-paying jobs. They will also support small businesses, promote prosperity, advance the fight against climate change, and encourage economic growth in communities of color and economically distressed areas.
Dr. Carl McCants said that we need to figure out where the gaps exist. Ms. Clair Sanderson added they have reviewed the areas that need addressing. There are actionable items in the review. Each supply chain is different. Congress is helping authorize what needs to be done. Chehreh said the review presented opportunities and focus. Great things happened with innovation in the USA. We need to take a balanced approach.
Russell Ellwanger congratulated Ms. Sanderson and her team. He stressed on the need to understand the importance of analog manufacturing. R&D and manufacturing are important. We have to take strong consideration of cultures. The UMC-Micron collaboration for stealing secrets was an example. UMC was fined US$60 million for helping the Chinese company steal trade secrets from US memory producer Micron.
Ellwanger added that we also have to look at corporate governance and focus on business continuity. We have to understand that R&D can also partner with DoD, and other suppliers. We also need to have a legislation regarding who is being funded, and in which country.
The US Congress is pushing for more US manufacturing. Ms. Claire Sanderson said its unrealistic to imagine the supply chain to be residing entirely in the USA. Secure supply chain means you have resiliency and redundancy. We do not want all our eggs in one basket. Demand for semiconductors will only grow. We need to bring back fabs to the USA. There will also be plenty of manufacturing in Europe and Southeast Asia. The USA also needs to get in the game.
Chehreh said that everything should be in balance. You need to have economies of scale by manufacturing around the world. Diversity is more than just a tagline. Innovation can come from anywhere. We also need domestic manufacturing. You need to have a balanced approach to the global context.
Ms. Sanderson added that USA cannot do it alone. We also need to work with allied countries. If we can keep the allies close, that only helps the USA. The CHIPS Act has a transparency with allied countries.
Ellwanger said culture is very important for any decision. A factory has characteristics of efficient, quality and effectiveness. You cannot legislate where innovation comes from. There is an absolute importance of world citizens. The innovation happening is quick, and with the end state in mind. We also need to have good R&D and manufacturing. Taiwan, South Korea, and China have been very active. We also need to have the initial momentum against the capital investment.
Ms. Sanderson added there were lot of efforts to ensure there were cutting-edge technology. The needs of the US economy and national security does not always use cutting edge. We need to ensure we are technology neutral. Technology policy really limits the innovation. Ellwanger added we need to have cutting-edge technology. What we do in analog is very cutting edge in nature.
Dr. McCants said there needs to be strategic vision. We have leading edge for memory, analog, and mixed-signal. We also need to look at photonics and power electronics. R&D ties all these things together. We need to look at the capabilities that we already have, and bring in modern manufacturing paradigm. We have made some progress. You are buying things such as FPGAs, memory, etc. We need to make efficient use of aggregated volume and make the best use of them.
Chehreh added that DoD takes steps to ensure we feel safe with various things. DoD is also consuming hyper electronics. Ellwanger noted that there are specific needs of DoD. It also moves on to aerospace and defense business, if needed. DoD funding and DARPA funding is an enablement for the industry.
Ms. Sanderson said that there will be lots of chips getting made in the USA. That will also help strengthen the supply chain. Carl McCants added that having the infrastructure for future technologies is also very important.
Xilinx accelerating hardware development
Xilinx Adapt: Vivado conference began in the USA today. There are sessions on verification IPs, traffic generators, simulation models in RTL and transaction level, etc.
Satyam Jani, Senior Product Manager, Xilinx, presented the simulation scope, such as AIE simulation, HLS co-simulation, QEMU, and hardware emulation. The Xilinx Versal ACAP simulation allows simulating invidual blocks or the entire system. The simulation choice is based on scope and abstraction. There are supported flows in Vitis and Vivado.
Verification IPs and traffic generators are used extensively. There is AXI VIP and AXI Stream VIP protocol checker support. Versal CIPS VIPs allow functional verification of control interfaces, and processing system (CIPS). It allows verifying PS-PL interfaces and OCM memories. Simulation libraries are for behavioral, functional and timing simulation. There are pre-compiled simulation libraries for XSIM. TLM model support is meant to reduce the simulation time.
Xilinx simulator (XSIM) is a home-grown simulator with no design size limitation. There is support for UVM 1.2 and functional coverage. XSIM SystemC is a mixed language simulation support for SystemVerilog and SystemC. There are pre-compiled SystemC models.
The integrated simulation flow covers from behavior to timing simulation. Compilation and simulation time are important. YOu can expand the verification environment with VIPs and TCL store apps.
Matt Piazza, Senior Product Management Engineer, Xilinx, presented on hardware debugging. There are fabric debug and hard block debug. UltraScale+ has new entrants such as IBERT GTM that debugs and characterizes for 58Gbps PAM4 transceivers. HBM monitor is also present. There are debug objectives for Versal, such as system-level visibility, higher performance, and flexibility. Debug packet controller (DPC) enables multiple access options.
Intel FPGAs enabling industrial automation and Industry 4.0
Takayuki Ikushima, Market Development Director, Industrial & Automotive Business Unit, Programmable Solutions Group, Intel, presented a session on Intel FPGAs enabling industrial automation and Industry 4.0, at the Intel FPGA Technology Day 2020.
Industries are going through transformation. There is now an evolution to smart factories. These are enabling downtime reduction, improved product quality and optimized operations. As per a Capgemini study over 70 percent of manufacturers have a smart factory initiative. FPGA flexibility, connectivity, and performance enable smart factory applications.
FPGA in Industry 4.0
Industry 4.0 presents more flexible and connected architecture. This opens the opportunities for implementing intelligence. Evolution to smart factories are happening in multiple phases. You need to connect the unconnected, be smart and connected, and move on to autonomous. Smart and connected devices are making their way to the factories.
Intel CPU is a major player in the industrial IT market. Intel FPGA is a market leader in industrial OT market. Together, they are driving IIoT transformation for Industry 4.0.
There is a role for FPGAs in the Industry 4.0 paradigm. Applications exist for vison-based, robotics, motion control, sensors, etc. Intel FPGA can provided TSN switch implementation. Many industrial apps now connect to the cloud for data logging, analytics, remote management, etc. Over things, edge, and cloud, FPGAs can combine many apps.
The Edge AI acceleration solutions from Intel include Corerain Nebula accelerator and the ATUS, or CVDL-m9A miniPCIe card. Cirerain is a high-performance, low-latency, and high-cost efficient AI acceleration solution. ATUS is a deep learning-based edge vision AI inference accelerator using Cyclone V FPGA.
An MLOps demo was done with AWS and LeapMind. Sample MLOps system was used to prove remotely-managed AI service for embedded IoT apps. LeapMind’s Blueoil and AWS components, such as AWS IoT Greengrass and Amazon SageMaker. It enabled multiple FPGA-based AI devices on the field to be managed and remotely updated by AWS Cloud.
Intel offers the portfolio for all three robotics activities, sense, plan, and act. At the sense stage, there is the depth camera and workload/AI accelerators. At the plan stage, Intel processor family is used. At the act stage, there are embedded FPGAs. There is also a drive-on-a-chip for robotics and drives. The reference design is an integrated drive system of single- and multi-axis field-oriented control (FOC), supporting concurrent control of upto four permanent magnet synchronous motors.
There is the TUV-certified IEC1508 functional safety data package. You can now reduce the time for functional safety certification. This includes devices, docs, IPs, and tools. A success story was the Yaskawa YRC1000 robot controller in Japan.
Among the reasons for selecting Intel FPGA were integration of custom logic, PCIe, and software applications, low-power for fanless system, monitoring position data of the encoders and cross-checking by FPGAs, reduced development time compared with ASIC, with programmability, shorter certification turnaround time, etc.
Intel offers supported protocols and IP partners. There are Intel FPGA-based time-sensitive networking (TSN) solutions, along with off-the-shelf solutions. There is the IIoT edge controller and gateway, as well, such as the eXware 707T. There are system-on-module (SoM) offerings, as well. Intel also offers the FPGA cloud connectivity kit. The base kit is certified for Microsoft Azure and qualified for AWS Greengrass.
There is the TLS 1.3 hardware security IP core from Xiphera in Finland. The cryptographic computations and key management are entirely FPGA-based, enables complete independence from software for security-critical apps.
Another solution is DOME, the IoT secure ownership management solution, from Veridify Security, USA. It offers low-touch onboarding and the end-to-end blockchain ownership management for globally distributed devices at the edge.
Let us all make smart factory for real!
Xilinx on future technologies of 5G wireless
Day 2 of the Xilinx Adapt: 5G event began with a presentation by Brendan Farley, VP Wireless Engineering & MD EMEA, Xilinx. He spoke about the future technologies of 5G wireless.
There is the disaggregated 5G radio access network, by 3GPP and O-RAN. If we look at the new radio units, mmWave technology is very sensitive to the channel. It needs to be easy installation, with low costs from the operational side. The hardware needs to be cost effective. On the DU side, operators are tied into OEMs. The objective is to move to a server-controlled open approach. The partitioning between the DU and radio unit is key.
The view from the base station gives one of massive MIMO. Viewing the city scape, there is direct line-of-sight access available in most areas. We get the capacity increase by re-using the frequency. Beam forming gets visualized. Services such as video streaming, AR/VR. remote health consultation, etc. are being offered.
There is need to upgrade the existing 4G sites with 5G mMIMO panels. You need to minimize the hardware TCO. This can be done by virtualizing the baseband and centralize to support multiple radios. Advanced silicon technology and integration will be needed. You also minimize the opex. There is need to maximize the RAN performance and capacity. You can also increase the bandwidth, optimize baseband with radio partitioning, and optimize the 5G operator services through acceleration, virtualization, and O-RAN.
In terms of the radio panel power, weight and cost optimization, there is the 320W 64TRX mMIMO panel. It can host increasingly powerful DPD algorithms to linearize the power efficient GaN PAs. GaN has been used successfully in China. You can also reduce the panel heatsink weight through RF power reduction. You can also drive lower TCO by utilizing the most advanced silicon technology with flexibility to enable future 5G/O-RAN system evolution.
GaN power amplifier (PA) technology has been linearized with the Xilinx digital pre-distortion (DPD). We have created powerful PA algorithms that run on the Xilinx FPGAs. The issue with GaN is long-term memory effect.
Although, the improvements in LDMOS amplifier characteristics allow for frequency ranges up to 22 GHz, GaN-based amplifiers achieve frequencies up to 30 GHz at power densities up to five times higher, although at higher prices than LDMOS devices.
As for the form factor/weight of O-RU design, Xilinx lidless yields 28-degrees C improvement over traditional lidded design. Chinese OEMs are now incorporating lidless technology in 5G mMIMO panels.
Advanced silicon integration
Advanced silicon integration is done on Xilinx Zynq RFSoC DFE (digital front-end). There is over 2X compute for powerful DPD and upto 400MHz bandwidth. There are hardened and configurable functions for power and cost. Programmable logic also enables customization and future adaptability.
There is increased flexible compute, while reducing TCO. Use cases will definitely evolve over time. Base stations can adapt with the Zynq RFSoC DFE. There can be hardened DFE cores in 5G phase 2. Rel 18 will have adaptable logic as the standards evolve.
You can also scale for capacity. There are studies conducted by Ericsson. In India, the 32TRX seems to have found a sweet spot. The 64TRX has found space in China and Korea.
For O-RAN and O-DU virtualization, the O-RAN defines the functional splits between O-DU (baseband) and O-RU (radio). We anticipate the further migration of functionality to O-RU. Equalization, channel estimation, etc., are associated.
There is the 5G mMIMO UL performance challenge. MIMO decoder channel correction performance is dependent on factors. There is the beamformer discrimination performance. There will be future UL performance solution. There will be improved UL beamformer performance. It is essential to have a system that is adaptable and programmable.
The Xilinx 7nm Versal ACAP platform is adaptable technology for next-gen 5G beamforming systems. The capacity, compute and performance is 5X than the 16nm device.
In conclusion, the first wave of 5G has provided a clear picture of success metrics and challenges for the next wave. Advanced technology is essential to realize the 5G vision of higher capacity and improved services in an economically viable manner. Next-gen Xilinx technology provides an adaptable platform.
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