Electronics manufacturing
Advanced materials for industrial leadership key for Europe
European Research & Innovation (R&I) Days was held recently in Brussels, Belgium.
At the Advanced Materials for Industrial Leadership session, Marc Lemaître, Director-General for Research and Innovation (RTD), European Commission, delivered the opening message. Advanced materials are used in many things, which we don’t even know. It is used for renewable energy, lighting, etc. About 70 percent of renewable energy is based on all-new advanced materials. Even AI, computers, etc., would not be performing, as they are today.
Europe has been the world leader in materials science. Do we turn this leadership into an advantage? We have a comprehensive and compelling agenda to get to that. We need to create dynamic, secure and focused ecosystem for advanced materials in Europe. Second, we need to align R&I objectives along the priorities. Third, we need increasing public and private investment. Fourth, address the demand side. Fifth, attracting and training the best talent.
Stellar success!
Prof. Luc Langer, MD Materia Nova, Belgium, said that we are in process of development of new advanced materials. We have project Stellar. We had a workshop on advancing insect contamination mitigation for laminar wings: Innovations in coating and testing technologies.
We developed nice, smooth surfaces to reduce the friction coefficient. These surfaces are very optimized. They have to be protected in time. The nice properties have to remain available over the lifetime. We had goal of developing surfaces and coatings that can be protected over time. We had academic scientists understanding material science what’s needed to be done. We also had industrial partners. Our obsession is: how can we accelerate discussion between academic materials scientists and industrial companies.
We went ahead, doing tests on the industry floors, and not in the lab, to validate the coating. We were very lucky to have an airline partner who was willing to put coating on the plane. Today, we have planes flying with this coating. If you can have the entire value chain — from scientists to end users — that really speeds up projects and development. We can now deliver new coatings in several other sectors, as a learning. EC should look at how can we use the knowledge and develop for other sectors.
Sabine Klauke, CTO, Airbus, stated that we saw the weight reduction potential. The project brought us closer to our environmental objectives. There were 14 industrial partners. We were looking to make the coating industrially reliable, and also viable. We need the overall ecosystem to produce it.
We also had graphene and systems orientation. We had graphene-based technology for very lightweight, electrical aircraft. We went from the technology readiness level or TRL-1 to TRL-4 and TRL-5 in about three years. We now have examples where materials are going into real applications.
Clivia M. Soyomayor Torres, DG, International Iberian Nanotechnology Lab (INL), Portugal, said that we find it fascinating to see use of materials for surfaces. We also need to take the knowledge to the other sectors. We are not learning from what we have learned before. Knowledge takes 10-20 years to be developed to a product.
Europe and ecosystem for materials
So, how is Europe going about in developing an ecosystem for materials. Klauke said materials are core for businesses. We also have strong requirements. We partner in the latest technology development and supply. Public-private partnership for advanced materials is really important to us.
Regarding challenges, we now need new performance materials. We need lighter systems and structure, leading to reduced fuel consumption. That consumes 97 percent of our CO2 footprint. Next, we need new materials for development of batteries, fuel cells, electronics, new systems, hydrogen environments, etc. We need joint work on the industrialization process and supply chain risks. Future supply chains will need cooperation from new bodies to secure safer supply chain.
We also need to scale up new materials. We need to work on joint loop and recycling. We need partnerships with industries and players for critical materials supply and guarantee of materials via digital means that can be adopted across the full chain. We need to step up with this. Joint platform on data sharing across the EU will ease the problem of traceability.
In Germany, there is a digital platform that supports data sharing across the country. We have to build such examples across Europe. We also need to have policy for recycling of composites. We need to develop smart management of resources within Europe. Eg., the German Bundesdatenschutzgesetz (BDSG) is a federal data protection Act, that together with data protection acts of German-federated states and other area-specific regulations, governs the exposure of personal data, which are manually processed or stored in IT systems.
Prices of materials are only going to increase in the future. Some of them can also become hard to get. We also need to comply with regulations, and also look for alternative materials. Cooperation remains key, along with EU support. We also need companies and academia to access and assess new materials. Aviation, as against construction and transportation, is minor. We can cross breed and develop new materials, as well. She thanked the EU Commission for supporting new materials, and aviation sector.
Clivia Torres added that we need to look at value chain and process development that involves some of the ideas for next-generation materials. We must be scouting and testing for new materials. We need to work on partnerships among equals.
Scientists have a passion for knowledge. We need to make things useful for the industry and usage. We can develop this further, and possibly have a string of solutions for the day after tomorrow. Langer added we also need to involve SMEs. We need to create new platforms for use. In the ecosystem, SMEs can have tools that can help them scale up and develop new materials.
There is strong fragmentation of R&I programs among the member states. What is needed for dynamic cooperation? Torres said the the fragmentation is also on how we produce and communicate knowledge. This knowledge is generated by knowledge. We have to pass the motivation to the younger colleagues for the future.
It all needs a level of trust. People can take knowledge up to different areas and levels. We can have best possible understanding. Consortia approach has been good. There are networks of excellence. We have large projects with companies. We are taking bits that can be accelerated. We need to have pool of ideas of knowledge, and look at what needs to be accelerated. We can benefit from the accumulated knowledge that we have since gathered.
Memories of a project are also very important. We need have better coordination, trust, mutual respect, motivation, etc. That way, we can further harvest our knowledge.
Lemaître noted that we have to make the European leadership in advanced materials happen. We need to take steps, such creating an Advanced Materials Technology Council. It will facilitate cooperation among all the players.
Why is India the next manufacturing hub?
Supply Chain Resources Group (SCRG), USA, organized a webinar today on: Why India is the next manufacturing hub?
The participants were Saurine Doshi, AT Kearney, Arun Kumar, Celesta Capital, and Mahesh Krishnamurti, SCRG. SCOOP founder, Philip Stoten, was the moderator.
So, what makes India the next manufacturing destination? And, why now? Kumar, Celesta, said there is a global value chain and dangers of concentration. Second, we have the geopolitical situation. Third, rise of local presence.
There is hyper-specialization of manufacturing landscape, driven by globalization. About 25+ percent of manufacturing is located in China. There is now a concentration risk. Pandemic was a wake up call. The world now needs multiple sources of supply. China was also becoming a geopolitical risk, globally. People started looking at services beyond China. Companies in the regional supply chains also started improving. India scores quite well, and is trusted by lot of countries. Manufacturers are seeking other locations. China also does not want to play in the low end.
India now has a great opportunity. Medium tech sector is showing promise. GoI is also pushing to move to the hi-tech intensive end. RSAP is dominated by China. India is now beginning to have free trade deals with Europe, Australia, etc. India’s import tariffs are also quite high among emerging markets. With GST, we are having a one, common market. India has also handed strong incentives, starting from the Covid-19 period. India’s digital public infrastructure has also developed.
Doshi, Kearney, added that we have seen the CHIPS Act in USA has seen bringing back leading-node chips to the USA. There are opportunities in lagging node technology. India has the advantage. Tata has signed a tech license with Powerchip, Taiwan. The environment in India is getting better. We will see green shoots around them.
Krishnamurti, SCRG, noted that India is well-positioned to becoming a major port maritime shipping hub. India also has got the global trust back. Around 1.4 billion people represents a very large market. There is significant demand for smartphones, and India is also the second-largest maker. There is a huge demand for automobiles. We also have edutech, healthcare, etc., that provides a huge demand. It has a growing appetite.
Doshi, Kearney, said 10 years ago, exports was the primary focus. Krishnamurti said India has passed through the pandemic, and had the need for advanced electronics. There is a much larger middle class coming up in India.
What will be the impact of elections that could see some slowdown? Doshi, Kearney, said we should be concerned more about manufacturing. Things should continue as usual, in India. Kumar agreed, adding there is an interesting legislation on labor laws. Momentum will be maintained, irrespective of the results. Krishnamurti added that continuity is very important for the supply chain. The economic growth train has already left the station.
Key areas for electronics manufacturing
Where should India be thinking in terms of the geography? What are the key areas for electronics manufacturing? Kumar, Celesta said that India is spreading out electronics manufacturing. We have units coming up in Assam and Gujarat. Tamil Nadu has emerged as a hub. Bangalore, Hyderabad, Baroda, Ahmedabad, etc., have also come up. We are also looking at the talent resource. Clusters can be used by talent. We already have about 1600 GCCs in India. It all depends on the sector.
Doshi, Kearney, added that MNCs are going to Gujarat, Tamil Nadu, Karnataka, etc. All state governments are keen on developing and getting business. Memory, storage, semiconductors, etc., can be part of that. The USA is trying to set up an ecosystem. India can also do that via special economic zones (SEZs). We will be getting the ecosystem of products very soon. Semiconductors and memory requires special skills, and there will be lot to learn. We also have some JVs coming up.
There are supply chain ecosystem issues as well. Regions in Guadalajara, Mexico, is one such example. What’s happening in India? Krishnamurti noted that the Government and states are providing sufficient incentives. Micron is now in India. Tata is starting a fab in India with Powerchip. We are also seeing ATMP and OSAT facilities coming up. These will create ecosystems across the chain, including water supply, electricity, etc. Mumbai, Gujarat in the west, and east zones, are being developed. We need to make this pan-India, and achieve equilibrium and balance. Collaboration between the academia and corporations is also very important for talent.
Regarding talent, Kumar, Celesta, said there are elite institutes across India. Companies are also investing in them. We need to ensure quality education is maintained across schools. It is not yet a situation like China. We need to improve this further. China knows how to set up manufacturing at scale. India is not there yet. We also have many job seekers. We need better education and job development.
Doshi, Kearney, added that roads, railways, road and water transport have all improved across India. It needs more SEZs across the states. He noted PSMC signed a licensing agreement with Tata. Incentives are also there. We can say India is set to scale up from infrastructure, talent, perspectives, etc. India has the dominance here, and it will change in future.
Achieving in India
India also has the size in terms of talent, size, etc. Infrastructure has allowed China to stay there. They still have a domestic market to retain large footprint. Regarding how easy it is to enter India as a foreign OEM, Krishnamurti said there are JVs happening, with contract manufacturers, as well. Diversity of India is very huge. There can also be chaos in India, as sometimes, there are both carts and cars on the road.
People should first understand what they are looking to achieve in India. We have to look at products and services, and their needs. We can align those with specific sectors. We need to do good due diligence. There are many organizations who have partners on the ground. They can always relay feedback
Doshi, Kearney, added that when customers make a mental leap, there is still a challenge at which things are done. It is becoming faster. We also need to have sense of when things can go live, and can they be relied upon. Stability is also a big issue. More companies feel that it is becoming good. We will also gain in speed over time.
Kumar, Celesta, said there are large companies with alternative sources for manufacturing. If a sector is aligned with the government, it can speed up things, look at tariffs, etc. They can also sit down and help, if required. It is becoming easier to do business. Krishnamurti added that things are improving, We are highly cognizant of the potential. Invest India is helping folks come and manufacture in India. We have the experience and speed.
Finally, what will happen in the short term? Kumar said we are in the early stages right now. Global manufacturing opportunities are enormous. It is going to speed up. Doshi said it may take 5 years to scale up. We also need to factor in the importance of global and local markets. Krishnamurti said the intent is there. There is no turning back. We will see demand for electronics and semiconductors grow. The flywheel is now moving.
GBIP looking to expand semiconductor collaborations with Taiwan
Global Business Innovation Program, UK, organized a semiconductors event with ITRI, Taiwan.
David Campbell Molloy, Partnership Manager Asia, Innovate UK, presented the Global Missions Program. Innovation is the key to UK’s future growth and prosperity. Talking about Innovate UK and EPSRC within UKRI, it is the UK’s Research & Innovation agency. It is a key delivery body of HMG’s R&I policies and strategies. We support academic research and business.
Innovate UK mission is to help UK businesses grow through the development and commercialization of new products, processes, and services, supported by an outstanding innovation ecosystem that is agile, inclusive, and easy to navigate. Engineering and Physical Sciences Research Council (EPSRC) mission is to support new ideas and transformative technologies that are foundations of innovations that improve our economy, environment and society, by investing in world-leading research and skills.
Innovate UK global programs to support businesses include Global Scoping Workshops, Global Expert Missions, Global Explorers, Global Business Innovation Programs, Global Incubator Programs, and Bilateral and multilateral R&D&I funding programs and access to Horizon Europe.
In Nov. 2022, a five-year MoU was signed between Innovate UK and the Department of Industrial Technology, Ministry of Economic Affairs, Taiwan, with commitment to strengthening joint R&D opportunities. Industrial Technology Research Institute or ITRI is the main delivery partner.
UK global business innovation
Louise Hooker, GBIP Program Lead, Innovate UK Business Growth, presented Global Business Innovation Program. Innovate UK is fully-funded competitive program delivered by IUK Business Growth. A national team of circa 270 innovation and growth specialist advisers provide specialist, tailored business support to help ambitious companies commercialize new products and services, and accelerate business growth
In the past 5 years, the program has supported +2,200 companies in key technology sectors to access markets of strategic importance. Significant focus is on Asian markets, notably Singapore, South Korea, and Japan. Taiwan has emerged in the last few years as a market of significant strategic importance. Like Singapore and South Korea, it has the benefit of bilateral funding from Innovate UK and ITRI.
A three-phase program aims to build capability, capacity, and drive collaboration. It is aimed at the most globally ambitious innovation- and technology-led companies with the greatest potential to scale internationally.
Clair Hsin-Fang Lee, Senior Business Manager/Europe Business Division, Industrial Technology Research Institute (ITRI), gave an overview of Taiwan’s semiconductor ecosystem.
Introduction to Taiwan
Guy Robertson, Science and Innovation Network, British Office Taipei, gave an introduction to Taiwan. The British Office represents UK interests in Taiwan. UK and Taiwan enjoy a vibrant relationship in trade, science, culture, and education. SIN (the Science and Innovation Network) is here to improve links between researchers and early-stage start-ups in the UK and Taiwan.
SIN provides support for two key programs: UK-Taiwan Innovative Industries Program (I2P), a researcher placement program, and UK-Taiwan Collaborative R&D program (2nd call for proposals will be April 24).
Taiwan is a stable, vibrant democracy with a free press and independent judiciary. It holds presidential and legislative elections every four years, with one having just occurred earlier this year. It has a population of 23.6 million, with good transport, industry, and utility infrastructure on the North and West coasts.
Traditionally, China and US have been Taiwan’s two key markets, with 35 percent and 17 percent of exports share, respectively. Export dynamics are changing with the increasing emphasis on India and South-East Asia. Taiwan’s GDP per capita is $72,485, the 12th richest globally, and higher than Germany, France and Japan.
Taiwan has science and innovation strengths. These are 3.96 percent R&D investment as percentage of GDP (UK 2.9 percent). It ranks third in patents per capita, behind US and Japan. It ranks fourth in WEF Innovation Capability Index ranking (UK #8). About 262,000 are employed in R&D (251,000 in the UK). 25 percent of all degrees are engineering-related.
Taiwan is very famous for semiconductors, and is also dominant in contract manufacturing for the electronics industry. It has a 5+2 industrial policy focusing on Asian Silicon Valley, smart machinery, national defense, green energy, AI/cyber security + new agricultural industry and zero emissions.
Focus areas and opportunities
Iain Mauchline, Electronics, Sensors & Photonics Lead, Innovate UK, presented on the focus areas and opportunities. Talking about UK semiconductor strategy, semiconductors are 1 of the 5 technologies of tomorrow. They are critical to the UK’s economic and national security, and to strategic advantage that the UK will secure on the global stage.
Over the next 20 years, UK will secure areas of world leading semiconductor technologies of future by focusing on strengths in R&D, design and IP, and compound semiconductors. All of this will facilitate technological innovation, boost growth, and bolster international position to improve supply chain resilience. The UK government plans to invest up to £1 billion over the next decade.
In the recent Autumn statement, the Chancellor has clarified the government’s priorities for the UK Infrastructure Bank, to ensure it is able to invest in critical supply chains where it meets the Bank’s strategic objectives, including semiconductor manufacturing and critical minerals.
Regarding UK’s semiconductor strategy, UKSII Feasibility Study has results due in early 2024. The DSIT-commissioned study is to understand the technical and economic feasibility of developing specific capabilities to support commercial R&D, grow UK semiconductor sector, and contribute to supply chain resilience. It has five key capabilities under evaluation:
- Silicon prototyping and low volume piloting.
- Advanced packaging.
- Compound semiconductor open-access foundry.
- Access to EDA tools and design IP.
- An institutional framework that would provide strategic coordination for the sector.
Semiconductor Advisory Panel was established by DSIT to enable the government to work closely with industry to deliver the goals of the National Semiconductor Strategy on growing the UK sector, ensuring a stable supply of chips, and protecting the UK from national security risks associated with semiconductor technology.
ChipStart is a two-year pilot program backed by the UK government that will provide early-stage companies involved in design of semiconductors the technical and commercial help they need to help bring new products to market – and ultimately, improve lives and livelihoods in the long-term.
Semiconductor strengths
UK has several semiconductor strengths. In semiconductor design/IP, there are over 100 semiconductor design/IP companies. Global companies are also in IP, AI, SoCs, graphics, IoT, etc. It has a world leading chip-design sector with clusters, including those in Bristol, Cambridge, and Edinburgh.
In compound and novel material semiconductors, UK has 8 percent share of the global compound semiconductor market. It has a compound semiconductor cluster, CSconnected, in South Wales. World-leading companies are working with advanced materials. Research strengths of the UK includes photonics / photonic systems integration, integrated circuit design, compound semiconductors, embedded security, on chip, polymer electronic materials. and new and advanced materials for devices (spintronics, magnonics, etc.).
Semiconductor-related investments
Semiconductor-related investments by Innovate UK have been many. Digital Security by Design (DSbD) is worth £80 million. It is transforming technology to create more resilient and secure foundation for a safer digital future.
Driving the Electric Revolution (DER) is worth £80 million. It is looking at electrification technologies, including power electronics, machines and drives (PEMD), developing clean technology supply chains. Next comes commercializing quantum technologies worth £174 million. We are advancing commercialization of new products and technologies based on advances in quantum science.
Robots for Safer World is worth £112 million. We are advancing robotics and autonomous systems in extreme and challenging environments. Manufacturing and Skills Innovation projects is worth £18 million. We are supporting skills development and manufacturing scale up for the semiconductors industry. Lastly, compound semiconductor app catapult worth £80+ million. We are helping the UK companies exploit advances in compound semiconductor technologies.
UK-Taiwan collaboration
There are several opportunities for UK-Taiwan collaboration. Due to global nature of the supply chain, the UK understands need for international co-operation, and identified synergies and opportunities offered by collaborating more closely with Taiwan.
UK is a world leader in new and emerging semiconductor materials, design/IP, hardware security and research. Taiwan has a well-established semiconductor ecosystem with a vast network of suppliers and vendors, and benefits from manufacturing infrastructure that is needed to support a resilient supply chain.
Taiwan is also targeting increased development of novel materials and technologies, which align well with the UK’s areas of expertise, such as those in IC design, power electronics, silicon photonics, and future telecoms.
Collaborative efforts have been initiated via agreements between Innovate UK and Taiwan Department of Industrial Trade, and joint funding of R&D projects between ITRI and Innovate UK. It has been further supported by agreements between ITRI and CSAC.
During last year’s GBIP, exciting opportunities were identified in quantum, WBG power electronics, and photonics across the supply chain, i.e., government agencies (e.g., ITRI) universities (e.g., NYCU), Incubators/accelerators (e.g., TTU), and companies and trade organization (e.g., PIDA).
Louise Hooker, GBIP Program Lead , Innovate UK Business Growth, presented on the application and selection process. The application deadline is 22 March 2024. Innovation visits to Taiwan are on 31 May-8 June 2024, and on Sept. 1-7, 2024. An Exploitation Workshop will be in Birmingham, on Oct. 15, 2024.
Review of 2023 global semiconductor market and outlook 2024
Global semiconductor sales declined by 8.2 percent in 2023, confirming projections that the industry would experience negative growth. Despite decrease in annual revenue, the second half of last year saw consistent month-over-month sales growth, signaling the beginning of the new semiconductor business cycle. Increase in latter half of the year was driven by sales in end-markets—such as AI, automotive, and industrial—that are expected to propel the industry to $1 trillion by 2030.
Experts discussed 2023 sales trends, and an outlook of the market in 2024 at an event organized by the Semiconductor Industry Association (SIA), USA.
The panelists were: Dan Hutcheson, Vice Chair at TechInsights, Dale Ford, Chief Analyst, Electronics Components Industry Association (ECIA), Lita Shon-Roy, President/CEO and Founder of TECHCET, and Christopher Danely, MD, Citi. Robert Casanova, Director of Industry Statistics and Economic Policy, SIA, was the moderator.
Casanova said the global semiconductor had industry dropped 8.2 percent in 2023, which was expected. The industry did see some solid growth in the latter half of 2023.
Dan Hutcheson, TechInsights, said that memory will grow back this year. Similarly, logic is likely to see 14 percent growth. Some issues are still plaguing the industry. You still have a hangover from Covid-19. There was also a shortage in autos. There are also some problems with EVs.
There is the conflict between China and USA, the Russia war, etc., are all going on. Restructuring of the supply chain is still going on. Range of forecasts were really wide last year. Customers stated that they probably missed the forecast last year. It is just the time that we are in! Funding is also taking a hit. Some were saying that Moore’s Law is dead, only to change their statements by end of the year.
2024 is also a big election year in history. Questions are also being asked about a downturn. The fed hasn’t been lowering interest rates as the market has been expecting. They are going to be cautious about lowering interest rates. Sam Altman also said that he wants $5-7 trillion for AI chips. He walked back that number at the Intel Foundry event recently.
Dale Ford, ECIA, stated some of the results will be complementary to what has already been said. The electronic component revenue growth of last year saw a difference between semiconductor and passive components. The semiconductor industry bounced back in Q3-2023, while passives took a little longer. We had strong rebound in volume of passives. Revenue growth for semiconductors was similar, but not as sharp.
If we look at interconnects, passives, and electro-mechanical (IPE) orders, we had an abrupt transition, from negative, to very strong growth coming into 2024. Hopefully, we can sustain that in 2024. Looking at the semiconductor growth cycle, QoQ growth accelerated to +11.6 percent at end of 2023. The annual revenue cycle outperformed expectations, and ended 2023 on the upswing at -8.2 percent. Demand drivers continue to shift from consumer markets. Asia is also achieving recovery to boost global picture. Question emerges: how well is the supply chain balanced?
Memory has a volatile cycle. It is similar to the industry. Memory ICs are amplifying the current cycle. Discretes have, however, shown decline last year. It is more vulnerable to excess inventory. Downward trend was also seen for analog ICs. Logic ICs never went negative in Americas last year. We are seeing recovery worldwide. Microcomponent ICs are also seeing some growth.
There is unified downward slide, and no market is immune. Memory ICs are amplifying / distorting the cycle. Memory, micro, and logic ICs are showing strong growth. Analog ICs and discretes are moving counter-cyclical in negative territory. Americas growth profile mirrors the worldwide trend at the end of 2023. Pricing dynamic now shifts role to drive recovery. New cycle had begun in August 2023, After five months, it improved by 6.1 percent above the bottom.
Broad-based optimism for 2024-25
As per WSTS, 2023 worldwide and Americas annual growth beat fall 2023 forecast. Fall WSTS presents broad based optimism for 2024. Double digit growth will be sustained into 2025. The higher Americas outlook is driven by larger market share of memory ICs. Non-memory market growth is expected, but at more subdued levels. The cyclical pattern endures!
What about the electronics components supply chain? Discretes will grow from -11.7 percent to 9.2 percent. Analog ICs will grow from 1.4 percent to 23.2 percent. Logic ICs will grow from -9.6 percent to 5.8 percent, respectively.
NAM Q4 2023 Manufacturers’ outlook survey saw more than 66 percent of the member companies have a positive economic outlook for 2024. Opinions are mixed on whether there will be a recession. The top economic challenge this year will be the workforce, with the labor market cooling substantially but remaining tight.
Private manufacturing construction spending is at an all-time high of $210 billion. Thanks to the production of semiconductors, electric vehicles and batteries, and general reshoring. Risks this year include geopolitical turmoil, slow global economic growth, cost pressures, talk of a recession, and labor issues.
Electronics supply chain will see strong growth profile in 2024. It is an ASP-driven semiconductor cycle. We have a hopeful outlook for moderating pressure. In supply chain index, cyber security has the top spot to look out for. We need the right conditions to continue growth. Inflation is today back down to 3.1 percent. However, there is danger of history repeating itself. We need to keep an eye on inflation.
There is growing need for speed and power, more development is happening in materials, commercial fusion energy is taking place, nanotech materials are passing human safety tests, and UltraRAM has also emerged, etc. We have a first operational graphene-based chip, which is 10 times faster than silicon. All of these bode well for the semiconductor industry.
Chip revenue up in 2024
Lita Shon-Roy, TECHCET, said that the economy will have a big impact. GDP had slowed down on global and domestic basis in the last couple of years. Geopolitics and economy are the major factors behind this. She added that 2022-2027 global fab expansion is worth $685 billion. Leading players include TSMC, Samsung, Intel, SK hynix, Micron, SMIC, TI, GlobalFoundries, Nanya, Infineon, Kioxia, UMC, STMicro, etc. US fab expansions from 2022-2027 is worth $185 billion. Players include Intel, TSMC, Samsung, Micron, TI, GlobalFoundries, Bosch, OnSemi, Microchip, Analog Devices, etc.
Regardless, we will see chip revenue this year. Total semiconductor revenue should be up 11.5 percent vs. 2023. Industrial and automotive segments look to be cooling. 2025 is expected to peak at an upturn of 21 percent vs. 2024. And, there will be moderate growth of 5.5 percent in 2026 vs. 2025.
Talking about semiconductor revenue forecast, after slumping by more than -13 percent YoY in 2023, the global semiconductor industry is poised to post consecutive years of double-digit sequential growth. It is expected to be largely driven by recovering memory ASPs in 2024, and total semiconductor revenue up +11.5 percent vs. 2023. Industrial and automotive segments look to be cooling. 2025 is expected to represent peak growth of the upturn (+21 percent vs. 2024) with moderating growth in 2026 (+5.5 percent vs. 2025). Prior to the of the decade, TECHCET projects a milestone of >$900 billion for the global semiconductor industry.
As for semiconductor materials forecast, TECHCET estimates that 2023 experienced a sequential decline of -6 percent. Silicon wafers experienced the largest retreat, falling by -11 percent. Other segments saw decreases of ow- to upper-single-digits. While 2024 and 2025 indicate improving recovery with respective sequential growths of +7.1 percent and +8.8 percent, 2026 and 2027 are expected to have moderate (low single-digit) growths, prior to a stronger performance in 2028. Several large companies are still applying for CHIPS Act funding, as well.
Several foreign suppliers have also pledged to set up facilities in the USA. Sunlit Chemical has a new facility for hydrofluoric acid (HF) facility in Phoenix, Arizona. It is currently a warehouse, and will change over to production later. Geopolitics are forever impacted by war, tariffs, and geopolitics. There are several critical minerals that are shipped. Some of those are being withheld by certain countries. There may also be impact on helium, etc. Process materials from China may also get hit. However, we believe that the current stability may continue.
There are several examples of recent expansions. Fujifilm invested €30 million in Belgium, with target completion by the end of 2024. Fujifilm also has Yen 2 billion investment, with plant location in Kumamoto, Japan, and full-scale production anticipated in Jan. 2024. Soitec has €400 million investment in a Singapore facility with projected completion in 2024.
STMicroelectronics has €730 million investment, supported financially by the government of Italy, in Catania. Merck has €500 million investment in Taiwan over the next four to six years with initial operations in 2025. Ucore Rare Metals has acquired a site in Louisiana for development of its first commercial rare earth element (REE) processing facility, with a goal of production by early 2025. VVC Resources in helium and natural gas, is located in Syracuse, Kansas. Six additional wells were expected to be completed by end of 2023.
We, as an industry, are also in threat of a labor shortage for chips. Some say that we are already in a shortage. This issue is being addressed by the CHIPS Act to encourage workforce development and local governments. Will that have an impact fast enough is unknown! Will immigration policy need to be eased to allow for an increase in workforce from educated countries? This is being discussed, but it is a very volatile topic.
Outlook for 2024 for semiconductor materials is very positive, with or without CHIPS Act money. Current geopolitical risks continue to pose a further downside. Peak growth for upturn is expected in 2025 for all semiconductor categories.
The global economy has reached a period of slowing growth. Current geopolitical risks pose a further downside. Semiconductor industry, after facing a cooling off in 2022 and a deepening downturn in 2023, is entering an upturn. It is off to a slow start in 2024 (many companies are providing negative sequential revenue guidance).
Additionally, several delays in US semiconductor fab expansions have been announced. Certain inventory corrections are expected to persist through 1H, 2024 is poised to reach double-digit revenue growth, primarily on strengthening memory ASPs, and a broader recovery, particularly in 2H. Peak growth for the upturn is expected in 2025 for all semiconductor outlook categories. The overall materials growth is expected to remain positive through 2028, as technology advancements drive expanded demand across most segments.
AI mania?
Chris Danely, Citi, added that last year was a worst year for semiconductors. We were actually down by nearly 20 percent. There was massive inventory buildup post Covid-19. Whenever the lead time goes up, you need to stock. There are about 30-40 semiconductor stocks, which was about 70 stocks in 2023. Everything changed when Nvidia came out with AI chips. Thereafter, it has been an AI mania.
Nvidia and AI has been a presage for a few others, such as AMD, Broadcom, etc. There are two components to stock price. Earnings, and what people will pay. Once the direction starts to change, the people will start chasing stocks. There was also sharp divide between AI and business. Memory was at the tail last year. Automotive and industrial end markets were falling off.
Today, handset, AI, EC, etc., markets have nearly recovered. Server, data center, consumer, are still recovering. Industrial and automotive are a bit terrible. On the positive side, stocks have been going up. By end of the year, you can see some correction in automotive. In AI, people are trying to get their arms around the technology. Domestic companies, universities, etc., are all buying AI. Nvidia, AMD, Broadcom, etc., are all in this space.
Next, memory and DRAM are also continuing to recover. The CHIPS Act has presented another big deal for the finance sector. It will probably benefit the equipment companies more. They will probably be the biggest beneficiary of the CHIPS Act.
Hutcheson added that AI is not the only driver. There are other segments as well. AI is the next big thing today. It will add to the size of the semiconductor industry. Even the small corporations are buying it. We are now moving to a stage where you can program AI with LLM.
Dale Ford noted that AI is an app. It has to be translated across to all the different equipment. You also need processors to process them. You need the communications dimension too. All of this would lead to a massive appetite for energy and power. There will be lot of energy and power generated by all of the AI devices in future.
Lita Shon-Roy added that there may likely be another situation where the supply chain may get affected in 2025. The new ramp up is also expected in 2025-26. We need to be see what will be in demand, and what will be constrained.
Chris Danely, said that AI was a huge theme last year. But, it is between 5-10 percent of the market. Memory also has 10-15 percent share. Another area is processors. From a stock perspective, AI is currently helping.
Lot has happened for semiconductors in 2023!
Friends, we have reached the end of another year. Lot has happened for semiconductors this year. But, more of that later.
First, a very interesting mention about my blog stats. While I wrote about a third of articles during 2023, than what I did in 2022, the web traffic has exceeded over last year’s! Great! I can hopefully do more, with less! 😉 Thanks to all of those who stopped by to read. I will try and write more in 2024.
Chips are truly the heart of everything! In January, with Chips Acts across both USA and Europe, showed their concern about declining shares of semiconductor production, as against Asian countries. At CES 2023, digital scent and BEV made an appearance! We saw how there was innovation in immersion, with the advent of digital scent technology.
European Photonics Industry Consortium (EPIC) talked about how optical metamaterials and metalenses offer novel functions. Dr. Ms. Laurie E. Locascio, provided an update on implementation of CHIPS for America Act.
Lars Reger, NXP Semiconductors, talked about how positive incentives of the EU and US Chips Acts were for expansion of required manufacturing capacity, at ISS 2023. Mark Thirsk, Linx Consulting, stated how materials suppliers will be challenged to develop, manufacture, and deliver advanced products. American Innovation and Manufacturing (AIM) Act of 2020 looks at HFC phase down and polyfluoroalkyl substances (PFAS) regulation. Martin van den Brink, ASML, discussed holistic lithography and the road to one trillion transistors. We face the challenge of Moore’s Law chessboard. January ended with Malcolm Penn suggesting that the global semiconductor industry could drop -22 percent in 2023, with no change in the prediction from May 2022!!
In February, Industrial Advisory Committee (IAC), USA, provided an update on the USA CHIPS R&D program. IRPS 2023 announced its focus on reliability of semiconductor devices, ICs, and microelectronic assemblies. US Secretary of Commerce, Ms. Gina Raimondo, delivered a speech titled “The CHIPS Act and long-term vision for America’s technological leadership” at the Georgetown University’s School of Foreign Service. The University posted my story link, and I remain humbly obliged! Thank you!! Semiconductor Industry Association (SIA), USA, did a review of the 2022 semiconductor industry and took a look at 2023.
Masters of Digital 2023, DIGITALEUROPE, called for diverse workforce, and more participation from private sector, in March. Leading female founders in technology also discussed about closing the gap. At CERAWeek by S&P Global, Paul Marsden, Bechtel Energy, stated Inflation Reduction Act (IRA) puts very clear value on molecule of carbon.
Nils Poel, deputy head of market affairs, CLEPA — the European Association of Automotive Suppliers, talked about shifting gears on semiconductor innovation for automotive at imec, Belgium. At ASEAN Electronics and Semiconductors Summit 2023 held in the Philippines, demand for electronics and semiconductors was likely to grow in the ASEAN. At the SEMI Silicon Valley and Northeast Chapters conference, Jay Vleeschhouwer, Griffin Securities, presented on the state of EDA. The big two — Cadence and Synopsys — rule!
Jean-Christophe Eloy, Yole Développement, presented the status of the advanced packaging industry. I tried to make a point, stating, are you aware that a semiconductor fab requires significant annual investments, and has very high failure rates? International Photonics & Electronics Committee (IPEC) had a conference where they talked about how linear drive enables green all-optical connectivity for data centers.
European vision for semiconductors, was presented by Francisco Ibáñez, DG CONNECT, European Commission, at ISS Europe 2023. Guillaume Girardin, Yole Group, talked about how beyond Moore is actuating the transformation age. Photonics will be of great importance to the development of quantum technologies.
METIS addressed the skills needs of the European microelectronics industry. Dr. Michael Alexander, Roland Berger, talked about deglobalization of semiconductor supply chain. He proclaimed the European Chips Act is a good initiative, but likely insufficient. Dr. Ms. Sabine Herlitschka, Infineon, stated that key for an energy efficient world lies in new semiconductor materials. The month closed with the US Chips Act, IRA, and tax incentives: What’s in it for materials companies?
In April, European Innovation Council (EIC) organized the EIC Quantum Portfolio and Chips Act. EU-27 accounts for 121 quantum start-ups. EU also identified the challenge to support the expansion of chip design capabilities. The scope includes innovative design approaches addressing combination of different functionalities such as computing, RF, power, memory and sensing. Proposals on software development for semiconductor chip design are also considered in this challenge. Legal professionals in Greater Phoenix, USA, discussed how to apply for the first round of CHIPS Act funding.
My most popular article of the year: New world order for semiconductors is emerging, was next. The new world order is entirely dependent on technology, not warfare! Even Australia has big plans for quantum.
In May, Chips.gov and NIST unveiled vision and strategy for National Semiconductor Technology Center (NSTC). Dr. Thomas Morgenstern, Infineon Technologies, presented European Chips Act as framework for revitalizing European semiconductor ecosystem, at ASMC 2023. Thomas Sonderman, SkyWater Technology, talked about revitalizing the domestic semiconductor manufacturing. Robert Maire, Semiconductor Advisors, presented on Chips Act, China, Covid, downcycle, re-shoring, Taiwan and technology challenges — chip chaos.
ETP4HPC organized a seminar on HPC system software/application co-design strategic research agenda (SRA) 5. Malcolm Penn, Future Horizons, talked about re-shoring, HI being in the news! NIST, DoC, organized a round-table on workforce cross-sector partnerships. EU-US Trade and Technology Council (TTC) is said to be essential for achieving transatlantic shared objectives. SEMI Foundation talked about how women in semiconductors were bridging gender gap through allyship.
Come June, and Yasuo Nakane, Mizuho Securities presented the flat panel display (FPD) industry supply chain outlook at Display Week 2023. TSMC debuted N3P process, and update 2nm, and TSMC 3DFabric progress! Who can catch up? At 2023 Symposium on VLSI Technology & Circuits, multi-chiplet heterogeneous integration packaging for semiconductor system scaling was discussed. There was a workshop on how next level of spintronics is beneficial to LSIs for high performance and ultra-low power.
Semiconductor Industry Association (SIA), USA, organized a conference on how AI and semiconductors will drive innovation and productivity. Hiroyuki Mizuno, Hitachi, presented on quantum computing: from hype to game changer!
In July, ETP4HPC organized a conference on emerging technologies for HPC in Europe. Solarplaza organized a conference around lessons learned in agri-PV. European Photonics Industry Consortium (EPIC) held a conference on photonics for wearables. My article, TSMC and Samsung vs. new world order was hugely successful. Later, Nikkei Forum, Japan, organized a seminar on the untold story of the chip war, and underestimated impact of export controls.
August was a difficult month personally, as I had to deal with medical emergencies. Solar Media organized a conference around how the industry leaders optimize the performance of their renewable and energy storage assets. Industrial Info Resources (IIR) organized a seminar on global semiconductor and automotive industries. Leveraging Chips Act in Texas with industry incentives and initiatives, was widely read. Chip crisis was likely to last till 2024 forcing companies to adopt costly mitigating measures, per EC chips survey.
In September, Dr. David McKee, DTC Capabilities and Technologies Working Group, presented the stack architectural framework for digital twin platform. Road to ‘Beyond Moore’ with heterogenous integration for next-gen computing was proclaimed at 2023 Heterogeneous Integration Symposium. Future Horizons stated global semiconductor industry’s ultra-strong Q2-23 was an unexpected big surprise. KDT consultation workshop was held in Brussels, Belgium, on advanced packaging and 3D heterogeneous integration for RF/mmWave applications. Xecs called out for RD&I in electronic components and systems in Europe.
In October, there was the Solarplaza Summit, which looked at agri-PV challenges and opportunities. SEMI, USA and Forge Nano demonstrated atomic layer deposition (ALD) strengths and perceived weaknesses. Also, SEMI University demonstrated how it was addressing the industry’s workforce challenges. SEMI next had a seminar on what can we do about PFAS? IEDM 2023 was announced, with chiplets, heterogenous design as key for future devices to achieve desired PPACt. EuroHPC Joint Undertaking discussed LUMI as enabler of world-class scientific breakthroughs!
In November, there was an update on CHIPS Act implementation, and recommendations from IAC Working Groups. European Photonics Industry Consortium (EPIC) hosted a seminar on optical designs and simulations. NAPMP, CHIPS for America, declared that collaboration was critical for the success of advanced packaging, APPF.
Come December, Cleantech Group reported low-carbon hydrogen growth was rising, but needs policy support. Semiconductor Industry Association (SIA), USA, organized a conference on how collaboration between auto and chip industries fosters innovation and drives market growth. Yole Group, France, organized a conference on China’s rise as a global challenger in semiconductor industry. NIST organized CHIPS R&D Interfaces technical seminar, stating that open chiplet economy was now real.
My personal crowning glory: Pradeep’s Techpoints was announced as media partner for Asia Photonics Expo 2024, to be held in Singapore. Thanks for the support, everyone. 🙂
That’s it for this year, folks. Hope to be back with more in 2024. Ciao, Tot ziens, Au revoir, Auf Wiedersehen, Sayōnara, Annyeonghi gaseyo, Selamat tinggal, Adiós, Do svidaniya, Goodbye, Abaar esho! 🙂
Have a great new year 2024 ahead! 😉
Collaboration critical for success of advanced packaging, APPF: NAPMP, CHIPS for America
CHIPS National Advanced Packaging Manufacturing Program (NAPMP) organized a conference today.
Approximately $3 billion in funding for the National Advanced Packaging Manufacturing Program (NAPMP) will be used to drive US leadership in advanced packaging. An initial funding opportunity for this program is expected to be announced in early 2024. Supporting innovation and keeping the US at the forefront of new research is a critical part of the president’s Investing in America agenda.
Gina Raimondo, Secretary of Commerce, stated: “Making substantial investments in domestic packaging capabilities and R&D is critical to creating a thriving semiconductor ecosystem in America. We need to make sure new leading-edge chip architectures can be invented in our research labs, designed for every end-use application, manufactured at scale and packaged with the most advanced technologies. This new vision for advanced packaging will enable us to implement President Biden’s Investing in America agenda and make our country a leader in leading-edge semiconductor manufacturing.”
Laurie E. Locascio, NIST Director, added: “Within a decade, we envision that America will both manufacture and package the world’s most sophisticated chips. This means both on-shoring a high-volume advanced packaging industry that is self-sustaining, profitable and environmentally sound, and conducting the research to accelerate new packaging approaches to market.”
Current challenges
Subramanian Iyer, director of NAPMP, Chips.gov, USA, discussed the current challenges in advanced packaging, and the NAPMP’s vision for investments in R&D. There are several opportunities in advanced packaging. Even though transistors have scaled dramatically, die sizes have grown larger. Monolithic dies still outperform multi-chip packaged assemblies.
Packaging is now evolving. It is evolving to emphasize system integration, rather than single-chip packaging with the increasing adoption of silicon processing techniques. Heterogeneous integration (HI) is also evolving, and is not new. The difference now is in the scale. There are simple I/Os, and more useful chip areas. We can end up with lower power, lower latency, and higher bandwidths.
Advanced packaging is now having more bump and pillar pitches. There is finer trace pitch, shorter inter-die distance, etc. We are also increasing the amount of silicon.
Advanced packaging blurs the line between monolithic chip and packaged assembly of heterogeneous chips. Scaling out the package involves accommodating larger number of closely packed heterogeneous dies. We can address power delivery, thermal dissipation, etc. Advanced packaging allows us to change how we put complex systems together. Bare dielets are stacked (3D) or integratedside by side at fine pitch on aninterconnect fabric (substrate). Dielets are heterogeneous, and a simpler and flatter hierarchy is possible.
Chiplets are IP designs, and need to be connected to complementary chiplets to function. Dielets are hardware instantiated chiplets. Bare dielets are stacked or integrated. Today, packages are incredibly complex and costly. We need to simplify packaging, and make it cost-effective to manufacture in the USA.
Critcal resource for advanced packaging
George Orji, Project leader, Microsystems and Nanotechnology Division, NIST, said that the NAPMP implementation planning should serve as critical resource to developed advanced packaging and related R&D. It is now a matter of national security.
NAPMP must be competent inheterogeneous integration, chiplets, photonics, and codesign. NAPMP should have easily accessible and flexible user facilities or hubs that focus on low-volume, cost-effective prototyping, including material characterization, metrology, modeling and simulation, and standards. It is also important to build a skilled workforce to support this industry. Within a decade, NAPMP-funded activities, coupled with CHIPS manufacturing incentives, will establish a vibrant, self-sustaining, profitable, high-volume, domestic, advanced packaging industry where advanced-node chips manufactured in the US, are packaged in the US. We expect the technology developed to be leveraged in new applications and market sectors and at scale.
The CHIPS IAC has also recommended to create programs. Within a decade, NAPMP-funded activities, coupled with CHIPS manufacturing incentives, will establish a vibrant advanced packaging industry in the USA. The Secretary of Commerce shall establish the NAPMP program, in coordination with the national semiconductor technology center established under subsection (c), to strengthen the semiconductor advanced test, assembly, and packaging capability in the domestic ecosystem, and which shall coordinate with a Manufacturing USA institute established under subsection (f), if applicable. The Director may make financial assistance awards, including construction awards, in support of the National Advanced Packaging Manufacturing Program.
Subramanian Iyer stated that we now need to establish advanced packaging in the USA. There are packaging roadmaps, such as Manufacturing Roadmap for Heterogeneous Integration and Electronics Packaging (MRHIEP), Materials and Electrical Test Technology Roadmap (MAESTRO) from International Electronics Manufacturing Initiative (iNEMI), Microelectronic and Advanced Packaging Technology (MAPT), and other roadmaps such as Heterogeneous Integration Roadmap (HIR) and International Roadmap for Devices and Systems (IRDS). All aspects of technologies are required to develop leading-edge on-shore advanced packaging manufacturing capability.
Priority areas
First, there should be an Advanced Packaging Piloting Facility (APPF). It is the key to facilitating high-volume manufacturing, piloting, and prototyping functions. Another important area includes chiplets and design ecosystem, and design and build in the USA, and later, sold worldwide.
The NAPMP priority research investment areas include substrates and materials as the platform for heterogeneous integration of dielets. Equipment, processes, and tools are also needed. There must be thermal management and efficient power delivery, more photonics and connectors, and also the chiplet ecosystem crucial for advanced packaging. APPF will provide the test bed for the integration of different investment areas, and functions as piloting and prototyping facility.
Materials and substrates are the platform on which advanced packaging is built. These substrates or interconnect fabrics (IF) may be based on silicon, glass, or organic materials and can include fan-out wafer-level processes. They must be compatible with advanced and legacy nodes, and different semiconductor material systems.
For equipment, tools, and processes, we need advances in these areas, where substrates are patterned and chipletsare reliably assembled on these substrates. This is to achieve goals in reducing patterned feature sizes on large areas, including through substrate vias, as well as strategies to reliably assemble chipletsonto these finer substrates and passivate them. We expect CMOS equipment and processes will be adapted to handle dies, wafers, and panels. We also expect the APPF to benefit from developments in equipment, tools, and processes.
For power delivery and thermal management, we need new thermal materials and novel circuit topologies to employ advanced substrates and HI. Advanced packaging makes severe demands on power density and can restrict heat spreading. HI will require multiple voltage domains and high granularity. Power delivery will likely require wide bandgap materials integrated into the substrate. Modelling and optimization to achieve high efficiency is a must.
In photonics and connectors, the focus will be on reliable and manufacturable integrated connectors that include computational capability, data pre-processing, security, and ease of installation to the packaged assembly. Packaged assemblies should interact with other assemblies and the outside world. Connectors can also be wired, RF, and optical.
As for the chiplet ecosystem, chiplet discovery methodologies will be developed to ensure a high level of reusability, design, and warehousing of these chiplets. They need to be small and work better when connection pitches and distances are small. We need to develop chiplet dicing and ESD-free transport. Chiplet ecosystem also requires standards and warehousing infrastructure where bare dies are stocked. NAPMP will focus on chiplet discovery methodologies, high-value chiplet designs, and integration methodologies. We will also need common protocols, and protocol translator chiplets.
Finally, there is co-design. Holistic package co-design “will be adapted for advanced packaging with consideration for built-in test and repair, security, interoperability, and reliability, with a detailed understanding of the substrate and processes used for assembly.” Co-design platform should comprehend chiplet architecture and communication options. We need to design for test, repair, security, and reliability. There can be thermal and thermo-mechanical constraints. We also need substrate and assembly technology. We need the extension of chip design methodologies to advanced packaging. NAPMP will support the co-design efforts.
We are also looking at packaging workforce development. It requires multi-disciplinary teams. NAPMP intends to fund projects that incorporate strong workforce development plans. It should be part of other educational advancement activities within each investment area, and APPF.
Collaboration critical!
APPF is the point where everything comes together! The APPF is where successful development efforts will be transitioned and validated for scaled transition to US manufacturing. It is a key facility for technology transfer to high-volume manufacturing.
APPF could include integrated process flows that can reach commercial scale, validating new technology specifications, compatibility with other processes, yield, and reliability, and assessing technologies for scaled transition to US manufacturing. The APPF may consider prototyping innovative design ideas from the community.
Collaboration is now critical for success! We will need the EDA vendors, materials and substrate suppliers, equipment and tool vendors, chiplet designers, chiplet fabricators, system houses and end users, OSATs and IDMs, thermal and connector solutions, educational institutions, etc., to come together.
Iyer noted that the NAPMP expects to release the first funding opportunity in early 2024. Materials and substrates will be the topic of the first funding opportunity. Advanced packaging is all about scale down and scale out. We need minimal hierarchy and reusable chiplets, and innovative architectures and products. We also need small NREs and short times to market. It offers a different way of building complex chips and systems which leverages our strengths in design and system architecture.
Our focus is on R&D that leads to products designed and manufactured in the US, with US software and equipment. We need to build US manufacturing and R&D workforce, and provide a self-sustaining innovation pipeline that fuels US packaging leadership.
The approximately $3 billion NAPMP program will be dedicated to activities that include an advanced packaging piloting facility for validating and transitioning new technologies to the US manufacturers, workforce training programs to ensure that new processes and tools are capably staffed, and funding for projects focusing on: materials and substrates, power delivery and thermal management, equipment, tools and processes, photonics and connectors, chiplet ecosystem, and co-design for test, repair, security, interoperability and reliability. Lora Weiss, Director of CHIPS R&D Office, added that we will leap ahead and do more advanced packaging in the future.
Xecs calls for RD&I in electronic components and systems
Xecs Call 3 is now open! For the Xecs Call 3, projects can be submitted in all areas of the 2023 ECS Strategic Research and Innovation Agenda.
As some countries have specific priorities in terms of funding criteria, you are strongly encourage to start contacting representatives of national funding bodies to ensure a close alignment between your project goal and national priorities. Once your project idea and consortium is mature, submit your Project Outline (PO) via the Project Zone by 18 January 2024, 17:00 CET.
AENEAS role in Xecs, was presented by Ms. Caroline Bedran, Director General AENEAS. AENEAS is a not-for-profit industry association, with members from large industries, small and medium enterprises, research institutes, academia, etc., that catalyzes RD&I collaborative activity in the electronic components systems — value chain supporting development of the digital economy. AENEAS membership is free of charge.
AENEAS members are key industrial players. Kurt Sievers, President and CEO of NXP Semiconductors, is AENEAS President. It has 540 members at the end of June 2023. Off these, 50 percent are SMEs, 24 percent are RTO, 23 are corporate, and 4 percent are associate members.
The EU RD&I funding landscape for the ECS industry includes Key Digital Technologies (KDT-JU) partnership under Horizon Europe and EUREKA Clusters Program.
Interesting challenges for Xecs Call 3 include following the ECS SRIA, complement other programs, like KDT and IPCEI ME/CT, have disaster recovery and resilience (tsunami, earthquakes, storms, floods, fire, etc.), climate change, sustainability, and work with adjacent communities, such as photonics, quantum, etc.
Xecs Call 3
Xecs and launch of the Call 3, was presented by Ms. Nadja Rohrbach, Xecs Director. Xecs is a Eureka cluster, supporting RD&I in the field of electronic components and systems. Managed by AENEAS, it has Complementary activities within KDT-JU, direct experience from Catrene, Euripides², and Penta clusters, and also supported by EPoSS and Inside Industry Associations.
Eureka is the world’s biggest public network for international cooperation in RD&I, present in over 45 countries. These are mainly European, but also including Canada, Israel, Singapore, South Africa and South Korea. Eureka has individual and joint cluster calls.
So, why participate in Xecs? To take advantage of transnational RD&I cooperation, along the entire value chain and related national funding in a broad range of countries also beyond Europe. Access expertise and get professional guidance coaching and mentoring from the industrial experts and Xecs teamGet. Boost competitiveness, accelerate growth and shorten time to market. Create disruptive ideas, get access to (new) markets and increase your international visibility.
Post the Xecs Call 3 launch, the PO submission is in 18 January 2024, FPP submission is in 18 April 2024, labelling is in May 2024, and funding is in Sept. 2024.
Eligibility criteria for Xecs includes developing a product, process or service. The project must have a civilian purpose. There should be at least two independent partners from two different Eureka countries. For mid-sized projects 35 person years (PY) minimum will be required. No single organization or country can be responsible for more than 70 percent of the project budget. It should be market-oriented project.
23 countries are active in the Xecs project submissions. These are: Austria, Belgium, Canada, Czech Republic, Denmark, Finland, France, Germany, Hungary, Ireland, Israel, Latvia, Luxembourg, Malta, Poland, Portugal, South Korea, Spain, Switzerland, The Netherlands, Sweden, and United Kingdom.
Measuring Scope 3 carbon emissions with digital twin
Digital Twin Consortium (DTC) recently organized a seminar on measuring Scope 3 carbon emissions with digital twin.
A digital twin is a virtual representation of real-world entities and processes, synchronized at a specific frequency and fidelity. Digital twin systems transform businesses by accelerating holistic understanding, optimal decision-making, and effective action. Digital twins are motivated by outcomes, tailored to use cases, powered by integration built on data, guided by domain knowledge, and implemented in IT/OT systems
Erich Barnstadt, Marketing Control Board Member, OPC Foundation, said we need resilient manufacturing supply chains. We need to be able to digitally provide asset data cross-platform, and combat climate change in the process.
For this to happen, the supplier needs to verify component / raw materials are within spec. It also needs to report carbon footprint and hazards of materials provided. The manufacturer needs to digitally verify data from supplier on-the-fly. It needs to calculate carbon footprint of product manufactured. It also needs to report the carbon emitted during manufacturing process to the government.
Let us try and understand carbon, and direct and indirect emissions. Scope 1 has direct emissions that result from direct emissions through the use of fossil fuels in transport, processes, or heating. Scope 2 has indirect emissions that result from production of electricity used by the company. However, Scope 3 results from supply chain emissions. It involves emissions from everything, else including purchased services or products, lifecycle of sold products, etc.
Looking at the share of scope 3 emissions in manufacturing, they account for 87 percent of all emissions, with scope 1 and 2 accounting for the remaining 13 percent. Top contributors to scope 3 emissions include purchased goods at 43 percent, use of sold goods at 33 percent, upstream and downstream transport at 4 percent, each, capital goods at 4 percent, and others at 3 percent.
We need to have an asset administration shell (AAS). It is a vendor-neutral asset data sharing service. It’s a shell (container), and cross-platform, and covers the full lifecycle of the asset. It contains OPC UA info model. Microsoft is one of the authors. There is open-source implementation. HTTP REST interface is developed by SPS’22, and uses OpenOfficeXml format.
IEC 62541 is an industrial interoperability standard from OPC UA. For interoperability, it is vendor, protocol, platform and OS independent. Open Source is available on GitHub (>4.5 million source lines are contributed by Microsoft. It is scalable from sensor to cloud, and has services-oriented architecture (SOA). It is owned by a non-profit OPC Foundation. The standard has 70 million+ installed base and exponentially growing.
CESMII is Smart Manufacturing Institute. CESMII SM Profile Designer includes machine builders, system integrators, and any domain expert. It also has the CESMII SM Marketplace, CESMII SM Innovation Platform, and other smart cloud infrastructure and platforms.
An example from CESMII was demonstrated. This demonstrator interprets training unit components as part of a larger system, and applies the Carbon Reporting Information Model to each unit, and to the machine. The common Information Model for Carbon Reporting allows consistent and accurate reports to be generated at any level of the enterprise, for any asset that implements this information interface.
It is imperative that we have a much better understanding of the Scope 3 emissions, and work together.
Road to ‘Beyond Moore’ with heterogenous integration for next-gen computing
Heterogeneous integration is paving the way for microelectronics resurgence, stated Dr. William Chen, ASE, and co-chair of the IEEE/ASME/SEMI Heterogeneous Integration Roadmap at the 2023 Heterogeneous Integration Symposium organized by IEEE Santa Clara Valley Electronics Packaging Chapter, Milpitas, USA.
2023 is the 75th anniversary of the transistor. On December 16, 1947, John Bardeen and Walter Houser Brattain at Bell Labs NJ, demonstrated the first working transistor, now know as the point-contact. William Shockley, invented junction transistor in 1948. They initiated the first stone for the foundation of the Smart or Intelligent Society.
Next are inventions of integrated circuits (independently by Jack Kilby and Robert Noyce, 1958 and 1959). Moore’s Law progress and 50+ years of scientific and technological progress by scientists and technologists still going strong today. Semiconductor and electronics are now recognized as foundation pillars for digital transformation in service to society and humanity.
In 1991, the world’s first Open-Source Technology Roadmap, the National Technology Roadmap for Semiconductors (NTRS) sponsored by US Semiconductor Industry Association (SIA). In 1998, NTRS expanded forming the first Global Technology Roadmap. Europe, Japan, Taiwan, and Korea joined. It was renamed International Technology Roadmap for Semiconductors (ITRS). In 2014, benefits of Moore’s Law scaling started diminishing, and a decision was made to end ITRS. The last edition of the ITRS was published July 8, 2016.
HI provides future directions
HI articulates state‐of‐the‐art advances in technology and science, and provides future directions, significant roadblocks and potential solutions. We have a roadmap for the next era of Moore’s Law. We are seeing the electronics industry resurgence, and that is decades into the future.
From 2022-2026, the total semiconductor market will grow almost 1.8x from 2019‐2026. It will be primarily fueled by server/storage/communications infrastructure and mobile phone/tablet segments. We will have advanced nodes for silicon. Chip architectures are dis-aggregating for cost and yield management. Silicon chiplet integration is enabled by advanced packaging technology.
HI is defined as the integration of separately manufactured components into a higher-level assembly (chiplets, SiPs, modules) that, in the aggregate, provides enhanced functionality and improved operating characteristics. Chiplet integration is becoming mainstream for HPC via advanced packaging platforms.
Today, we are at unique point in time when there is global recognition on critical roles of semiconductor and microelectronics as foundational pillars to the various nations economies. Heterogeneous integration through advanced packaging for chiplets and system-in package is crucial to achieve best optimal systems: performance, power, cost, reliability, time-to-market, and market penetration, paving the way for microelectronics resurgence for decades to come.
HIR twenty-three technical working groups, represent broad-based ecosystem for advanced packaging innovations. These range from package architecture and design, assembly, test, materials, equipment, tools, encompassing AI and ML. Basic research and collaboration across disciplines in HI (e.g. SiP and chiplets, and more) lays foundation for renaissance in science and technology, and microelectronics resurgence, in service to society and humanity.
HI interdisciplinary innovations
Dr. Xin Wu, Corporate VP, AMD presented on HI interdisciplinary innovations. Moore’s Law was designed to rebut contemporary claims that ICs were expensive and unreliable. FPGA capacity grew ~680x in 10 nodes, benefiting from Moore’s Law, hetero-integration, packaging, and new technologies.
Moore’s Law has since slowed down significantly. We need expensive solutions to keep it alive. We now have gate-all-around, EUV double patterning, SiGe channel, etc. Node-to-node mask/wafer cost increase can be > 30 percent. There is high design cost for new technology nodes. Advanced packaging and 3D integration can provide new opportunities.
Let’s look at semiconductor technology. Although silicon node advances continue, scaling has slowed down. Standard-cell-based library design kept (almost kept) node scaling. SRAM and customized design scaling has reduced to about half (or less) per node. Economic benefit of Moore’s Law was reduced significantly. Cost of manufacture and design increased from node to node. Hetero-integrations (HI) provide a chance to advance the semiconductor industry further for certain products and applications. Unlike Moore’s Law, HI provides many varieties of technology, each associated with its cost and suitable to certain kinds of applications. HI development requires multi-disciplinary innovations.
There remain key challenges of HI product. First, we have 3D stack technology itself. Next, architecture that benefited from HI connections and mitigates. We also have HI design, CAD, simulation flow and PDKs (including 3D modeling). Some other issues include software, pkg (I/Os) routability, signal and power integrity (SIPI), and power delivery. We also have to deal with thermal solutions, multi-chip production flow and testing, reliability, etc.
He gave an example of AMD CPU with 3D V-Cache using hybrid bond stacking. Design innovations and CAD flow for HI have continually progressed, but still have a long way to go.
Thermo-mechanical engineering is critical part of HI. Power consumption is also a leading cost factor in data centers. Thermal and mechanical solutions directly affect performance and power efficiency. It is one of the key STCOs or system technology co-optimization concept. SoC type system is dis-aggregated, or partitioned, into smaller modules (or chiplets) that can be asynchronously designed by dispersed teams, and later combined into a larger, highly flexible system using chiplet-based package design.
In summary, silicon scaling has been slowing. Costs continually increase from node to node. Hetero-integrations (HI) provide new opportunities. HI is not another Moore’s Law. They fit distinct applications differently, and also come with a cost. IC industry will continue to grow, especially in data processing areas (data centers, auto drive, 5G, AI) etc. Those who can target these areas to specific customers and applications and can provide solutions at better cost will fare better. Future success requires more inter-disciplinary knowledge and engineering.
Beyond Moore with HI
Dr. Moonsoo Kang, EVP, Advanced Package (AVP) Business, Samsung Electronics, presented the road to Beyond Moore with heterogenous integration for next-gen computing.
Why do we need ‘Beyond Moore’? There is an increased need for new solutions due to the slowdown of Moore’s Law, and computing power solutions. There are three challenges:
- Cost: Moore’s law slowdown caused by technical difficulty, while cost continue to increase.
- Performance: Power efficiency and bandwidth are limited by physical constraint of chiplets.
- Memory bandwidth: Bottleneck of system performance is memory bandwidth.
We need ‘Beyond Moore’ and heterogeneous integration to mitigate development cost, and to improve performance. Moore’s Law slowdown was caused by technical difficulty, while costs continue to increase. We can have cost reduction with high yielding smaller chips and optimal process selection. We also have die size challenge. Increases of die size are done for needs of high performance. ‘Beyond Moore’ can make it better!
Samsung has launched a new advanced package (AVP) business unit to meet the increasing importance of advanced packaging. It provides flexible services to customers leveraging Samsung Semiconductor’s synergy platform. Samsung AVP heterogeneous integration platform is key here.
Low-power memory integration platform fan-out package provides size, thickness, and thermal performance benefits. It enables smaller form factor with fine pitch interconnection. It is minimizing PKG thickness without substrate, and enhancing thermal performance with thicker die. Samsung provides both panel and wafer level fan-out package solutions. FOPLP has been in mass production since 2018. FOWLP will be in mass production from Q4-23.
Samsung provides wide I/O memory integration platform. These are used in LLW DRAM application, and RDL-based lateral multi-chiplet integration. Samsung also provides high bandwidth memory integration platforms I and II. I-Cube (Si-interposer or embedded Si-bridge RDL interposer) enables larger interposer, more HBMs. and multi multi-die for AI/data center applications.
Samsung also has the Integrated Silicon Capacitor (ISC) solution. ISC leads to decoupling capacitor competitiveness in component level. ISC production ramp-up with capacitor density (1,350nF/mm 2) is expected in Q3-24.
Future will have high-bandwidth memory integration platform. Memory and logic will be in highly-integrated SiP for next generation of HPC applications. Samsung’s logic 3D IC platform roadmap has X-cube that can integrate any configurations of logic-logic stacking optimized for performance.
Now, there are technical challenges, such as power and signal integrity (PSI). Power integrity challenges are jitter noise due to power coupling noise, and IR drop by high-power logic operation ( >1kW). A solution is integrated silicon capacitor, and integrated VR. Next, signal integrity challenges are signal degradation for higher speed IP (SerDes 112Gbps), and cross-talk noise by design complexity. A solution is the design methodology, and low-loss material.
We also have thermal congestion issue. For multi-chip implementations, there is thermal cross-talk and different thermal limits as challenges. A solution can be thermal-aware design. 3D multi-stack implementation issue is next. There can be accumulated heat and resistance. A solution can be joint thermal enhancement, and thermal-aware design.
Collaboration among partners’ specialty and Samsung AVP’s HI platform to overcome rising challenges of semiconductors is necessary.
IFA Berlin 2023 to feature Sustainability Village, robotics, and more!
IFA Berlin 2023, to be held at Messe Berlin, Germany, Sept. 1-5, is now sold out! It is the best trade show in the world for consumer electronics and home appliances. It is spread across 26 halls and 130,000sqm. 48 countries will be represented by 2,059 customers. Over 180,000 visitors are expected from 144 countries.
IFA 2023 has exceeded 2022 both in terms of number of customers and square meters. All of our major customers have confirmed for the show in 2023. New customers to IFA account for 30 percent of the overall exhibition and sponsorship revenue in 2023. The USA will have 53 customers spread across 1,800 sqm. From the US market, there are speakers from Amazon, IBM, Meta, Nationwide, Paramount, etc.
Sustainability Village
This year, IFA 2023 will, for the first time, welcome a dedicated Sustainability Village with its own onsite ‘mend and repair shop’ tackling e waste, a sustainability stage that will host a comprehensive conference program on sustainability best practices, interactive workshops and a dedicated exhibitor area.
Exhibitors include Shelley, Fairphone, Miele, Fair Cobalt Alliance, Ambient Photonics, CleanR, Rhinosheld, IFA Nursery powered by Treedom, Wertgigant. ZVEI, VDA and ZVEH are hosting a House of Smart Living, and Miele is showcasing the Eco pod. There are 50 speakers
including Miele, Decarbonize, Treedom Fairphone , Ecovadis Global Reporting Initiative.
Alongside the content programme, there are three interactive Fairphone Workshops on Urban Mining. A volunteer ran Mend & Repair Workshop will run on Saturday 2nd September. Global thought leaders will share how they, and their organizations are rising to complex challenges and demonstrating tangible results that drive efficiencies.
IFA NEXT
Taking over Hub 27, we see over 400 startups, up from 127, from across the globe showing us the next big things the tech Industry has in store! Our own dedicated IFA Next Stage Area will be showcasing inspiring entrepreneurs, fierce pitch battles and industry experts.
BSH Startup kitchen is an area full of the latest kitchen and cooking specific tech. Spacious
Investors lounge, where, with our partners Funded House, we will help connect the most exciting founders of over 100 startups with knowledgeable investors.
Startup Safari guided tours will take place twice daily for an easy way to view a wide selection of this years. Over 200 investors are registered, including representatives from Earlybird, Pegasus Tech Ventures and Techstars. Berlin Startup Night are full of partners and are bringing a selection of their brightest startups.
IFA Leaders Summit
IFA Leaders Summit will be a high-level content program. Exclusive main stage will have the most influential figures in the industry coming together to explore the most critical and meaningful topics that are shaping consumer electronics and home appliances today.
From technologists, innovators, and inventors to retail executives, thought leaders, and influencers, we will bring together the most radical thinkers. Latest developments in the next-gen tech, the future of smart homes, IoT trends, AI-powered devices, robotics, cloud gaming, the changing face of retail, and much more, will be on display.
Diversity, equity and inclusion (DE&I) program has a dedicated stage for women in tech and allies who will speak about how to accelerate progress towards diversity and inclusion in the tech industry. Key themes are the path to Artificial General Intelligence (AGI); the future of humanity depends on diversity; Leveraging technology for DEI; Reducing bias in the digital age; and Creating safe and inclusive culture.
House of Robots
Established within the Robotics Hub, the House of Robots is an immersive experience, brand new for IFA 2023.
This activation will display four of the leading robotics providers from across the globe, providing visitors an opportunity to experience, interact and learn about such a range of different robots.
- Miroki by Enchanted Tools: Founded by Jérôme Monceaux, who had already helped create the robots Pepper and Nao, Enchanted Tools recently unveiled Miroki, the prototype of a new generation of humanoid robots that are both wondrous and useful. Mirokaï is part of a ground breaking new species of service robots created by Enchanted Tools (ET), addressing worker shortages in essential sectors like healthcare. ET is composed by a team of 50
mechatronics and AI experts, led by Jérôme Monceaux, former EVP at Aldebaran/Softbank Robotics, and co-creator of robots Nao and Pepper. - Circle Assembly Robot and Robot Dog Spot by CeTI: Both a large scale, detailed industrial robot displaying the efficiency of Robots and the roaming, interactive animal inspired Dog Robot, presented by research centre CeTI.
- Desi by SingularityNET: Desi is a humanoid robot and the lead vocalist of the Jam Galaxy Band. Desi runs on music and electricity, and is on a mission to share her belief that the world can be changed for the better through the power of AI in the creative arts.
- Go2 by UniTree: An other RobotDog, with a self developed 4D LIDAR L1 with 360×90 hemispherical ultra-wide recognition, super-small blind spot and a minimum detection.
At IFA 2023, Desi will not only be on display at the House of Robots but also perform a bespoke, never before seen duet with a DJ at the Opening Reception. Desi will go on stage with SingularityNET’s COO during the DE&I event.
We will also have the Berlin Tech Week. Key highlights will also be presented by Honor, HiSense, FC Union Berlin, SpaceX, KWEBBELKOP, etc.
Visitors can also get to see the sights of Berlin, such as the Brandenburg Gate, Checkpoint Charlie, Reichstag, etc. For those interested, The Brandenburg Gate is an 18th-century neoclassical monument in Berlin, built on the orders of Prussian king Frederick William II after restoring the Orangist power by suppressing the Dutch popular unrest.
Checkpoint Charlie was the best-known Berlin Wall crossing point between East Berlin and West Berlin during the Cold War, as named by the Western Allies. The Reichstag is an internationally recognizable symbol of democracy and the current home of the German Parliament.
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