EDA

Evolving to a world of smart everything: Dr. Aart de Geus, Synopsys

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Dr. Aart de Geus, chairman and co-CEO, Synopsys, graced the ongoing SNUG India 2018, being held in Bangalore.

He delivered the keynote titled, “At the Heart of Impact,” discussing how the demand for computation power is changing virtually all industries — from automotive to healthcare to financial services.

AartSilicon has arrived at a state that is now making software possible that we only could dream of years ago. The world is moving into its next age: the age of smart everything. If you look at chips, there’s only one word and that’s called Moore’s Law. This is easily being the single, or most rapid sustained exponential in the existence of mankind.

The push to smaller geometries, which has been predicted as ending so many times. Moore’s Law is supposedly dead, and yet, Moore’s Law is now more expensive, but, it’s certainly not dead! We also have the opportunity to count the first 500 designs in each technology. FinFETs were impossible and too hard to do, but, here we are! The most advanced chips have all moved to this!

Let’s propose a thinking model of how to look at what EDA really is. The first question is: can you capture it on a computer? If you can capture it, can you actually model its behavior? If you can model it, can you simulate? If you can simulate, can you analyze a result? If you can understand the analysis, can you optimize, and if you can optimize, can you ultimately automate?

Digital twin
Digital simulation first, and then synthesis, completely changed the productivity picture in our field. The productivity push has continued. The notion of IP re-use, which, itself is not new, as transistor became gate, became register, became a small processor, became ultimately, big building blocks. The notion of a digital twin is essential.

AI is interesting, because it parallels somewhat, the history of EDA. You have to bring together data, collect the data, structure it, so that it’s usable. We have a lot of data in our programs. In the case of AI, it’s called learning, rather than simulating. That learning is then interpreted on the EDGE devices actively to ultimately, i.e., that creates some limited action field, and the long-term goal is autonomous behavior in many different fields. We have seen some remarkable advances that may initially not have gone quite as high as what we’re all familiar with, but the notion of a digital twin is essential.

There are four forces to understand. The first two, actually act in tandem. More computation allows for more machine learning, and more machine learning wants one thing more, even more machine learning, which we’ll push on more computation. This statement will drive the semiconductor industry for the next few decades.

The consumption of silicon will increase significantly. It is accentuated by one more thing: more data. Big data is a common term at this point. If you look at the number of sensors that are being put all over the world and all kinds of products, the amount of data that is becoming available is so large that it’s even difficult to make sense of it, unless you applied the very machine learning techniques that are now very rapidly evolving.

You need quantum physics to predict. Its called Ab Initio, means, from the start. It’s fundamentally going to the very basic of physics that are applicable to the atomic-molecular level. This technology is at Synopsys. We also added to this super-fine meshing to be able to describe the devices, and the ability to extract parameters.

We have invested in and are working with a number of partners on DTCO or design technology co-optimization. It has one objective. What do I tweak in the technology so that the design gets better?

If you look at the car, this is a source of data like you haven’t seen before: cameras, many RADAR, LIDAR, ultrasonic, and others. These cars are going to generate about four terabytes of data per day. This is where the cloud and AI machine learning will continue to blossom and grow at an unbelievable speed.

Simulation essential
Simulation is going to be essential in the digital world. It will take many more dimensions. We are very much focused on the digital electronic side of things.

What made it all work is the fusion of three things. Logic, optimization, that was the heart of it, but also, in parallel, integrated timing, and the notion of libraries.

On the electronic side, we have all the necessities to the modeling and of the simulation. We have invested and grown the capability to do device simulation for photonic devices and the simulation of those. We have even incorporated RedHawk inside of IC Compiler II.

Now, EUV is coming into the picture and many other materials accentuate this. We have invested massively by working closely with all of the most advanced fabs in the world.

Vision processor is a fusion itself of multiple things. Synopsys actually has put quite a bit of effort in that as a building block. Our vision processor has a CPU that can have up to four cores, each made up of a scalar CPU, and a bit vector DSP. Around that is a convolution neural network that help do a number of the tasks. The interpretation of the neural network learning data in a common implementation platform and with all the software that makes this possible.

Safety and cars have already been a theme for us. Automotive IP does have needs. There’s a substantial number of standards around that.

Energy distribution
Let’s also look at the notion of energy distribution. Are you going to put big cables to tank stations? How do you get it there? Is it local energy generation and by the way can we use that to deal with some of the clean energy needs to fix everything. It’s quite remarkable to find out that Tesla, which is aiming at being an electric car by increasing the autonomous car, also has a battery business, and has an energy distribution business by putting recharging stations, energy generation by owning a solar cell company.

Synopsys has invested in a number of things around security on a simple premise: all systems have inputs and outputs. They very quickly turn it to digital data, into electronic systems that are really systems on a chip, that are compute systems, really bring software, and the software itself is algorithms and proprietary code, and more dangerously so, third-party code and open source code vulnerabilities.

Today, networking the cloud is just one big computational continuum, that is now refining itself and becoming savvy. Be ready for the next phase! That absolutely has started and is upon us. The age of smart everything is happening at an incredibly fast clip and will have a very big impact. It will have an impact at a human evolutionary scale.

All the market segments are digitizing themselves. The semiconductor ecosystem is at the center of making this happen. This transformation is changing and challenging the semiconductor industry as we evolve to a world of smart everything that is networked, mobile, and also under increased pressure to become more secure. Synopsys is both humbled and privileged to be in the midst of this transformation.

Dr. Pradip K. Dutta, group VP and MD of Synopsys India and Sri Lanka, said: “As we move closer to completing two decades of SNUG in India, we are committed to making it the leading platform for the electronic design engineering community to connect with each other and learn to innovate from silicon to software. As the semiconductor industry and the ecosystem evolve with the accelerating pace of digital transformation, the center of gravity is moving to the intersection of hardware and software.”

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ITC India to address design, test, and yield challenges

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The forthcoming International Test Conference (ITC) will be held on July 22nd-24th, 2018, at the Radisson Blu Hotel in Marathalli, Bangalore.

I must thank Navin Bishnoi, General Chair, ITC India, and director, ASIC India Design Center, GLOBALFOUNDRIES, and Veeresh Shetty, senior marketing manager, Mentor, for apprising me of developments.

The second edition of the conference, it is the world’s premier event dedicated to the electronic test of devices, boards and systems. At ITC India, design, test, and yield professionals can confront challenges faced by the industry, and learn how these challenges are being addressed by the combined efforts of academia, design tool and equipment suppliers, designers, and test engineers. The ITC India is being run under the guidance of ITC USA, and is supported by the IEEE Bangalore Section and IESA.

NavinLet’s look at the test challenges that the conference seeks to address. Navin Bishnoi said:  “DFT, test and reliability domains are seeing a huge focus with the need of standard test practices for a variety of applications across communication, automotive, computing and industrial.

“In addition, the cost of implementation and testing continues to be challenged, asking designers to look at innovative ways to optimize test, without impacting quality. ITC India brings the best minds from academia, research and industry to share best practices to enable the standard DFT/Test practices for variety of applications with reduced cost and high quality.

“The conference covers sessions on emerging test needs for topics such as: artificial intelligence, automotive and IoT, hardware security, system test, analog and mixed signal test, yield learning, test analytics, test methodology, benchmarks, test standards, memory and 3D test, diagnosis, DFT architectures, functional- and software-based tests.”

Next, what is the focus on DFT architecture and DFT strategy in automotive and other devices with low-cost testing requirements?

He added: “Today’s automotive safety-critical chips need multiple in-system self-test modes, such as power-on self-test and repair, periodic in-field self-test during mission mode, advanced error correction solutions, redundancy, etc. The conference has numerous presentations on summarizing the implications of automotive test, reliability and functional safety on all aspects of the SoC lifecycle, while accelerating the time-to-market for automotive SoCs.

“There is a strong focus on understanding the increasing use of system-level tests to screen smartphone and notebook processors for manufacturing defects by taking an in-depth look at the limitations of state-of-the-art scan test methodology. In addition, there is continuous study in the fields of DFT, diagnosis, yield learning, and root cause analysis, which use machine learning algorithms for solving various problems.”

Trends in modelling
Let us also look at the the trends in modelling and the simulation of defects in analog circuits and their applications that the conference seeks to address.

Bishnoi said that digital circuits have now evolved to standardize fault modeling and simulation. However, analog circuits have work in progress to look at new methods for modeling and simulating different types of faults using a mixed-signal fault injection methodology.

“Modeling defects in analog circuit use transient analyses that leverage different methods to inject faults. This is critical for today’s use case applications, like automotive, sensors, and industrial, which has significant analog components in the SoC. One of the trends that will be addressed in the conference is the layout-based fault modelling that is in fact a statistical analysis of process defects.

Now, to the directions made in advanced packaging technology. What’s the road ahead?

Bishnoi added: “Packaging technology has exploded with complexity in recent times for need of stacked dies, which involves change in processes, materials, equipment, as well as in the SoC implementation and sign-off. Advanced packaging enables small form-factor chips, with high-speed functionality for consumer market.

And, how are challenges in analog loopback testing for RF transceivers being addressed?

He said: “The main challenge in the implementation of loopback testing for RF transceivers is distinguishing the non-linearity effects of Rx and Tx, performance of channels during parallel testing, as well as coupling effects. Various test solutions will be discussed during the conference to address the challenges of an analog loopback testing of RF transceivers. Solutions employing the BiST techniques to have a quick TAT during manufacturing test will also be discussed.”

For those unaware, BiST or the built-in self-test, is a design technique in which parts of a circuit are used to test the circuit itself.

Finally, which version of the conference is this? Are we going to see regular ones? Bishnoi noted: “This is the second edition of the conference. We went through rigorous analysis and discussions with global leaders about the frequency and venue of the conference. It was decided to keep it annually (with the amount of growth in test/reliability space), as well as to keep it in Bangalore for the first 5 years, before we review it again to check if we should take it to other cities in India.

“The conference includes four keynotes from visionary leaders from Synopsys, Tessolve, Intel and Mentor Graphics, an exciting panel discussion on Fault Tolerance or Fault In-tolerance, as well as a variety of technical sessions and exhibits/demos from sponsors. It also has a dedicated day (on Sunday) for tutorials on six topics covering automotive, analog test, IEEE standards, machine learning in-test, system-level test and security.”

I will be present at ITC India 2018 in Bangalore, and look forward to meeting many of you, the attendees, as well! 🙂

Cadence @ DAC 2018: Electronic systems and semiconductor design for cloud

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Cadence Design Systems made a host of announcements at the ongoing 55th Design Automation Conference, at Moscone Center, San Francisco, USA. These are:

  • Cadence delivers the first broad cloud portfolio for the development of electronic systems and semiconductors.
  • Cadence collaborates with Amazon Web Services (AWS) to deliver electronic systems and semiconductor design for the cloud.
  • Cadence and Microsoft collaborate to facilitate semiconductor and system design on the Microsoft Azure Cloud platform.
  • Cadence collaborates with Google Cloud to enable cloud-based development of electronic systems and semiconductors.
  • Cadence launches Liberate Trio Characterization Suite employing machine learning and cloud optimizations.

Very interesting!

I caught up with Carl Siva, VP of Information Technology, Cloud, Cadence Design Systems Inc. and Craig Johnson, VP of Cloud Business Development, Cadence Design Systems Inc., to find out more.

First, why has Cadence chosen to go the cloud way now?

CarlCarl Siva said: “Designs are continuing to become more complex, process nodes are getting smaller, and the volume of chip design data is increasing exponentially, and creating peak compute needs. Traditional data center models of company-owned, -housed, and -managed cannot support peak needs.

“Cadence has been engaged with cloud vendors and customers on this topic for several years. Our decision to launch our portfolio now is based on the increased customer interest and their growing confidence in the security of the cloud. Cadence’s cloud approach has been proven internally. So, it was logical to draw upon that extensive experience to drive customer adoption, so that they can achieve the productivity, scalability, security and flexibility benefits of the cloud.”

The Cadence Cloud portfolio includes customer-managed and Cadence-managed cloud environments. What’s in there and how are they different?

Craig Johnson, VP of Cloud Business Development, Cadence Design Systems Inc., said: “The Cadence Cloud portfolio offerings are targeted toward small-, mid-sized and enterprise- systems and semiconductor companies, providing improved productivity, scalability, security and flexibility benefits. For example, the platform can enable customers to gain access to dedicated compute resources in as little as five minutes.

“With the Cadence Cloud-Hosted Design Solution (the Cadence-managed option), small companies benefit from this offering because it eliminates the need for a costly internal infrastructure and the overhead from a large Computer-aided design (CAD) and IT staff, allowing these companies to focus on chip design innovation.

“Mid- to large-sized companies also benefit because the Cadence-managed environment allows them to move an entire design project or team to offload the strain on their on-premise environments. It also includes the Palladium Cloud, a managed and scalable emulation environment for customers desiring to use our hardware without the responsibilities of equipment installation or maintenance.

“With the Cadence Cloud Passport model (the customer-managed option), mid- to large-sized companies that have the means to manage their own cloud infrastructure internally and small companies that are cloud-savvy can use Cadence software tools via their current IaaS provider.

“The Cadence Cloud Passport model includes the Cloud-ready Cadence software tools that have been tested for use in the cloud, a cloud-based license server for high reliability, and access to Cadence software through familiar download mechanisms.
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Mentor-THE GAIN to boost India’s ESDM startup ecosystem

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Mentor, a Siemens business, has announced a strategic collaboration program with THE GAIN (The Global Accelerator for Innovation Network) – a technology accelerator company, focused on product engineering IP startups.

MentorBoth organizations will work with innovative Indian startups to accelerate, develop and customize IP to address domestic and international markets. They will focus on accelerating India’s product engineering IP ecosystem by helping companies in the early stages of entrepreneurship.

Established to advance the ESDM (electronics system design and manufacturing) ecosystem in India, the collaboration’s goal is to foster excellence in the early stages of startup companies. Both will work closely with the startups and entrepreneurs looking to establish and launch companies in the product engineering space, with a special focus on engaging with startups in the early phase of entrepreneurship.

“Mentor has established an outstanding track record of supporting, developing and accelerating startup ecosystems, both in India and across the globe,” said Raghu Panicker, Mentor’s country sales director for India. ”Through this strategic collaboration, we look forward to further accelerating the India startup ecosystem by working closely with promising product companies to make them successful.”

“India’s ESDM ecosystem is on a growth trajectory thanks to the ‘Make in India’ focus by the Indian government,” said Poornima Shenoy, CEO of THE GAIN.

“This collaboration with Mentor, a global technology leader, will have distinct benefits to startups looking to grow and succeed. It is our shared vision to collaborate and support highly successful startups in India who deliver innovative products. We are looking at accelerating the growth of at least 30 companies in the next three years.”

Outlining the specific steps Mentor-GAIN will be taking to help India’s product engineering IP ecosystem, she said: “At THE GAIN, we are looking to “excellerate” no more than five to seven start-ups per year. This is after a multi-tier rigorous selection process. Our entrepreneurs are often with deep industry knowledge and experience, who need a lead time of two-three years to prove the business and product viability.

“Tools are amongst the highest overheads in this journey. Here, the role of companies like Mentor, would be crucial. They have use cases, knowledge of decades and special schemes for entrepreneurs. This provides the right balance between cost and success. They also have leaders who understand and ‘walk the talk’.

“India needs to have more success stories with IP companies. We are looking at product engineering as a step in that direction. It is necessary for us to accelerate growth by productizing IP and leveraging global partnerships. It is not about overnight success, but about long-time multiplier returns. Our country and the industry needs to move in that direction.

“This is a unique partnership where both partners understand what works and what are the factors relevant to success.”

Justifying innovativeness
How does one justify ‘innovativeness’, when the two entities will support startups with innovative products?

Shenoy added: “It is a global race for innovation. We are looking for companies for the development of products, services, and applications related, to smart living and industry 4.0. India is a big market, but one, which is hugely price-sensitive.

“Our focus is on the B2B space and how soon can we get solutions out into the market in these areas. Innovation can save you money, help the environment and widen your market base. It could address niche segments and verticals. We are seeing interest from start-ups in other geographies to address this vibrant and dynamic marketplace. Global solution providers, like Mentor, function seamlessly across borders.

“At THE GAIN, we partner with innovative entrepreneurs by providing them with access to funding, active mentoring and to business. We can move to the next rung if they create MVP and validate it with their target customer base. This is a key area where they need assistance.”

Old wine! New bottle?
Finally, hasn’t this exercise been tried before? How are they confident about its success?

Shenoy said: “Every partnership is the start of a new beginning. It is only when we try that we can succeed. We are sure that as we embark on this journey on building the ecosystem and providing a platform for the Indian startups , we will learn and grow.

“We might slip up at times, but that is the beauty of a partnership. We learn together! In India, we have hardly seen any focus on this vertical. This understanding is a step in the right direction and a vital link to future success.”

Expressing his opinion on what Mentor is gaining out of this partnership, Raghu Panicker of Mentor, elaborated: “Mentor gains access to start-ups in the ideation stage itself. Mentor can, then, nurture them, and help start-ups with technologies in the areas of chips and system design. Start-ups are usually open to looking at new technologies.”

THE GAIN is a technology accelerator headquartered at Bangalore and founded by BV Naidu, former STPI director-turned-entrepreneur. The organization focuses on accelerating early-stage companies through access to funding, access to active mentoring and access to businesses.

Friends, if this interests you, please contact either Ms Poornima Shenoy at The GAIN or Raghu Panicker at Mentor. Best of luck!

Focus on system design as ESD Alliance-SEMI sign MoU

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Earlier this week, the ESD Alliance recently signed a memorandum of understanding (MoU) to join SEMI as a strategic association partner.

BobAs a SEMI strategic association partner, the ESD Alliance will continue to act as the central voice of the semiconductor design industry to promote its value as a vital component of the global electronics manufacturing supply chain.

Bob Smith, executive director of the ESD Alliance said: “SEMI and the ESD Alliance (formerly EDAC) have had a good relationship for many years, but there was certainly no pre-existing timetable to bring SEMI and the ESD Alliance together.

“The increasing focus on system design, and the need for manufacturing and design to be more closely linked have certainly been drivers for collaboration.

“Several years ago, SEMI expanded their mission to span the entire electronics product manufacturing chain including design. Since the ESD Alliance represents design, it is a natural fit for the ESD Alliance to fill-in this part of SEMI’s mission.

“From the ESD Alliance standpoint, we benefit by being able to leverage SEMI’s global platform to build our community. Although, we have members outside of North America, we don’t have any local presence outside of the US. SEMI has offices across the globe that will allow us to bring our programs to other areas of the world.

“Next, it is a good fit in the increasing the collaboration that’s required between design and manufacturing. In fact, many of SEMI’s member companies had asked them for deeper access to the design community.”

Now that product design has been added the to electronics manufacturing supply chain,  it will bring manufacturing and design closer together by being common members of SEMI, he added.

What are the ways that SEMI gives the ESD Alliance an opportunity to further expand its reach and grow to its full potential?

Smith added: “SEMI will help expand ESD Alliance’s global presence by offering programs and events in conjunction with SEMI’s worldwide platform. Expand programs/activities in education, collaboration and networking to our members and SEMI members that are interested in design.

“We can also grow the membership further by offering more programs and being active in other geographies beyond North America.”

MOS memory investors, China to correct DRAM imbalance

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penn1According to an IC Insights report, the 47 percent full-year 2017 jump in the price-per-bit of DRAM was the largest annual increase since 1978, surpassing the previous high of 45 percent registered 30 years ago in 1988! This sounds interesting!

Are the rising DRAM prices aiding startup Chinese competitors? Are major DRAM suppliers somehow stunting global DRAM demand?

Dr. Walden C. Rhines, president and CEO, Mentor Graphics, a Siemens Business, said: “The DRAM business has always gone through cycles of imbalance between supply and demand. Growth of demand in the last 18 months has been stronger than growth of supply.

“Substantial investments in 2017 by the MOS (metal-oxide semiconductor) memory producers, as well as the addition of China to the supply chain, will correct this imbalance late this year or, at the latest, early next year.”

The DRAM price-per-Gb has been on a steep rise. To this, Dr. Rhines said: “It is a commodity, although there are many types of specialty DRAMs emerging. Because DRAMs are viewed by customers as a near-commodity, the price is heavily influenced by the availability of supply. Supply has been very tight during the last 18 months.

Malcolm Penn, chairman and CEO, Future Horizons, UK, added, “This is supply and demand, pure text-book economics.”

Are the rising DRAM prices opening the door for startup Chinese competitors?

Dr. Rhines noted: “Chinese competitors made their decision to invest in DRAM capacity long before the recent strengthening of demand in the balance of supply and demand. Of course, higher, or stable, pricing may make it easier for new producers to absorb the costs of ramping up new capacity and developing experience with a new technology.”

Malcolm Penn agreed: “Potentially yes, and to anyone else. Coca Cola were contemplating building DRAMs in the 1990s. DSRAM market boom, again, pure text-book economics. Whether or not they succeed is an entirely different matter. If the Chinese do enter the market, can they then survive the inevitable downturn and cycles? That remains to be seen!”

Can the startup Chinese DRAM producers field any competitive product soon? Dr. Rhines noted: “They probably can. But, they will have to develop a production base of “learning” to reduce cost, improve yields and maybe even reliability. This will take some time.”

Penn added: “Technically (i.e., meeting the spec), probably, yes. Reliability, probably no, for the Tier 1 customers (that will take several years to build up the production experience). Cost, definitely not!

“Their small fab scale and late learning curve start means that their die cost will be sizably higher than those of Samsung and SKH, and also Micron. Plus, their yields will be lower. Then, there’s the deep cash pockets issue to fund these ongoing cost disadvantages.”

300mm fabs
In a separate situation, some 300mm fabs closing, for example, ProMOS. Dr. Rhines said: “It’s because of an imbalance of supply and demand for the products they make, thus limiting their profitability. It could also be because they don’t see an adequate investment return from the expensive new capacity investments, and therefore, find it more attractive to phase out some of their existing capacity.”

Malcolm Penn felt that the fabs were too old and technically obsolete.

Finally, are there more IC companies making transition to fab-lite or fabless business model?

Penn noted: “There’s no-one left to change! Everyone’s now fablite or fabless, except for Intel and Samsung (logic) and the memory manufacturers.”

Dr. Rhines said: “Based upon the growth of foundry revenue vs. total semiconductor revenue growth, there must be a continuing transition of capacity away from IDMs toward foundries. In addition, IDMs like Samsung are finding it economic to build the foundry business to increase the volume base of products that utilize their technology and capital investment.”

PSS complementary to UVM: Dr. Wally Rhines

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Here is the concluding part of my discussion with Dr. Walden Rhines, chairman and CEO, Mentor, A Siemens Company.

Has the PSS been formally released? What are its implications?

RhinesDr. Rhines said: “Accellera released an Early Adopter spec for public review at DAC in June, 2017 and is currently working on completing our work in preparation for a 1.0 release in 2018. Accellera plans to have a “1.0 Preview” version available in February, 2018 (@DVCon US) for another 30-day public review period. Then, they will do one more cleanup pass, and submit to the Accellera Board for approval in May 2018.

“The expectation is that the Board will approve the Portable Stimulus Standard 1.0 version in June, 2018, prior to the DAC. Mentor plans to have Questa inFact fully updated by then, to fully support the new standard when it comes out.

“As for the implications, we expect the Portable Stimulus standard to be the next advancement in abstraction and productivity for SoC verification. It is not expected to replace UVM, but rather be complementary to UVM to improve coverage closure, verification efficiency, and effectiveness at the block level.

“The ability to re-use the verification intent expressed in PSS from a block-level UVM environment to a software-driven, embedded-processor SoC environment, on multiple platforms (simulation, emulation, FPGA prototyping, etc.), will provide a quantum leap in productivity.

“Since the Portable Stimulus specifications are declarative, tools can fully analyze the verification-intent description at the system level and generate multiple correct-by-construction implementations of use case tests, on multiple platforms, from a single specification without requiring the verification team to rewrite the tests in UVM for the blocks and C for the system.

By the way, are the semiconductor/EDA companies re-looking at designs, rather than analyze more than 500,000 defective parts every day to identify design and process problems? If yes, how?

He said: “With today’s increased design complexity – they do both – re-look at designs before manufacturing and analyze afterwards. The complexity of today’s designs and manufacturing process requires multiple approaches to achieve high yields in each new node that is rolled out.

“Design for manufacturing and for yield are a must. However, the knowledge of the specific design practices that need to be followed for a new node is developed in multiple stages: in pre-silicon, test chips, first production design and when chips reach high production volume.

* Pre-silicon: Simulation models are used for initial design rules. Many assumptions are made and care must be taken to balance the benefit with potential overdesign for a process that will mature over time.

* Test chips: Early test chips try to mimic the major features of a real design, however, limited complexity and volume means some design rules can’t be discovered at this stage.

* First production design: Additional complexity of a real design and increased volumes expose more issues that need to be fed back to design for future revisions or the next design on a node.

* High production volume and additional designs introduced: High production volume and each subsequent design can benefit from the learnings at the previous stages. Many issues during this phase are resolved with process improvements, but continuous learning still remains key.

“The challenge is not eliminating the later learning phases, as this will never go away. Rather, the challenge is for the industry to maximize the learning at each phase and establish a continuous improvement cycle in design to take advantage of the knowledge gained. This is the foundational idea in closed-loop DFM, which is a process to maximize the design for manufacturing benefit throughout all phases.

Let’s also look at verification. What is the latest regarding coverage and power across all the aspects of verification?

Dr. Rhines added: “Actually, the recent trends have expanded to multiple concerns that cut across all aspects of verification, beyond coverage and power, such as security and safety. One driving force behind these trends is the convergence of computing, networking, and communications technologies. This is driving new markets, such as the Internet-of-things (IoT) ecosystem and automotive.

“A common theme across these emerging systems is the need for security, safety, and low power–whether you are talking about IoT edge devices or high-availability systems in the cloud. These new challenges have opened innovation opportunities, enabling us to rethink the way we approach verification. For example, concerning coverage, new statistical metrics have emerged providing deep system-level analysis capabilities that leverage data analytics techniques. This insight has become essential for system-level performance analysis.
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