Disruptive innovation with Xilinx Versal ACAP super FPGA

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Xilinx Inc. recently announced Versal – the super FPGA. Versal is said to be the first adaptive compute acceleration platform (ACAP), a fully software-programmable, heterogeneous, compute platform.

Versal ACAP combines scalar engines, adaptable engines, and intelligent engines to achieve dramatic performance improvements of up to 20X over today’s fastest FPGA implementations, and over 100X over today’s fastest CPU implementations—for data center, wired network, 5G wireless, and automotive driver-assist applications.

Versal ACAP
Versal is the first ACAP by Xilinx. What exactly is an ACAP? For which applications does it work best?

Victor Peng

Victor Peng, president and CEO, Xilinx, said: “An ACAP is a heterogeneous, hardware adaptable platform that is built from the ground up to be fully software programmable. An ACAP is fundamentally different from any multi-core architecture as it provides hardware programmability, but, the developer does not have to understand any of the hardware detail.

“From a software standpoint, it includes tools, libraries, run-time stacks and everything that you’d expect from a modern software-driven product. The tool chain, however, takes into account every type of developer—from the hardware developer, to embedded developer, to data scientist, and to framework developer.

Differences from classic FPGA and SoC
Now, that means there are technical differences in the Versal from a classic FPGA and to an SoC.

He said: “A Versal ACAP is significantly different than a regular FPGA or SoC. Zero hardware expertise is required to boot the device. Developers can connect to a host via CCIX or PCIe and get memory-mapped access to all peripherals (e.g., AI engines, DDR memory controllers).

“The Network-on-Chip is at the heart of what makes this possible. It provides ease-of-use, and makes the ACAP inherently SW programmable—available at boot and without any traditional FPGA place-and-route or bit stream. No programmable logic experience is required to get started, but designers can design their own IP or add from the large Xilinx ecosystem.

“With regard to Xilinx’s hardware programmable SoCs (Zynq-7000 and Zynq UltraScale+ SoCs), the Zynq platform partially integrated two out of the three engine types (Scalar Engines and Adaptable Hardware Engines).

“Versal devices add a third engine type (intelligent engines). More importantly, the ACAP architecture tightly couples them together, via the Network on Chip (NOC) to enable each engine type to deliver 2-3x the computational efficiency of a single engine architecture, such as a SIMT GPU.”

Does this mean that Xilinx will address, besides the classic hardware designers, the application engineers in the future?

He noted: “Xilinx has been addressing software developers with design abstraction tools as well as its hardware programmable SoC devices (Zynq-7000 and Zynq UltraScale+) for multiple generations. However, with ACAP, software programmability is inherently designed into the architecture itself for the entire platform, including its hardware adaptable engines and peripherals.”


Global semicon industry likely to grow +4.4pc in 2019: Dr. Wally Rhines, Mentor

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Happy new year, to all of you. 🙂 And, it gets even better, having a discussion with Dr. Walden C. Rhines, CEO and Chairman of the Board of Directors of Mentor, A Siemens Company, on the global semiconductor industry trends for the year 2019.

Semiconductor industry in 2018, and 2019
First, I needed to know how did the global semiconductor industry performed last year? And, what is the way forward in 2019.

Dr. Walden C. Rhines.

Dr. Wally Rhines said: “2018 was another strong growth year for the global semiconductor. IC bookings for the first 10 months remain above 2017 levels and silicon area shipments for the last six quarters have also been above the trends line, with fourth quarter YoY growth 10 percent. And, IC revenues overall continue to have strong double-digit growth for 2018, with fourth quarter YoY growth of nearly 23 percent.

“However, analysts are expecting much more modest growth in 2019. Individual analyst predictions for growth in 2019 vary from -2 to +8 percent, with the average forecasts at +4.4 percent.

“Much of this is due to the softening memory market, along with concerns about tariffs, inflation and global trade war. While the rest of the IC business has been relatively strong with Samsung and Intel noting solid demand for ICs for servers and PCs, sentiment by senior managers of semiconductor companies is near a record low level. So, I’m not expecting much growth, if any, in 2019 and more likely a decline.

EDA in 2019
On the same note, how is the global EDA industry performing, and what’s the path in 2019?

He said: “Revenue growth of the EDA industry continues to be remarkably strong, fueled by new entrants into the IC design world, like networking companies (e.g. Google, Facebook, Amazon, Alibaba, etc.) and automotive system and Tier1 companies, as well as a plethora of new AI-driven fabless semiconductor start-ups. Design activity precedes semiconductor revenue growth so it would not be surprising to continue to see strong EDA company performance even with a weak semiconductor market in 2019.

“EDA venture funding has rebounded, reaching a 6-year high of $16.5M showing a renewed confidence in the future of EDA. The major companies all have sighted better than expected results. On the semiconductor side of EDA there seem to be more technology challenges than the industry has faced in a long time.

“Some of those include new compute architectures, the emergence of photonics, increased lithographic complexities involving EUV and other techniques, new and more complex packaging, massive increases in data, and the multiplication of sources of design data (often created according to differing standards).

“The challenges on the system side of EDA are multiplying as expected. It is becoming more difficult to be at the leading edge when designing end-products in silos. Embedded software, mechanical, PCB, packaging, electrical interconnect, networking (access to the intranet) and security are just a few of the domains that need to work closer together in a more integrated manner. The increasing complexity is also making each of the domains more challenging. This all pushes new materials and methodologies into each of the domains listed above.”

Five trends in semicon for 2019
I wanted to find out about the top five trends in semicon for 2019.

He said: “The top five semiconductor technology trends include:
* the ongoing ramp of next-generation technologies, led by Machine Learning, Artificial Intelligence and cloud, and SaaS demand on the datacenter,
* the roll-out of IoT – especially in manufacturing,
* 5G development,
* computing on the edge, and
*the increasing semiconductor content within electrical devices.”

Global semiconductor industry trends 2019: Jaswinder Ahuja, Cadence

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Today happens to be my birthday! 😉 And, what better way to celebrate, with a discussion on the global semiconductor industry and the expected trends for 2019.

I caught up with my good friend, Jaswinder Ahuja, Corporate VP & MD of Cadence Design Systems India Pvt Ltd, and asked him about the global semiconductor industry trends for 2019. So, how is the global semicon industry performing this year? How does Cadence see it going in 2019?

Jaswinder Ahuja, Cadence.

Global semicon industry trends
Jaswinder Ahuja said: “The semiconductor industry is doing very well. Estimates say that it has crossed $400 billion in revenue. This growth is being driven by four or five waves that have emerged over the last couple of years. These are:

  • Cloud and data center applications are booming, and the top names in this space, including, Amazon and Google are now designing their own chips.
  • Automotive is (and has been) going through a transformation over the last few years. ADAS is just the beginning. From infotainment to safety, the whole vehicle is driven on precision electronics.
  • Industrial IoT is another wave. By incorporating artificial intelligence (AI) to manufacturing and industrial processes, we are looking at a revolution—what is being called Industry 4.0.
  • Mobile and wireless have, of course, driven growth in the last decade to decade-and-a-half, and it doesn’t show any signs of slowing down.
  • Consumer and IoT devices can also be considered a wave, although the consumer wave started some time ago. IoT is the game-changer there, with so many billion connected devices being forecasted in the next 5-10 years.

“Thanks to these technology waves, our sense is that the growth will continue into 2019, and probably beyond, especially as AI and ML become more prevalent across applications.”

Global EDA and memory industries
How is the global EDA industry performing this year? How do you see it going next year in 2019?

He said: “Cadence has seen strong results in 2018 so far across product lines. This is thanks to multiple technology waves, especially machine learning, that are driving increased design activity and our System Design Enablement strategy, as well as our continued focus on innovation and launching new products.”

And, what’s the road ahead for memory? Is memory attracting more investment?

He added: “The memory market is being driven by the data-driven economy, and the need to store and process data at the edge and in the cloud. Added to that is the huge demand for smart and connected devices, for which memory is crucial.

“There isn’t any data about investments, but keeping in mind the consolidation that is happening across the industry, it could well be that we may witness some industry M&A activity with memory companies as well. The merger of SanDisk and Western Digital is one such example.”

EUV lithography trends
Has EUV lithography progressed? By when is EUV lithography likely to get mainstream?

Ahuja noted: “As technology advances, both manufacturing and design complexity grow. Designs are being scaled down to meet the ever-increasing demand for more functionality contained in a single chip, creating unique implementation challenges.

“Manufacturing is facing huge challenges in terms of printability, manufacturability, yield ramp-up and variability. Unfortunately, restrictions on power, performance and area (PPA) or turnaround time (TAT) do not scale up along with these factors.

“Foundries have been talking about EUV for years now. However, the power and performance improvements with EUV don’t look very significant at this time. Clearly, there is still some distance to go, before EUV will become mainstream.

“On a related note, in February 2018, Cadence and imec, the world-leading research and innovation hub in nanoelectronics and digital technologies, announced that its extensive, long-standing collaboration had resulted in the industry’s first 3nm test chip tapeout.

“The tapeout project, geared toward advancing 3nm chip design, was completed using EUV and 193 immersion (193i) lithography-oriented design rules, and the Cadence Innovus Implementation System and Genus Synthesis Solution.”

Trends in power and verification
Finally, what is the latest regarding coverage and power across all the aspects of verification?

He said: “Over the past decade, verification complexity and demands on engineering teams have continued to rise rapidly. Applying innovative solution flows, automation tools, and best-in-class verification engines is necessary to overcome the resulting verification gap.

“With regard to verification coverage, the challenge is always to know when you are done (the process of verification signoff). Cadence has a unique methodology and technology for measuring and signing off on the design and verification metrics used during the many milestones typical in any integrated circuit (IC) development, and it is called Metric Driven Verification (MDV).

“While milestones and metrics vary by design type and end-application, the final verification signoff will, at a minimum, contain the criteria and metrics within a flexible, human-readable and user-defined organizational structure. Automated data collection, project tracking, dashboards and in-depth report techniques are mandatory elements to eliminate subjectivity, allowing engineers to spend more time on verification and less time manually collecting and organizing data.

“Power-optimization techniques are creating new complexities in the physical and functional behavior of electronic designs. An integral piece of a functional verification plan, Cadence’s power-aware verification methodology can help verify power optimization without impacting design intent, minimizing late-cycle errors and debugging cycles. After all, simulating without power intent is like simulation with some RTL code black-boxed.

“The methodology brings together power-aware elaboration with formal analysis and simulation. With power-aware elaboration, all of the blocks as well as the power management features in the design are in place, so design verification with power intent is possible. Power intent introduces power/ground nets, voltage levels, power switches, isolation cells, and state retention registers. Any verification technology—simulation, emulation, prototyping, or formal—can be applied on a power-aware elaboration of the design.”

SnapEDA-Samtec to accelerate design process

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Samtec is releasing new digital models for over 100,000 of its products on SnapEDA, the industry-leading circuit board design library. Traditionally, designers have spent days creating digital models – such as symbols and footprints – for each component in their respective designs.

ElizabethWith this Samtec-SnapEDA collaboration, designers can now easily discover, download, and design with over 100,000 ready-to-use Samtec connector models, helping accelerate the design process. The new models include USB, card edge, board-to-board, headers, and RF coaxial connectors.

Elizabeth Bustamante, CAD Manager, SnapEDA, spoke from San Francisco, USA, on why Samtec chose to go with SnapEDA. She said: “We’re thrilled to work with Samtec because they are one of the most in-demand connector manufacturers on SnapEDA. Our users will benefit greatly from these new PCB libraries that will save them days of time, and allow them to quickly design-in Samtec parts.

“Samtec chose SnapEDA because over half a million engineers use SnapEDA each year to select and design-in parts into their designs. With our massive community of hardware designers, and their high-quality components that are high in demand with our community, it was the perfect match.”

Competing against existing models
How will Samtec compete against other such existing models? She added: “It’s not so much that Samtec is competing to get their models into a design, but rather, their physical products. The digital model (or, what are in fact, manufacturing files), are really when they design-in comes to fruition.
1 - Samtec Symbol _ Footprint
“Samtec has high-quality and reliable products, and an incredible focus on service and support. I think, that’s why so many engineers trust their products. Ultimately, engineers will make the decision based on which specs are right for them, and the model is really the ‘icing on the cake’, after they’ve made that selection decision as a reward to help them design it in more easily.”

Samtec has over 100,000 new models on SnapEDA. The new models include USB, card edge, board-to-board, headers, and RF coaxial connectors, because the new models include USB, card edge, board-to-board, headers, and RF coaxial connectors. Since Samtec focuses on connectivity solutions, that’s where the focus was for this project. However, SnapEDA has millions of models for all kinds of products.

Boosting electronics designers’ productivity
How can electronics designers boost their productivity with free symbols and footprints for Samtec products? Elizabeth Bustamante said: “Finding high-quality models for the exact part number, in the exact format and version you need is actually quite difficult. With these models, Samtec’s Signal Integrity Team is working directly with defining every element.

“Additionally, SnapEDA’s translation technology ensures that it is available in every format. The commitment to quality, and the breadth of our database and design formats supported is why we’re the #1 parts library on the web in terms of traffic.

“On top of this, creating connector models (which these are) are especially time-consuming, due to their non-standard shapes, pitches, pads, and cutouts regions. Having these models available to download, designers can spend more time in improving their design, allowing them to focus on optimization and innovation.”

Finally, how are newer, unreleased digital models going to be handled? She said: “We have a popular service, called InstaPart, which allows the engineers to request any models in 24 hours, and fulfilled by SnapEDA’s in-house component engineering team. Furthermore, the SnapEDA and Samtec teams are working closely to deploy new models to the SnapEDA platform as they become available.”

It is really great to have a lady address the queries on behalf of an organization. Many congratulations to the SnapEDA-Samtec combine.

Self-driving cars pushing boundaries of IC testing: Nilanjan Mukherjee, Mentor

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Nilanjan Mukherjee, Engineering director, Tessent, Mentor A Siemens Business, presented the opening keynote on day 2 of the ITC 2018, on self-driving cars and how they are pushing the boundaries of IC testing.

IMG_20180724_112645Automotive ICs will grow from 7.4 percent in 2017 to 9.3 percent by 2021. New entrants are attracted by new revenue opportunities. Leading auto makers are planning to launch self-driving cars, such as Tesla, GM, Hyundai, Renault-Nissan, Toyota, Volvo, etc., as per the Boston Consulting Group. According to McKinsey & Co., 57 percent of customers globally, trust self-driving cars.

Increasing detection capabilities require higher compute performance. Higher compute requirements are accelerating the process node requirements. For the next decade, the number of gates will double every 2 years. There will be 2x more compression every 2 years, just to maintain the test cost. There is a huge increase in transistor processing, and trends will continue with the future 5nm/3nm nodes. Further scaling will require density increase, in addition to the pitch scaling.

Test requirements ensure that semiconductor devices remain defect free. They should also ensure that any new defects are quickly detected throughout the device’s operational lifecycle. Low defective parts per billion – the implications of defective parts in automotive apps, are more severe than in consumer apps. The defect coverage should cover all circuitry.

More defects and lower DPPB require better coverage. There are complete defect excitation considerations. The defects are prioritized by their physical likelihood.

Automotive grade ATPG provides a complete set of critical area-based fault models for manufacturing tests. Cell-aware test benefits are well documented. Additional user–defined fault models (UDFM) are targeting inter-cell defects and interconnect bridges and open defects. We have to find ways to reduce the test time for analog parts.

Typically low coverage is 70-90 percent for analog parts. Fault simulation allows one to determine portions not being tested. There is a need to eliminate the manual FMEDA metric estimates that are required for ISO-26262. The fault simulator can report the metrics automatically, eliminating untolerated faults, and achieving higher ASIL rating.

There are multiple modes of in-system testing. Key-on tests have very little time budget. Limited functions are tested. Key-off tests see comprehensive testing. The budget is 10x times that of key-on tests. Finally, online tests are challenging. They are periodic and incremental.

Mission-mode controller is the in-system test controller. It automates communication between the test instruments and the service processor.

The new VersaPoint test point technology gives 2-4 percent SAF coverage vs. LBIST (logic built-in self test) test points. That’s 2X-3X reduction in test time at 90 percent coverage. It also reduces deterministic ATPG pattern counts by 2-4X.

VersaPoint test points with observation during shift helps in fast in-system logic monitoring. This helps on an average to reduce the test times by 3-4X.

Requirements for future in-system test solutions:
* Able to apply any type of test.
* Able to add, modify and update the in-system tests during the entire lifecycle of an IC.
* Minimal system memory and incremental data.

Programmable deterministic BIST for FuSa (functional safety) include two levels of highly compressed patterns. This reduces the memory required to store the patterns on the chip.

In the non-destructive memory BIST, there are traditional memory BIST constraints. Memory is tested in small bursts of activity by making sure that the original contents of the memory is restored after test.

Austemper acquisition by Siemens brings solutions across all areas. It is a completely functional safety solution. There is safety analysis, so you can design an automotive for safety. It also has safety verification, and multi-domain fault injection, providing evidence to achieve ASIL compliance.

Automotive ICs have redefined the standard for quality of manufacturing.

To be, or not to be fault tolerant! Or fault intolerant?

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IMG_20180723_183441Semiconductors is a tough business, and definitely not for the faint hearted, said Suman Narayan, senior VP, for Semiconductors, IoT and Analytics, Cyient. If you are in DFT, you are in the insurance business. He was moderating a panel discussion on ‘fault tolerance vs. fault intolerance’.

Rubin Parekhji, senior technologist, Texas Instruments, said that a system is fault tolerant if there is no error. An app is fault tolerant if there is no intolerant fault. An affordable system should be fault tolerant. Which faults are important? How are hardware-software fault tolerant? For instance, if not done well, it will lead to bulky devices. There is a need to optimize and differentiate. There is a need to build fault tolerant systems using fault intolerant building blocks.

Jais Abraham, director of engineering, Qualcomm, said that device complexity has increased 6X times since 2010. There is a disproportionate increase in test cost vs. node shrink benefits. Are we good at fault finding? It’s our fault. Be intolerant to faults, but don’t be maniacal. Think of the entire gamut of testing. Think of the system, and not just the chip. Think of the manufacturing quality, and find remedies. Fault tolerance may mean testing enough such that it meets the quality requirements of customers, who are becoming intolerant. We continue to invest in fault tolerance architectures.

Ruchir Dixit, Technical director, Mentor,  felt that making a system robust is the choice. The key is the machine that we make, and whether it is robust. The customers expect a quality robust system. Simpler systems make up a complex system. Successful system deals with malfunctions. There are regenerative components. The ISO-26262 standard drives robustness.

Dr Sandeep Pendharkar, Engineering director, Intel, felt that there is an increased usage of semiconductors in apps such as ADAS and medical. Functional safety (FuSa) requires unprecedented quality levels. Now, DPPM has changed to DPPB.

Achieving near zero DPPB on the nearest node is nearly impossible. Fault tolerance is the way forward. How should the test flows change to comprehend all this? Should we cap the number of recoverable faults before declaring a chip unusable?

Ram Jonnavithula, VP of Engineering, Tessolve, said that a pacemaker should be fault tolerant, with zero defects. Fault tolerance requires redundancy, mechanism to detect and isolate faults. Sometimes, fault tolerance could mean reduced performance, but the system still functions.

Adit D. Singh, Prof. Electrical & Computer Engineering, Auburn University, USA, highlighted the threats to electronics reliability. These are:
* Test escapes – DPPM. Especially, escape from testing components. Also, timing defects.
* New failures occur during operation. They can also be due to aging.
* Poor system design, which are actually, no solution. There can be design errors and improper shields.

Test diversity helps costs. Design diversity helps fault tolerance costs. Design triplicated modules independently. Avoid correlated failures.

So, what’s it going to be? Be fault tolerant! Or, fault intolerant?

Automotive electrification drives use of design IP: Dr Yervant Zorian, Synopsys

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IMG_20180723_083209_2At the ongoing ITC 2018, Dr Yervant Zorian , Synopsys fellow and chief architect, delivered the keynote. He said that today, change is in automotive and IoT. There were 15 competitors in 2004, which became six in autonomous driving. Connected cars is growing at 25 percent, and 92 percent connected cars should be built in 2020.

As of now, we have around 100 million codes in 2017, which are moving on to 300 million by 2025. The emerging technology trends are:
* Semi-autonomous /autonomous vehicles
* V2V (Vehicle to vehicle)
* V2I (Vehicle to infrastructure)
* Cloud connectivity
* Security
* Target users all age groups

Automotive apps need different SoC architectures. There are high-end ADAS, infotainment and MCUs.

ADAS is among the fastest-growing auto app. Sensors are seeing a fusion of massive data. We act fast, post data interpretation. The more data we provide to ML, we can get better results, via machine learning. AI is another growing area. There will be AI chips worth $38.6 million by 2025.

Automotive grade IP reduce risk and increase safety.  Automotive test phases are in production test, power-on self-testing and in-field testing. Innovations benefit advanced designs on established nodes. We are now having EPPM below 1.

Automotive electrification drives the use of design IP. The amount and variety of IP is increasing. ASIL D/D is now ready for AEC-Q100 testing. Each Fin has to be accurate, to reduce repair. There is on-chip self-repair as well.

On logic side, ATPG is there for autonomous testing. The SoC-level hierarchical system automates. Fault diagnosis is done via the DDR PHY. Automotive grade IP (FS) reduces risk.

There is also the automotive safety integrity level (ASIL). ASIL levels of final product depends on implementation. Reliability, reduces risks. Mission-critical automotive ICs need ECCC.  Adding RAS is also important.

Automotive test phases include production test phase, power on phase and mission mode phase, respectively.

Power on-off and periodic self-test for mission mode are available. Periodic testing can be done block by block. We need to pay to attention to the safety manager. Also, M-BIST implementation is must for functional safety. There is the Synopsys M-BIST.

Security is very critical, once we are connecting cars. Secure hardware is the root of trust. The tRoot provides a chipset that cannot be tampered. There must be detection and protection. Safety, quality and security play important roles.