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SnapEDA-Samtec to accelerate design process

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Samtec is releasing new digital models for over 100,000 of its products on SnapEDA, the industry-leading circuit board design library. Traditionally, designers have spent days creating digital models – such as symbols and footprints – for each component in their respective designs.

ElizabethWith this Samtec-SnapEDA collaboration, designers can now easily discover, download, and design with over 100,000 ready-to-use Samtec connector models, helping accelerate the design process. The new models include USB, card edge, board-to-board, headers, and RF coaxial connectors.

Elizabeth Bustamante, CAD Manager, SnapEDA, spoke from San Francisco, USA, on why Samtec chose to go with SnapEDA. She said: “We’re thrilled to work with Samtec because they are one of the most in-demand connector manufacturers on SnapEDA. Our users will benefit greatly from these new PCB libraries that will save them days of time, and allow them to quickly design-in Samtec parts.

“Samtec chose SnapEDA because over half a million engineers use SnapEDA each year to select and design-in parts into their designs. With our massive community of hardware designers, and their high-quality components that are high in demand with our community, it was the perfect match.”

Competing against existing models
How will Samtec compete against other such existing models? She added: “It’s not so much that Samtec is competing to get their models into a design, but rather, their physical products. The digital model (or, what are in fact, manufacturing files), are really when they design-in comes to fruition.
1 - Samtec Symbol _ Footprint
“Samtec has high-quality and reliable products, and an incredible focus on service and support. I think, that’s why so many engineers trust their products. Ultimately, engineers will make the decision based on which specs are right for them, and the model is really the ‘icing on the cake’, after they’ve made that selection decision as a reward to help them design it in more easily.”

Samtec has over 100,000 new models on SnapEDA. The new models include USB, card edge, board-to-board, headers, and RF coaxial connectors, because the new models include USB, card edge, board-to-board, headers, and RF coaxial connectors. Since Samtec focuses on connectivity solutions, that’s where the focus was for this project. However, SnapEDA has millions of models for all kinds of products.
Snap1

Boosting electronics designers’ productivity
How can electronics designers boost their productivity with free symbols and footprints for Samtec products? Elizabeth Bustamante said: “Finding high-quality models for the exact part number, in the exact format and version you need is actually quite difficult. With these models, Samtec’s Signal Integrity Team is working directly with defining every element.

“Additionally, SnapEDA’s translation technology ensures that it is available in every format. The commitment to quality, and the breadth of our database and design formats supported is why we’re the #1 parts library on the web in terms of traffic.

“On top of this, creating connector models (which these are) are especially time-consuming, due to their non-standard shapes, pitches, pads, and cutouts regions. Having these models available to download, designers can spend more time in improving their design, allowing them to focus on optimization and innovation.”

Finally, how are newer, unreleased digital models going to be handled? She said: “We have a popular service, called InstaPart, which allows the engineers to request any models in 24 hours, and fulfilled by SnapEDA’s in-house component engineering team. Furthermore, the SnapEDA and Samtec teams are working closely to deploy new models to the SnapEDA platform as they become available.”

It is really great to have a lady address the queries on behalf of an organization. Many congratulations to the SnapEDA-Samtec combine.

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SiFive presents RISC-V product overview

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SiFive recently presented the RISC-V product overview. Krste Asanovic, co-founder and chief architect, said: “Have you ever heard of a $1 billion hardware company with 13 employees? Instagram turned into a $1 billion acquisition with only 13 employees.

“SiFive provides RISC-V core IP. SiFive RISC-V core IP product offering includes E Cores and U Cores. E Cores are the industry leading 32- and 64-bit embedded cores. U Cores are the high performance 64-bit application cores.”

The Core Series offer unique design points which can be customized for application-specific requirements. Standard Cores are pre-configured implementations of Core Series, free RTL and FPGA evaluations.

E2 Series RISC-V Core IP
E2SiFive E2 Series RISC-V Core IP is SiFive’s smallest, lowest power core series. It provides clean-sheet design from the inventors of RISC-V. It has a new interrupt controller enabling fast interrupt handling. It also has support for coherent heterogenous MP with other SiFive cores. The E20 and E21 are Standard Cores within the E2 series.

E2 Series is the smallest, most efficient RISC-V MCU family. It is:
– RV32IMAFC capable core
– 2-3 stage, optional, Harvard Pipeline

It is configurable to meet application specific needs. It is the first RISC-V core with support for for the RISC-V Core local interrupt controller (CLIC). Drop In Cortex-M0+ and Cortex-M3/M4 replacement.

E21 is 12 percent higher performance per MHz vs Cortex-M4 in CoreMark, when using equivalent GCC Compilers. E20 is 28 percent higher performance per MHz vs Cortex-M0+ in CoreMark,  when using equivalent GCC Compilers.

SiFiveE3 and E5 Series RISC-V Core IP are high performance 32-bit and 64-bit RISC-V MCUs. Features include pipelined multiapplication unit, multicore support, fast interrupts and memory protection.

U5 Series RISC-V Core IP
SiFive U5 Series RISC-V Core IP is 64-bit RISC-V Multicore Linux-capable. The U5-MC allows for instantiation of up to 9 U5 and/or E5 cores as well a configurable Level 2 cache. Flexible memory system allows for application-specific resource partitioning.

It has broad market applications – general-purpose embedded, industrial, IoT, high-performance real -time embedded, automotive.

The U54 -MC4 Standard Core is also 64-bit RISC-V multicore Linux capable.

“RISC -V delivers a platform for innovation, unshackled from the proprietary interface of the past. This freedom allows us to bring compute closer to data to optimize special-purpose compute capabilities targeted at Big Data and Fast Data applications,” according to Martin Fink, CTO, Western Digital.

Faster-to-market processes key for success in automotives: Fisker

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There has been a partnership between global automotive design icon, Henrik Fisker, and Berlin-based automotive and mobility tech investment group, motec Ventures.

FiskerMotec Ventures has made the commitment to source talent from all over the world, beginning in Europe and branching out, to cultivate new and innovative tech companies and usher in the next generation of the automotive industry. It is also important for all automotive and technology talent based outside of Silicon Valley.

I asked Fisker how he is focused on discovering new, agile mobility technology companies in Europe and abroad to disrupt the automotive sector. Also, his joining the Board of Motec Ventures is to facilitate increased collaboration between promising new suppliers, SMEs and OEMs in an effort to lower manufacturing costs and enable smarter scale-up.

Fisker said: “I’m already engaged with Motech Ventures, and have had several discussion where we review new start-ups. We study the start-up’s technology, and I particularly see if it’s applicable to any of the future programs at Fisker Inc., as well as the global automotive industry.

“If we see that the start-up can contribute to part of the supply chain with a breakthrough idea, Motech Ventures will invest into the start-up and we use our network to help the start-up grow. If the technology is applicable to any of Fisker Inc.’s future products, Fisker Inc. may participate in the investment round and engage with the start-up directly.

“The automotive industry is changing forever, where much shorter development cycles and faster-to-market processes are necessary to be successful. By working with new start-ups, extreme short development cycles are possible, as they are not bogged down by traditional long automotive processes, and they must be faster to succeed.

“Several new technologies can be developed and tested faster today, due to extensive use of new software. If an OEM can make fast decisions, the technology can be implemented much faster. The days of 3.5+ year development cycles are over, it’s too long for the product to stay relevant.”

How will Fisker help guide efforts to increase collaboration between the suppliers, SMEs and OEMs to lower manufacturing costs and enable smarter scaling?

He added: “Motech is partly formed by e&Co., an automotive consultancy that works with many SMEs and OEMs including Fisker Inc. e&Co has the ability to make the introductions and actively work with the new start-ups.”

Fisker will co-invest in motec portfolio companies in sectors, ranging from smart manufacturing, AI-based process optimization to concrete autonomous driving applications.

He said that Fisker Inc. has the ability to co invest if the technology is applicable to a Fisker project. Fisker Inc. would engage with the start-up directly and have them work as a Fisker supplier on a program.

How is the project aimed at tapping into the hotbed of engineering and tech talent in Germany, Europe and abroad?

Fisker said: “Motech is actively seeking out start-ups with innovative technologies that the board of motec ventures can see the need for in the automotive industry. We are all actively working on future automotive programs in various ways.

As for helping drive down manufacturing costs and to enable smarter scaling, he noted: “Motech is focusing on the collaboration part. Fisker Inc. will focus on driving down cost and smarter scaling on our own Fisker Inc. programs. For competitive reasons, we are not sharing any details of those efforts. We are constantly reviewing and engaging with new start-ups.”

Helix’s MxC 200 DC-DC power IC increases efficiency at data centers

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Fabless power semiconductor company, Helix Semiconductors, announced that Agility Power Systems (Agility) is using the MxC 200 IC for its innovative, 1kW, high-efficiency 48VDC to 12VDC power converter. Agility designs highly efficient switched capacitor power conversion devices targeted at the data center, solar and electric vehicle markets.

As data storage capacity grows exponentially, as does the need for highly-efficient data center hardware and infrastructure.

Jason Young, president and CEO, Agility Power Systems, said: “Earlier this year, Agility Power Systems used the MuxCapacitor technology to create a 1kW 48V to 12V power converter with 97.6 percent peak efficiency using discrete components. This proof of concept unit was first demonstrated at the Helix Semiconductors booth at APEC in early March.

“Agility is now launching a new smaller, more cost effective and more functional version of that converter by integrating Helix’s MxC200 ASIC into the design in a way that amplifies the benefits of the already industry leading efficiency and power density characteristics of the MxC200.”

How is the MxC 200 DC-DC power IC bringing increased efficiency at data centers?

Bud Courville, VP of Business Development, Helix Semiconductors, said: “Our patented MuxCapacitor technology has a higher peak efficiency and maintains that efficiency across a much greater portion of the load curve when compared to traditional magnetic based power conversion devices used in data centers.
Helix1“This feature creates higher operating efficiency and reduced heat generation across a wider range of applications than traditional power converters. Exact sizing of the power conversion device to the application’s specific load becomes less critical when near peak efficiency is maintained through a wider range.

By how much is the financial benefit by reduced cooling costs due to lower heat generation?

To this, he added: “It depends on the Power Utilization Effectiveness (PUE) of the data center and the cost per watt at each facility. Here is a brief definition and description of the PUE.

“Power usage effectiveness (PUE) is a metric used to determine the energy efficiency of a data center. PUE is determined by dividing the amount of power entering a data center by the power used to run the computer infrastructure within it. PUE is, therefore, expressed as a ratio, with overall efficiency improving as the quotient decreases toward 1.”

PUE was created by members of the Green Grid, an industry group focused on data center energy efficiency. Data center infrastructure efficiency (DCIE) is the reciprocal of PUE and is expressed as a percentage that improves as it approaches 100 percent.
Helix2
He said: “While PUE varies from data center to data center, recent studies indicate that the typical data center has an average PUE of around 1.7. This means that for every 1.7 watts in at the utility meter, only one watt is delivered out to the IT load.

“For every watt saved in operating efficiency at the point of load, 1.7 watts worth of energy costs are saved. In a 1kW power conversion device that would mean that an efficiency improvement of 5 percent would equate to a point of load savings of 50 watts and a total energy savings of 85 watts. The cost savings of this reduction in overall energy usage adds up quickly at data centers consuming large amounts of power 24 hours a day.”

How has the bidirectional nature of Helix MuxCapacitor enabled new design configuration?

Courville said: “MuxCapacitor technology can be configured to operate as either a voltage step down or step up device within the same circuit. This makes it ideal for solar, EV and “Prosumer” renewable energy applications where power can be both drawn from or added to the grid or battery storage.”

Finally, what are the other MxC 200’s game-changing features and benefits in large power applications?

Courville said: “There are many features and benefits of the MxC 200 that improve performance in large power usage applications. The most pronounced benefit by far is the significant cost savings that results from improved efficiency both at peak load conditions and across the broader load curve.

“This cost savings comes both from a reduction in power consumed to operate the load and power consumed to temperature control the environment. For a smaller data center facility with a PUE of 2.0, the cost savings is double that of the savings from the reduction in energy consumed to drive the load.

“The power density of the MxC 200 is another key feature. In addition to reducing heat and cost through higher efficiency, the MxC 200 can also reduce the weight and size required for a power conversion device.

“The MxC 200 also has multiple output voltage settings. For Agility’s 48V input device, this feature would allow for output voltages of 24V or 6V in addition to the primary 12V output. The bidirectional nature of MuxCapacitor technology makes it ideal for certain applications.”

Self-driving cars pushing boundaries of IC testing: Nilanjan Mukherjee, Mentor

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Nilanjan Mukherjee, Engineering director, Tessent, Mentor A Siemens Business, presented the opening keynote on day 2 of the ITC 2018, on self-driving cars and how they are pushing the boundaries of IC testing.

IMG_20180724_112645Automotive ICs will grow from 7.4 percent in 2017 to 9.3 percent by 2021. New entrants are attracted by new revenue opportunities. Leading auto makers are planning to launch self-driving cars, such as Tesla, GM, Hyundai, Renault-Nissan, Toyota, Volvo, etc., as per the Boston Consulting Group. According to McKinsey & Co., 57 percent of customers globally, trust self-driving cars.

Increasing detection capabilities require higher compute performance. Higher compute requirements are accelerating the process node requirements. For the next decade, the number of gates will double every 2 years. There will be 2x more compression every 2 years, just to maintain the test cost. There is a huge increase in transistor processing, and trends will continue with the future 5nm/3nm nodes. Further scaling will require density increase, in addition to the pitch scaling.

Test requirements ensure that semiconductor devices remain defect free. They should also ensure that any new defects are quickly detected throughout the device’s operational lifecycle. Low defective parts per billion – the implications of defective parts in automotive apps, are more severe than in consumer apps. The defect coverage should cover all circuitry.

More defects and lower DPPB require better coverage. There are complete defect excitation considerations. The defects are prioritized by their physical likelihood.

Automotive grade ATPG provides a complete set of critical area-based fault models for manufacturing tests. Cell-aware test benefits are well documented. Additional user–defined fault models (UDFM) are targeting inter-cell defects and interconnect bridges and open defects. We have to find ways to reduce the test time for analog parts.

Typically low coverage is 70-90 percent for analog parts. Fault simulation allows one to determine portions not being tested. There is a need to eliminate the manual FMEDA metric estimates that are required for ISO-26262. The fault simulator can report the metrics automatically, eliminating untolerated faults, and achieving higher ASIL rating.

There are multiple modes of in-system testing. Key-on tests have very little time budget. Limited functions are tested. Key-off tests see comprehensive testing. The budget is 10x times that of key-on tests. Finally, online tests are challenging. They are periodic and incremental.

Mission-mode controller is the in-system test controller. It automates communication between the test instruments and the service processor.

The new VersaPoint test point technology gives 2-4 percent SAF coverage vs. LBIST (logic built-in self test) test points. That’s 2X-3X reduction in test time at 90 percent coverage. It also reduces deterministic ATPG pattern counts by 2-4X.

VersaPoint test points with observation during shift helps in fast in-system logic monitoring. This helps on an average to reduce the test times by 3-4X.

Requirements for future in-system test solutions:
* Able to apply any type of test.
* Able to add, modify and update the in-system tests during the entire lifecycle of an IC.
* Minimal system memory and incremental data.

Programmable deterministic BIST for FuSa (functional safety) include two levels of highly compressed patterns. This reduces the memory required to store the patterns on the chip.

In the non-destructive memory BIST, there are traditional memory BIST constraints. Memory is tested in small bursts of activity by making sure that the original contents of the memory is restored after test.

Austemper acquisition by Siemens brings solutions across all areas. It is a completely functional safety solution. There is safety analysis, so you can design an automotive for safety. It also has safety verification, and multi-domain fault injection, providing evidence to achieve ASIL compliance.

Automotive ICs have redefined the standard for quality of manufacturing.

To be, or not to be fault tolerant! Or fault intolerant?

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IMG_20180723_183441Semiconductors is a tough business, and definitely not for the faint hearted, said Suman Narayan, senior VP, for Semiconductors, IoT and Analytics, Cyient. If you are in DFT, you are in the insurance business. He was moderating a panel discussion on ‘fault tolerance vs. fault intolerance’.

Rubin Parekhji, senior technologist, Texas Instruments, said that a system is fault tolerant if there is no error. An app is fault tolerant if there is no intolerant fault. An affordable system should be fault tolerant. Which faults are important? How are hardware-software fault tolerant? For instance, if not done well, it will lead to bulky devices. There is a need to optimize and differentiate. There is a need to build fault tolerant systems using fault intolerant building blocks.

Jais Abraham, director of engineering, Qualcomm, said that device complexity has increased 6X times since 2010. There is a disproportionate increase in test cost vs. node shrink benefits. Are we good at fault finding? It’s our fault. Be intolerant to faults, but don’t be maniacal. Think of the entire gamut of testing. Think of the system, and not just the chip. Think of the manufacturing quality, and find remedies. Fault tolerance may mean testing enough such that it meets the quality requirements of customers, who are becoming intolerant. We continue to invest in fault tolerance architectures.

Ruchir Dixit, Technical director, Mentor,  felt that making a system robust is the choice. The key is the machine that we make, and whether it is robust. The customers expect a quality robust system. Simpler systems make up a complex system. Successful system deals with malfunctions. There are regenerative components. The ISO-26262 standard drives robustness.

Dr Sandeep Pendharkar, Engineering director, Intel, felt that there is an increased usage of semiconductors in apps such as ADAS and medical. Functional safety (FuSa) requires unprecedented quality levels. Now, DPPM has changed to DPPB.

Achieving near zero DPPB on the nearest node is nearly impossible. Fault tolerance is the way forward. How should the test flows change to comprehend all this? Should we cap the number of recoverable faults before declaring a chip unusable?

Ram Jonnavithula, VP of Engineering, Tessolve, said that a pacemaker should be fault tolerant, with zero defects. Fault tolerance requires redundancy, mechanism to detect and isolate faults. Sometimes, fault tolerance could mean reduced performance, but the system still functions.

Adit D. Singh, Prof. Electrical & Computer Engineering, Auburn University, USA, highlighted the threats to electronics reliability. These are:
* Test escapes – DPPM. Especially, escape from testing components. Also, timing defects.
* New failures occur during operation. They can also be due to aging.
* Poor system design, which are actually, no solution. There can be design errors and improper shields.

Test diversity helps costs. Design diversity helps fault tolerance costs. Design triplicated modules independently. Avoid correlated failures.

So, what’s it going to be? Be fault tolerant! Or, fault intolerant?

Need for end-user driven test strategy: Raja Manickam, Tessolve

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At the ongoing ITC 2018 conference, Raja Manickam, founder and CEO, Tessolve, spoke on ‘Always on ERA’?

RajaEvery chip is tested. About 10 million++ chips are tested every day. A chip carries millions of data and also does continuous self test. It is expected that the chip is always on. Engineers look at all possible combinations. They try and solve problems quickly.

Design is supposed to be pure genius. However, testing is the necessary evil. There is DFT to probe FT and SLT. We just keep on adding tests.

The players who help drive us are the academia, EDA companies, fabs, and ATEs (they add more instruments, and make it bigger). What matters is that the chip must work in a particular manner, all the time.

Test leadership creates an environment for test strategy and drives it. There must be given flexibility and innovation for test leadership. Focus on the end-user relevancy.

Next-gen BIST provides M-BIST and scan compression engines on separate DFx die. The ATE interface can exist in the DFx die. Base functional die will provide power and clocks.

At any time a machine is running, less than 20 percent of the instruments are used. That’s not the best use of assets.

Factors influencing traditional ATE include loop back testing, ATE need to test deserialized parallel data, miniature MEMS loop back device to improve SI and MEMS RF relay, and the use of FPGAs.

There are adaptive tests and predictive algorithms. The ATE could look like instrumentation and intelligence built in to the load board or hardware. There could be three dimensional handlers. The handler will go vertical. There should be an end-user driven test strategy. The test strategy should be holistic.