Fabless power semiconductor company, Helix Semiconductors, announced that Agility Power Systems (Agility) is using the MxC 200 IC for its innovative, 1kW, high-efficiency 48VDC to 12VDC power converter. Agility designs highly efficient switched capacitor power conversion devices targeted at the data center, solar and electric vehicle markets.
As data storage capacity grows exponentially, as does the need for highly-efficient data center hardware and infrastructure.
Jason Young, president and CEO, Agility Power Systems, said: “Earlier this year, Agility Power Systems used the MuxCapacitor technology to create a 1kW 48V to 12V power converter with 97.6 percent peak efficiency using discrete components. This proof of concept unit was first demonstrated at the Helix Semiconductors booth at APEC in early March.
“Agility is now launching a new smaller, more cost effective and more functional version of that converter by integrating Helix’s MxC200 ASIC into the design in a way that amplifies the benefits of the already industry leading efficiency and power density characteristics of the MxC200.”
How is the MxC 200 DC-DC power IC bringing increased efficiency at data centers?
Bud Courville, VP of Business Development, Helix Semiconductors, said: “Our patented MuxCapacitor technology has a higher peak efficiency and maintains that efficiency across a much greater portion of the load curve when compared to traditional magnetic based power conversion devices used in data centers.
“This feature creates higher operating efficiency and reduced heat generation across a wider range of applications than traditional power converters. Exact sizing of the power conversion device to the application’s specific load becomes less critical when near peak efficiency is maintained through a wider range.
By how much is the financial benefit by reduced cooling costs due to lower heat generation?
To this, he added: “It depends on the Power Utilization Effectiveness (PUE) of the data center and the cost per watt at each facility. Here is a brief definition and description of the PUE.
“Power usage effectiveness (PUE) is a metric used to determine the energy efficiency of a data center. PUE is determined by dividing the amount of power entering a data center by the power used to run the computer infrastructure within it. PUE is, therefore, expressed as a ratio, with overall efficiency improving as the quotient decreases toward 1.”
PUE was created by members of the Green Grid, an industry group focused on data center energy efficiency. Data center infrastructure efficiency (DCIE) is the reciprocal of PUE and is expressed as a percentage that improves as it approaches 100 percent.
He said: “While PUE varies from data center to data center, recent studies indicate that the typical data center has an average PUE of around 1.7. This means that for every 1.7 watts in at the utility meter, only one watt is delivered out to the IT load.
“For every watt saved in operating efficiency at the point of load, 1.7 watts worth of energy costs are saved. In a 1kW power conversion device that would mean that an efficiency improvement of 5 percent would equate to a point of load savings of 50 watts and a total energy savings of 85 watts. The cost savings of this reduction in overall energy usage adds up quickly at data centers consuming large amounts of power 24 hours a day.”
How has the bidirectional nature of Helix MuxCapacitor enabled new design configuration?
Courville said: “MuxCapacitor technology can be configured to operate as either a voltage step down or step up device within the same circuit. This makes it ideal for solar, EV and “Prosumer” renewable energy applications where power can be both drawn from or added to the grid or battery storage.”
Finally, what are the other MxC 200’s game-changing features and benefits in large power applications?
Courville said: “There are many features and benefits of the MxC 200 that improve performance in large power usage applications. The most pronounced benefit by far is the significant cost savings that results from improved efficiency both at peak load conditions and across the broader load curve.
“This cost savings comes both from a reduction in power consumed to operate the load and power consumed to temperature control the environment. For a smaller data center facility with a PUE of 2.0, the cost savings is double that of the savings from the reduction in energy consumed to drive the load.
“The power density of the MxC 200 is another key feature. In addition to reducing heat and cost through higher efficiency, the MxC 200 can also reduce the weight and size required for a power conversion device.
“The MxC 200 also has multiple output voltage settings. For Agility’s 48V input device, this feature would allow for output voltages of 24V or 6V in addition to the primary 12V output. The bidirectional nature of MuxCapacitor technology makes it ideal for certain applications.”
Nilanjan Mukherjee, Engineering director, Tessent, Mentor A Siemens Business, presented the opening keynote on day 2 of the ITC 2018, on self-driving cars and how they are pushing the boundaries of IC testing.
Automotive ICs will grow from 7.4 percent in 2017 to 9.3 percent by 2021. New entrants are attracted by new revenue opportunities. Leading auto makers are planning to launch self-driving cars, such as Tesla, GM, Hyundai, Renault-Nissan, Toyota, Volvo, etc., as per the Boston Consulting Group. According to McKinsey & Co., 57 percent of customers globally, trust self-driving cars.
Increasing detection capabilities require higher compute performance. Higher compute requirements are accelerating the process node requirements. For the next decade, the number of gates will double every 2 years. There will be 2x more compression every 2 years, just to maintain the test cost. There is a huge increase in transistor processing, and trends will continue with the future 5nm/3nm nodes. Further scaling will require density increase, in addition to the pitch scaling.
Test requirements ensure that semiconductor devices remain defect free. They should also ensure that any new defects are quickly detected throughout the device’s operational lifecycle. Low defective parts per billion – the implications of defective parts in automotive apps, are more severe than in consumer apps. The defect coverage should cover all circuitry.
More defects and lower DPPB require better coverage. There are complete defect excitation considerations. The defects are prioritized by their physical likelihood.
Automotive grade ATPG provides a complete set of critical area-based fault models for manufacturing tests. Cell-aware test benefits are well documented. Additional user–defined fault models (UDFM) are targeting inter-cell defects and interconnect bridges and open defects. We have to find ways to reduce the test time for analog parts.
Typically low coverage is 70-90 percent for analog parts. Fault simulation allows one to determine portions not being tested. There is a need to eliminate the manual FMEDA metric estimates that are required for ISO-26262. The fault simulator can report the metrics automatically, eliminating untolerated faults, and achieving higher ASIL rating.
There are multiple modes of in-system testing. Key-on tests have very little time budget. Limited functions are tested. Key-off tests see comprehensive testing. The budget is 10x times that of key-on tests. Finally, online tests are challenging. They are periodic and incremental.
Mission-mode controller is the in-system test controller. It automates communication between the test instruments and the service processor.
The new VersaPoint test point technology gives 2-4 percent SAF coverage vs. LBIST (logic built-in self test) test points. That’s 2X-3X reduction in test time at 90 percent coverage. It also reduces deterministic ATPG pattern counts by 2-4X.
VersaPoint test points with observation during shift helps in fast in-system logic monitoring. This helps on an average to reduce the test times by 3-4X.
Requirements for future in-system test solutions:
* Able to apply any type of test.
* Able to add, modify and update the in-system tests during the entire lifecycle of an IC.
* Minimal system memory and incremental data.
Programmable deterministic BIST for FuSa (functional safety) include two levels of highly compressed patterns. This reduces the memory required to store the patterns on the chip.
In the non-destructive memory BIST, there are traditional memory BIST constraints. Memory is tested in small bursts of activity by making sure that the original contents of the memory is restored after test.
Austemper acquisition by Siemens brings solutions across all areas. It is a completely functional safety solution. There is safety analysis, so you can design an automotive for safety. It also has safety verification, and multi-domain fault injection, providing evidence to achieve ASIL compliance.
Automotive ICs have redefined the standard for quality of manufacturing.
Semiconductors is a tough business, and definitely not for the faint hearted, said Suman Narayan, senior VP, for Semiconductors, IoT and Analytics, Cyient. If you are in DFT, you are in the insurance business. He was moderating a panel discussion on ‘fault tolerance vs. fault intolerance’.
Rubin Parekhji, senior technologist, Texas Instruments, said that a system is fault tolerant if there is no error. An app is fault tolerant if there is no intolerant fault. An affordable system should be fault tolerant. Which faults are important? How are hardware-software fault tolerant? For instance, if not done well, it will lead to bulky devices. There is a need to optimize and differentiate. There is a need to build fault tolerant systems using fault intolerant building blocks.
Jais Abraham, director of engineering, Qualcomm, said that device complexity has increased 6X times since 2010. There is a disproportionate increase in test cost vs. node shrink benefits. Are we good at fault finding? It’s our fault. Be intolerant to faults, but don’t be maniacal. Think of the entire gamut of testing. Think of the system, and not just the chip. Think of the manufacturing quality, and find remedies. Fault tolerance may mean testing enough such that it meets the quality requirements of customers, who are becoming intolerant. We continue to invest in fault tolerance architectures.
Ruchir Dixit, Technical director, Mentor, felt that making a system robust is the choice. The key is the machine that we make, and whether it is robust. The customers expect a quality robust system. Simpler systems make up a complex system. Successful system deals with malfunctions. There are regenerative components. The ISO-26262 standard drives robustness.
Dr Sandeep Pendharkar, Engineering director, Intel, felt that there is an increased usage of semiconductors in apps such as ADAS and medical. Functional safety (FuSa) requires unprecedented quality levels. Now, DPPM has changed to DPPB.
Achieving near zero DPPB on the nearest node is nearly impossible. Fault tolerance is the way forward. How should the test flows change to comprehend all this? Should we cap the number of recoverable faults before declaring a chip unusable?
Ram Jonnavithula, VP of Engineering, Tessolve, said that a pacemaker should be fault tolerant, with zero defects. Fault tolerance requires redundancy, mechanism to detect and isolate faults. Sometimes, fault tolerance could mean reduced performance, but the system still functions.
Adit D. Singh, Prof. Electrical & Computer Engineering, Auburn University, USA, highlighted the threats to electronics reliability. These are:
* Test escapes – DPPM. Especially, escape from testing components. Also, timing defects.
* New failures occur during operation. They can also be due to aging.
* Poor system design, which are actually, no solution. There can be design errors and improper shields.
Test diversity helps costs. Design diversity helps fault tolerance costs. Design triplicated modules independently. Avoid correlated failures.
So, what’s it going to be? Be fault tolerant! Or, fault intolerant?
At the ongoing ITC 2018 conference, Raja Manickam, founder and CEO, Tessolve, spoke on ‘Always on ERA’?
Every chip is tested. About 10 million++ chips are tested every day. A chip carries millions of data and also does continuous self test. It is expected that the chip is always on. Engineers look at all possible combinations. They try and solve problems quickly.
Design is supposed to be pure genius. However, testing is the necessary evil. There is DFT to probe FT and SLT. We just keep on adding tests.
The players who help drive us are the academia, EDA companies, fabs, and ATEs (they add more instruments, and make it bigger). What matters is that the chip must work in a particular manner, all the time.
Test leadership creates an environment for test strategy and drives it. There must be given flexibility and innovation for test leadership. Focus on the end-user relevancy.
Next-gen BIST provides M-BIST and scan compression engines on separate DFx die. The ATE interface can exist in the DFx die. Base functional die will provide power and clocks.
At any time a machine is running, less than 20 percent of the instruments are used. That’s not the best use of assets.
Factors influencing traditional ATE include loop back testing, ATE need to test deserialized parallel data, miniature MEMS loop back device to improve SI and MEMS RF relay, and the use of FPGAs.
There are adaptive tests and predictive algorithms. The ATE could look like instrumentation and intelligence built in to the load board or hardware. There could be three dimensional handlers. The handler will go vertical. There should be an end-user driven test strategy. The test strategy should be holistic.
According to an IC Insights report, the 47 percent full-year 2017 jump in the price-per-bit of DRAM was the largest annual increase since 1978, surpassing the previous high of 45 percent registered 30 years ago in 1988! This sounds interesting!
Are the rising DRAM prices aiding startup Chinese competitors? Are major DRAM suppliers somehow stunting global DRAM demand?
Dr. Walden C. Rhines, president and CEO, Mentor Graphics, a Siemens Business, said: “The DRAM business has always gone through cycles of imbalance between supply and demand. Growth of demand in the last 18 months has been stronger than growth of supply.
“Substantial investments in 2017 by the MOS (metal-oxide semiconductor) memory producers, as well as the addition of China to the supply chain, will correct this imbalance late this year or, at the latest, early next year.”
The DRAM price-per-Gb has been on a steep rise. To this, Dr. Rhines said: “It is a commodity, although there are many types of specialty DRAMs emerging. Because DRAMs are viewed by customers as a near-commodity, the price is heavily influenced by the availability of supply. Supply has been very tight during the last 18 months.
Malcolm Penn, chairman and CEO, Future Horizons, UK, added, “This is supply and demand, pure text-book economics.”
Are the rising DRAM prices opening the door for startup Chinese competitors?
Dr. Rhines noted: “Chinese competitors made their decision to invest in DRAM capacity long before the recent strengthening of demand in the balance of supply and demand. Of course, higher, or stable, pricing may make it easier for new producers to absorb the costs of ramping up new capacity and developing experience with a new technology.”
Malcolm Penn agreed: “Potentially yes, and to anyone else. Coca Cola were contemplating building DRAMs in the 1990s. DSRAM market boom, again, pure text-book economics. Whether or not they succeed is an entirely different matter. If the Chinese do enter the market, can they then survive the inevitable downturn and cycles? That remains to be seen!”
Can the startup Chinese DRAM producers field any competitive product soon? Dr. Rhines noted: “They probably can. But, they will have to develop a production base of “learning” to reduce cost, improve yields and maybe even reliability. This will take some time.”
Penn added: “Technically (i.e., meeting the spec), probably, yes. Reliability, probably no, for the Tier 1 customers (that will take several years to build up the production experience). Cost, definitely not!
“Their small fab scale and late learning curve start means that their die cost will be sizably higher than those of Samsung and SKH, and also Micron. Plus, their yields will be lower. Then, there’s the deep cash pockets issue to fund these ongoing cost disadvantages.”
In a separate situation, some 300mm fabs closing, for example, ProMOS. Dr. Rhines said: “It’s because of an imbalance of supply and demand for the products they make, thus limiting their profitability. It could also be because they don’t see an adequate investment return from the expensive new capacity investments, and therefore, find it more attractive to phase out some of their existing capacity.”
Malcolm Penn felt that the fabs were too old and technically obsolete.
Finally, are there more IC companies making transition to fab-lite or fabless business model?
Penn noted: “There’s no-one left to change! Everyone’s now fablite or fabless, except for Intel and Samsung (logic) and the memory manufacturers.”
Dr. Rhines said: “Based upon the growth of foundry revenue vs. total semiconductor revenue growth, there must be a continuing transition of capacity away from IDMs toward foundries. In addition, IDMs like Samsung are finding it economic to build the foundry business to increase the volume base of products that utilize their technology and capital investment.”
This is a bold title, right? The Union Government of India is on its way to achieving the 175 GW target for installed renewable energy capacity by 2022. By November 2017, a total of 62 GW renewable power had been installed, of which 27 GW were installed since May 2014, and 11.79 GW since January 2017.
India is said to have achieved historic low tariffs for solar (Rs. 2.44/ unit) and wind (Rs. 2.64/ unit) through transparent bidding and facilitation. India also attained global 4th and 6th position in global Wind and Solar Power installed capacity.
Now, India has laid down an ambitious bidding trajectory for 100 GW capacity of solar energy and 60 GW capacity of wind over the next three years. Read more
Kochi-based V-Guard Industries Ltd in Kerala state, is India’s leading consumer electrical and electronics major. It has evolved into a renowned consumer brand with market-leading products in select segments.
Mithun K. Chittilappilly, Managing Director of V-Guard Industries foresaw the need for market expansion beyond South of India, and consistently increased the footprint in other parts of the country. In 2012, the company established presence in Guwahati, and introduced new products, like solar inverters, switch gears and mixer grinders. His vision is to elevate V-Guard to the next level through long-term growth plans.
Chittilappilly said: “I joined the business in 2006. We have since grown. We had almost 50 percent revenue coming from voltage stabilisers. The revenue for voltage stabilizers has come down from 50 percent to 18 percent. Now, we are present pan India. We are also looking to diversify.
“We have entered inverters and batteries, kitchen appliances, and switchgears. We have since become strong players in these segments, especially, water heaters. Today, the new categories are contributing 10-15 percent to the overall revenue. The wires and cables business is doing Rs 60 crore EBIDTA year-on-year. There was also a good boom in the construction industry from 2006-12. For water heaters, we have been doing business worth Rs. 8 crores.”
How did this come about? He added: “We changed the structure to several categories of business. Today, we have 2,000+ people on roll. We are fairly comfortable. We have two to three channels, such as electrical, battery, etc.
“We have DSIR-approved labs in Kochi. In Gurgaon, we have development teams for switchgear. We also have a separate team on industrial designs. We also have a team working on smart products, such as IoT.”
Elaborating, he added: “We are working on products that communicate with consumers. We have products that are connected, controlled and M2M capable. We are bringing capabilities like machine learning as well. We are also in the battery segment. The battery will be an expensive part of an electric car in the future.
“We are also building in auto diagnostics into devices. For instance, the next-gen water heater can communicate to the other water heater as well. In rural areas, farmers need to know when a pump should be switched on/off. We have automated that. We also need to ensure that the products are protected from natural disasters.”
Isn’t there competition from the MNCs? He noted that MNCs don’t bother much about Indian-based products. “Our retail is distributed. We have a great talent pool in India and we develop products. We are in the consumer electrical business and continue to do that well.”
“We have looked at automation, and find that robots prices are declining. We have distribution boards, where intelligent management is built in. We are looking at smart products that can make some difference to consumers. We are thinking of getting into modular switches, and smart home solutions. In kitchen appliances, if you have a mixer grinder, it can control speed.
“We are also working on a digital strategy for the company that includes looking at the predictive maintenance in plants, where AI comes in. AI may help reduce headcounts. We have to wait and see what happens.”