Chips Act
Gina Raimondo updates on US CHIPS Act implementation; Investing in leading-edge technology
Gina M. Raimondo, Secretary of Commerce, USA, gave a speech today at the Center for Strategic and International Studies (CSIS), Washington, DC, on the critical progress CHIPS for America has made over the last year.
Earlier this month, leaders from Departments of Commerce, Defense, and Energy; and the National Science Foundation, and CEO of the National Center for the Advancement of Semiconductor Technology (NATCAST) gathered at the White House to announce over $5 billion in expected investment in the CHIPS R&D program. This includes the National Semiconductor Technology Center (NSTC), and formally establish a public-private consortium for the NSTC.
The announcement included hundreds of millions of dollars of expected investment in the semiconductor workforce, along with the specific funding announcements in packaging, metrology, and a CHIPS Manufacturing USA Institute. This announcement is a reflection of President Joe Biden’s commitment to American innovation and R&D.
Gina Raimondo recalled the space war from the 1960s. CHIPS initiative mirrors the space race that the US had with the Soviet Union decades ago. At that time, President Kennedy issued a call to America to put a man on the moon. Six decades later, President Joe Biden has called for producing semiconductors in the USA, against geopolitics. We can once again cement our leadership role the in global semiconductor industry race.
Raimondo stated that there’s been a game-changer in the demand for leading-edge semiconductor chips. You all know what it is: AI. When we started this initiative in Aug. 2022, generative AI wasn’t even really part of our vocabulary. Now it’s everywhere! Today, AI will become the defining technology of our generation. You can’t lead in AI if you don’t lead in making leading-edge chips. Our work in implementing the CHIPS Act just got a whole lot more important.
US currently leads in design of chips, AI LLMs, etc. But, we don’t manufacture or package any leading-edge chips needed to fuel AI and our whole innovation ecosystem, including chips necessary for national defense. In reality, we were not manufacturing chips in America! We now need to change this, make leading edge and mature chips in America. We need to have lot more semiconductors in America.
The brutal fact is the United States cannot lead the world as a technology and innovation leader on such a shaky foundation. We need to make these chips in America. We need more talent development in America. We need more R&D in America, and just a lot more manufacturing at scale. China is taking an increasing role in their chip production. We have to now nail this! Every detail matters! China is taking an increasingly ambitious role in increasing their own chip production.
We have to nail the implementation of the CHIPS and Science Act. We have to execute like every detail matters because it does and we have to be bold enough with our vision, which is why I liken it to the space race.
We will be judged on two things. First, whether we were able to build a reliable and resilient semiconductor industry that advances our country’s technological leadership. Second, whether we were good stewards of taxpayer dollars. A year into it, I’m proud to say that we are on track to accomplish both. In record time, this team at the Commerce Department has stood up a program, a team, which is flexible, fast, and world class. Over 200 people work in the CHIPS office today. They have a track record of delivering on big projects.
Since President Biden signed the CHIPS Act, and before we put a single dollar out into any private companies, the private sector in USA announced $200 billion in semiconductor manufacturing investments. That’s incredible, and I want to thank the industry.
Nine states have now created new economic development programs. Over 50 community colleges across 19 states have announced programs to partner with the semiconductor industry and opportunities. We are working with the labor unions, academia, research agencies, NSTC, etc., on training workforce for future. NSTC will tackle the R&D challenges facing America’s chips manufacturing ecosystem and upskill, so that we have a skilled workforce.
Focus on targeted investments
We also have some bad news! We have, so far, received over 600 statements of interest, and many of them by strong companies. A significant majority of companies expressing interest aren’t going to receive funding,, including many excellent proposals by strong and worthy companies. Our job is to make targeted investments in relentless pursuit of achieving our national security objectives. We cannot have projects starting in 2030. We need them now.
At the outset, we said that we would invest about $28 billion of the program’s $39 billion in incentives for leading-edge chip manufacturing. The leading-edge companies alone have requested more than $70 billion. We are obsessed with the protection of taxpayers money. We are also going to create thousands of jobs. Companies are also having to go with the national guardrails for these various projects.
We have also made a few decisions. We have decided to prioritize projects that will be operational by 2030. There are many worthy proposals that we have received with plans to come online after 2030. We are saying no, for now, to those projects because we want to maximize our impact in this decade. It’s not responsible to give money to a project that will come online 10 or 12 years from now, if it means saying no to excellent projects that could come online this year.
CEOs generally come in, and ask for billions of dollars. Later, they get half of what they had asked. We have finite amount of money to manage the economy. We have some goals for 2030. Some projects are going to come online in 2030 and beyond. We are not giving the funding for such projects currently. There is risk involved. But, there is way more risk by doing nothing! We cannot be reliant of one part of the world for the most important piece of hardware, and that’s way more riskier in doing nothing!
Two new clusters
Raimondo noted the CHIPS Act goal is to have at least two new large-scale clusters of leading-edge logic fabs, with each of those clusters employing thousands of workers. We expect to exceed that target. We think our investments in leading-edge logic chips will put USA on track to produce roughly 20 percent of the world’s leading-edge logic chips by the end of the decade.
By the end of the decade we are going to go from 0 to 20 percent of leading-edge chips built in the USA. Supply chains will also come along. They can no longer be as vulnerable to geopolitical challenges as they are today. We will also be successful in having leading-edge memory, a critical input for AI systems, right here in the USA.
United States can become the home to the entire silicon supply chain for production of leading-edge chips – from polysilicon production, to wafer manufacturing, fabrication, and advanced packaging. That’s the game, by the way! Let’s be bold! This is not to build a few new fabs, and call it a day. Polysilicon to advanced packaging, and everything in between, including R&D, will happen in the United States.
We are not losing sight of the importance of current generation and mature node chips, which are essential for cars, medical devices, defense systems, and critical infrastructure. Just think back to to the pandemic. We were furloughing tens of thousands of workers from car companies for lack of a single legacy chip. We have got to improve the fragility of that supply chain. We made three announcements of investments in current and mature chip companies – BAE, Microchip, and Global Foundries. We are going to continue to announce additional investments in current and mature production to make sure we have a domestic supply of these critical chips. We are also going to make continuous announcements for materials.
By 2030, the USA will be the only country in the world where new chip architectures can be invented in our new research labs, including those funded by NSTC. They will also be designed in the USA for every end-use application you can think of. Manufactured at scale in the USA by well-paid American workers. And, packaged with the most advanced technology in the world. All on our shores.
Engineering schools all over the country will be pumping out more engineers and technicians trained specifically for the chips industry. We are going to make building hardware sexy again. Today, CEOs are excited. Labor unions are excited. Community college(s) are excited. High schools are excited. They want to know, what can we do to be part of our efforts to revitalize America’s chip ecosystem.
Following the CHIPS Act and other announcements, now, companies are saying: in what state should we expand? With which college should we partner? Where should NSTC be located, and with whom should they partner? We are going as fast as we can. We are more intent on getting this right, and build an industrial base, and beyond. I am excited for what’s going to come.
Implementing CHIPS Act
Earlier, Sujai Shivakumar, Director and Senior Fellow, Renewing American Innovation Project, welcomed the audience. He said that innovation is the engine that powers our nation’s economic growth, competitiveness, and national security. Semiconductors are the platform on which our economy runs, and, on which, so much of our innovation is built. That’s why implementing CHIPS and Science Act is so important.
In various ways, CHIPS pushing the renewable, or how can we manufacture in the United States, greener workforce, connect Americans to the innovation economy, reinvest in our R&D infrastructure, build new public-private partnerships, and cooperate with allies and strategic partners. Importantly, rewire and grow resilient supply chains. All this is to secure the future of US leadership in the 21st century. Semiconductors run everything, We have the CHIPS Act to forward the industry and secure the US leadership in the 21st century.
Fireside chat
Charles Wessner, Senior Adviser (Non-Resident), Renewing American Innovation Project, was engaged in a fireside chat with the Secretary. He asked whether the funding is sufficient to meet the goals. Riamondo stated companies are coming forward, and setting up the ecosystem. This is achievable with the money that we have.
Next, TSMC has spent about $30 billion in expansion. National Fund in China spent about $41 billion. Where does USA stand? Raimondo said China is not exactly shy about their ambitions. They have also poured $100 billion in domestic chip production. Leading-edge chip producers in the USA are majorly American, such as AMD, Intel, Nvidia, Microsoft, etc. What TSMC is doing in Arizona is path breaking. They are investing in United States. We are grateful for that, and are going to make sure it’s successful.
Legislation requires that we also invest $2 billion in foundational chips. GlobalFoundries is doing foundational chips and that alone was $1.5 billion. We are going to exceed the $2 billion mark. We can easily invest a bit more in the excellent companies. We can now do leading-edge chips, leading-edge memory, and and current mature, and still have some for the supply chain.. We are also keeping the tax credits. Tax credits will be shown to have been an unbelievably powerful part of the incentive to stretch the capital. That is why we’re able to do so much with relatively limited grant money.
We also envision the NSTC and NATCAST to be some part of R&D, and also launching workforce centers of excellence as the national hub for semiconductor training and excellence. We are also developing the semiconductor curriculum. We hope this can go ahead and unify the industry. Companies also want to make sure that the talent supply is available here in USA. That will be an important work for the NSTC.
We are now meeting the moment with leading-edge semiconductors, and meet the needs of AI and other technologies. We need to succeed! Failure is not an option here!! Imagine, if we are dependent on a couple of countries in Asia for such chips!!! We now need to lead the world in this kind of advanced technology. America is a world leader, and we intend to remain that way. We also need to keep up with the talent.
The President’s called many times for responsible immigration. We need to keep that talent. I would be strongly supportive of something that maintains highly skilled immigrants for this industry. It doesn’t have to be so narrow. I wish it were broader than just the chips industry. But, it’s a huge thing that does keep me up at night.
Wessner added that the space race is a good metaphor. Every decision is difficult and it helps us to have a dialog, noted Raimondo. We have spoken with several Governers, and other Senators. They have been strongly supportive of the CHIPS Act. They also want more jobs in their states, We have limited money right now, and there will be tough choices initially.
Wessner stated that NSTC seems to have enough potential. How do you see its longevity? Raimondo said NSTC has to be built for the decades to come. We have announced the Board and Woman to run that. We will also have workforce centers of excellence. We have to maximize on this.
Lastly, what will happen to the smaller companies? Is anything being done for them? Raimondo said we are determined to give small grants to small companies. There are many innovative companies in the semiconductor supply chain. They are not building big fabs. They might have materials that are innovative or somehow, provide inputs to fabs. We have a whole initiative internally to look at small companies to give them small grants. The majority will be told no, but many small companies are going to get funded.
NSTC will set up infrastructure, whether labs or testing facilities or prototyping facilities, digital twin facilities for little companies to use, and to have access to equipment and talent that they otherwise couldn’t afford. She does not know what the next wave of innovation is as these chips get smaller. Small companies should have access to labs and facilities so they can develop new technology, even though they’re capital constrained.
CHIPS Act and its impact on design and verification markets
Design and Verification Conference, DVCon USA 2023, started yesterday at DoubleTree by Hilton Hotel San Jose, USA.
Accellera Systems Initiative hosted a luncheon, featuring Bob Smith Executive Director, SEMI ESD Alliance, who spoke on “The CHIPS Act and Its Impact on the Design & Verification Markets.” SEMI is said to have over 2,400 members globally.
Bob Smith began with a view of the design ecosystem today. The electronic systems and products market is currently worth $2 trillion+. The fabless/foundry and IDM market is said to be around $419 billion. The equipment and materials, and OSATs/C-Subs market is worth about $154 billion. Finally, the design automation and IP/services market is said to be about $13 billion today.
Chips Act is about Creating Helpful Incentives to Produce Semiconductors. The official name stands as the CHIPS and Science Act of 2022. It was signed into law in Aug. 2022.
The Chips Act’s mission is: to strengthen and revitalize the semiconductor R&D, semiconductor manufacturing, and investment in American workers. Priorities include meeting the economic and national security needs, ensure long-term leadership in the semiconductor sector, strengthen and expand regional clusters, catalyze private sector investment, generate benefits for a broad range of stakeholders and communities, and protect the taxpayer dollars.
The US Department of Commerce (DoC) will oversee $50 billion in investments to expand domestic manufacturing of mature and advanced semiconductors. The budget allocations for Chips Act stand at $52.7 billion, with $39 billion in manufacturing — to provide incentives to spur the development of new semiconductor fabs in the USA. $11 billion is allocated to R&D programs and workforce development. $2 billion goes for legacy chip production and microelectronics common.
For domestic manufacturing, there are incentives to develop domestic semiconductor manufacturing including ‘legacy’ chip production. For Commerce R&D and workforce development, there are plans for the National Semiconductor Technology Center (NSTC), National Advanced Packaging Manufacturing Program (NAPMP), and other R&D and workforce development programs.
Microelectronics Common (CHIPS for America Defense Fund) includes University-based prototype to fab semiconductor technology transition, DoD unique applications, and workforce training. CHIPS for America International Technology Security and Innovation Fund will co-ordinate with foreign governments to co-ordinate security, supply chain and communications. CHIPS for America Workforce and Education Fund will have 90,000 new domestic workers needed by 2025.
Design and verification focus
Where do design and verification fit in? There are four entities under DoC. NSTC will serve as the focal point for research and engineering throughout the semiconductor ecosystem, advancing and enabling disruptive innovation to provide US leadership in the industries of the future. NAPMP will strengthen the semiconductor advanced test, assembly, and packaging capability in the domestic ecosystem. It includes heterogeneous integration, tooling and automation, wafer/panel and substrate technology.
NAPMP target areas include co-design and verification, chiplets, pilot packaging facilities, tooling and automation, and materials and substrates. We also have the Metrology R&D (NIST), and Manufacturing Institute(s) USA.
Industrial Advisory Committee (IAC) provides advice and recommendation to Commerce and NSTC. It has members from the industry, academia, federal laboratories and others. It has 24 members, including representatives from AMD, Applied Materials, ASML, Ford, Intel, Micron, Microsoft, Stanford, Synopsys, Texas Instruments, UCB, etc.
IAC R&D Gaps Working Group has the R&D Vision for Chips Act program with grand challenges. These include capabilities with ecosystem gaps, and applications with research gaps.
IAC recommendations 1 include establish easily accessible prototyping capabilities in multiple facilities, with the ability to rapidly try out CMOS+X at a scale that is relevant for the semiconductor industry. There is need to create a semiverse digital twin. We also need to establish chiplets ecosystem and 3D heterogenous integration platform for innovation and advanced packaging. We need to build an accessible platform for chip design, and enable new EDA tools that treat 3D (monolithic or stacked) as an intrinsic assumption. We also need to create a nurturing ecosystem for promising startups.
The IAC’s role is to provide input and make recommendations. The IAC does not make policy or rules – it is only an advisory body. But, the IAC clearly recognizes the need for new design and verification automation tools that will be needed to support the missions of the NSTC and NAPMP (among others).
First order effects are the direct effects that the CHIPS Act would have on the design ecosystem (EDA, IP, etc.). Second order effects are positive benefits and opportunities that arise from the US focus on re-tooling domestic semiconductor manufacturing capabilities.
In first order effects, the CHIPS Act recognizes that the future of semiconductor design is moving to chiplets and heterogeneous integration. The need for new automation tools for design and verification is clearly recognized as being essential. Opportunity exists for new technologies and commercial solutions. It is important to follow the direction of the NSTC (hub for CHIPS Act activities and organizations) and the NAPMP.
Potential second order effects include WFD programs that should help address the chronic shortage of talent across our industry. Expansion of domestic manufacturing capability should lead to more on-shoring of design activities, which would require automation tools.
R&D programs in various projects under the CHIPS Act/NSTC will require tools, and may offer partnerships or collaboration to solve critical challenges in advancing the state-of-the-art. There are likely many others since the scope of the CHIPS Act is so broad.
May I take a moment to thank my dear friends, Bob Smith, ESD Alliance, Ms. Barbara Benjamin, HighPointe Communications, and Ms. Nanette Collins, NVC, for inviting me to be part of DVCon USA 2023.
Teams working to ensure implementation and future impact of US Chips Act
National Institute of Standards and Technology (NIST), USA, organized a conference today with the Industrial Advisory Committee (IAC) and participants from the US semiconductor industry on the Chips Act. The US CHIPS and Science Act will:
- Bolster US leadership in semiconductors.
- Promote US innovation in wireless supply chains.
- Advance US global leadership in the technologies of the future.
- Catalyze regional economic growth and development.
- Provide STEM opportunities to more of America to participate in good-paying skilled jobs.
- Drive opportunity and equity for all of America in STEM and innovation.
Welcome remarks were made by Ms. Laurie Locascio, Under Secretary of Commerce for Standards and Technology. She thanked everyone for the work they are doing.
Ms. Gina Raimondo, Secretary of Commerce, lauded the industry, stating the portion they all are working on is very important. It will determine our success. TSMC did a ground-breaking ceremony this week in Arizona for a 3mm fab. We are focused on R&D roadmap. We need to get this right as it is very important! We need to have public-private partnerships.
There are four key elements to compete with China. She only mentioned the first — to invest in America. We have to protect, and are rolling out elements for semiconductors. America has great tradition in private-public partnerships. We need everyone to step up, and advance the work we are doing.
We are also nudging TSMC to do more. We want a mega fab and a giga fab in the USA. They said we need to have the workforce. If you want TSMC to manufacture in America, we need to have the necessary workforce in America. The USA also needs design in semiconductors, apps, etc.
We are talking about changing the way we teach in America so that it is more applied, have more color and diversitycome in, have better K-12 education, etc. We are teaching computer science in every category of classes. We will provide all the support to the semiconductor industry. It is very important for the USA, and to deal with autocratic governments.
The 2021 National Defense Authorization Act’s (NDAA) call to create a National Semiconductor Technology Center (NSTC), and a National Advanced Packaging Manufacturing Program (NAPMP) has established a pathway for this urgent investment. It will uniquely accelerate the US transformation into a secure semiconductor powerhouse.
As President Joe Biden said in the post-passage release from the White House: “The CHIPS and Science Act is exactly what we need to be doing to grow our economy right now. By making more semiconductors in the United States, this bill will increase domestic manufacturing and lower costs for families. And, it will strengthen our national security by making us less dependent on foreign sources of semiconductors.”
Chips R&D update
Eric Lin, CHIPS R&D Director, NIST, provided the CHIPS R&D update. It is an exciting and unprecedented time. Teams are working hard to make sure we can implement the Chips Act and make future impact. The vision is for providing economic security, national security and future innovation. We need to have continued and sustained programs. $39 billion is meant for manufacturing, and $11 billion is reserved for R&D. Major programs have been identified.
We are strengthening and advancing US leadership in R&D. It is an integrated ecosystem driving innovation. This is in partnership with all partners — industry, academia, government, and allies. We have a strategic view of the R&D infrastructure, participant value proposition, and technology focus areas. We are informed by the Industrial Advisory Committee. There are the National Semiconductor Technology Center (NSTC), Metrology R&D, etc. We had two semiconductor metrology-focused workshops in April 2022. We intend to continue this process.
NSTC has the vision to serve as focal point for research and engineering throughout the semiconductor ecosystem, advancing and enabling the innovation to provide US leaders in the industries of the future. NSTC white paper will come out in Q1-2023. It will summarize the results of a landscape analysis, outline a government structure, and describe a preliminary operating and financial model. It will focus on research and engineering on challenging projects with a time horizon of 5 years. NSTC will serve as key convening body for the ecosystem. NSTC will have core of centrally-operated, inhouse research, engineering, and program with a network of directly funded and affiliated entities.
National Advanced Packaging Manufacturing Program (NAPMP)will strengthen the semiconductor advanced test, assembly, and packaging capability. The National Advanced Packaging Manufacturing Program has technology areas, such as co-design, chiplets, heterogenous design, platforms, advanced tooling, and materials and substrates. We will identify the areas of focus and services needed to build domestic capacity.
Manufacturing USA Program Design
Ms. Mojdeh Bahar, Interim CHIPS R&D Manufacturing USA Director, NIST talked about Manufacturing USA Program Design. Its goals are to enhance the industrial competitiveness, increase economic growth, reduce energy use, and strengthen US national security. It can also facilitate the transition of innovative materials, etc.
The Manufacturing USA Network consists of 16 agencies — ranging from electronics, environment, materials, etc. 16 institutes with 2,320 member organizations are partnering on grand challenges. 708 collaborative technology and workforce R&D projects are going on. 63 percent of the members are from the industry, and 72 percent are small. $127 million in federal program funds attracts $354 million in state, private, and pandemic funds. Over 90,000 people are trained in advanced manufacturing.
We have been working on the Chips Act for a while now. We have microelectronics roadmaps. We have an RFI that will inform NIST’s development of funding opportunities for federal assistance to establish Manufacturing USA semiconductor institutes.
Dr. James Olthoff, Interim CHIPS R&D Metrology Director, NIST, said we are very excited about the Chips program. It has four aims: focus areas for grand challenges, broad-based awards and partnerships, workforce component, and developing instruments and facilities. On Sept. 1, 2022, we listed metrology grand challenges, with metrology for materials purity, etc.
We have two clusters of focus areas. Cluster 1 looks at advanced metrology, modelling, standards, etc. Verification and validation of advanced models, advanced modeling for next-gen manufacturing processes, etc. Cluster 2 looks at the materials aspect of the industry. We are developing new measurement technologies and services. Materials characterization metrology for advanced packaging is another area.
Eric Lin added that USA is also having international co-ordination. Strong alignment on the value of R&D, identifying effective leverage points, and specific program areas. There are discussions around the supply chain, guardrails, etc. The impact of Chips R&D program is maximized when integrated with programs across the USG. We are working closely with DoD, DoE, NSF, and other agencies, with support from the White House and OSTP.
There is the DoD microelectronics commons to ensure that growth supports and takes advantage of national defense technologies. Cores include commercial hubs and foundries, mid-TRL prototyping, pilot, test, and assembly through commons, and high TRL production and commercialization for DIB, services, and others.
We also have alignment timeframes. We are road-mapping from 3 to 30 years, access co-ordination up to 12 months, leadership execution management from 1 to 5 years, and resource co-ordination up to 12 months. The USG Shared Resource Network will have expanded capability, and higher chance of success. Actual capabilities and functions of programs are TBD. The NSTC white paper will come out in Q1-2023. Additional steps will be shared thereafter.
Update on R&D working group
Dan Armbrust, R&D Working Group Chair, Silicon Catalyst, updated on R&D Working Group. There are R&D gaps, organization and PPP gaps, and workforce gaps. We are looking at the long-term research areas for the semiconductor industry. We have put together a 90-day sprint. We will be wrapping up the WG recommendations in Jan. 2023, and finalize recommendations to the Industrial Advisory Committee (IAC) in Feb. 2023.
We need to establish the grand challenges and refresh periodically. We need to have a role for Chips Act entities and funding. We have assembled an inventory of relevant reports and white papers (~15). We have reviewed member inputs on R&D grand challenges and gaps. We have formed three breakout teams to begin drafting recommendations. We are on schedule to finalize recommendations to IAC by Feb. 15, 2023.
The breakout teams are looking at R&D grand challenges and gaps, establishing research grand challenges and refresh periodically, and how the Chips Act entities can address R&D grand challenges and gaps.
Ms. Deirdre Hanford, Chief Security Officer, Synopsys, talked about the DoC IAC — Organization/PPP Working Group. We are listening to what the DoC is trying to achieve. We have an outstanding team in place. We will review and examine various funding sources for semiconductor R&D, and map out relationships among the entities to ensure spending efficiency. We have to review the essential functions and governance of the NSTC and NAPMP. We are also reviewing PPP proposals for R&D partnerships, value proposition, etc.
The Department will release a white paper in Q1-2023 that will summarize the details of the landscape analysis, governance structure, and preliminary operating and financial model. Imec has been around for four decades. We need to understand their model to help our government and industry. We need to also look at how R&D instruments need to work together across DoD, DoE, NSF, DoC, etc. How will co-ordination between various R&D efforts take place? We also need to look at what alignment exists in various inputs to DoC on NSTC/NAPMP, etc.
CHIPS funding key to address memory wall, democratize access to advanced semiconductor design, develop open chiplet ecosystem
Following the landmark enactment in August 2022 of the CHIPS and Science Act to re-invigorate domestic semiconductor manufacturing and research, the Semiconductor Industry Association (SIA) and the Boston Consulting Group (BCG) released a report titled American Semiconductor Research: Leadership Through Innovation, identifying five key areas of the semiconductor R&D ecosystem that should be strengthened by the new law’s R&D funding.
The report highlights the importance of government-industry collaboration on two historic new entities—the National Semiconductor Technology Center (NSTC) and the National Advanced Packaging Manufacturing Program (NAPMP)—created by the CHIPS and Science Act. The study also calls for CHIPS funding to be used to bridge key gaps in the current semiconductor R&D ecosystem. Doing so, will help pave the way for sustained US chip innovation leadership.
Eric Breckenfeld, Director of Technology Policy, SIA, said Chips R&D implementation is to promote the collaborative R&D ecosystem aligned with industry technology agenda. It needs to support transition pathways for innovative technologies, and upgrade research infrastructure for early-stage ecosystem. It can also establish and extend access for mid-stage development and prototype infrastructure, convene industry, academia, and government for collaborative innovation partnerships, etc. Semiconductor incentives include construct, expand or modernize fabs located in the USA. NSTC aims to strengthen security of supply chain and economic competitiveness, and public-private partnership. NIST or commerce includes National Advanced Packaging Manufacturing Program.
Innovative technologies face transition barriers at multiple stages. They have to go through basic research, applied research, pathfinding and prototyping, piloting, and scaling to volume production. There is scaling up production of pilot manufacturing processes to commercially useful volumes. There are funders and performers in the NSTC/NAPMP and Valley of Death. Funders include DoE Office of Science, NIST, SBIR/STTR, etc. Performers include DoE National Labs, Universities and NNCI, NIST Laboratories, etc.
NAPMP priority
Gilroy Vandentop, Director of Corporate University Research, Intel, stated that there are so many participants and stakeholders. There are several challenges facing us. A white paper will also be released soon. Intel hopes for an industry-supported board. Shrinking the feature size is never going to drop down. We think there will be some capacity in the Intel Oregon facility. NAPMP is another priority area for Intel.
We need different academic groups to work together. We need good partnership with the academia. We will also need to focus on workforce development. We need to make that scalable and accessible. We also need to focus on marketing. We allow students to develop chips using our technology. We like what the Semiconductor Academy has been doing. We need to get started with workforce development right away. Chip programs will help them get into manufacturing.
SRC can help broaden the student population. More internships are needed. Jump 2.0 program is also ongoing. SRC is ramping up sustainability programs. Sustainability research will also have to grow at SRC.
Dr. Vijay Narayanan, IBM Fellow, said workforce development is critical. We need to start early with high school programs, etc. We also need to have regional clusters, and democratize the semiconductor education. Capturing that is going to be very important.
Addressing memory wall
Steve Pawlowski, CVP, Advanced Memory Systems, Micron, said the cost of moving data has been rising. Data movement energy for even today’s most-efficient memory solutions can be >100x the energy required for compute. Reducing that ratio is critical. Some workloads require even more data/compute. Addressing the memory wall is critical to long-term leadership.
Looking at memory trends, domain-specific architectures (DSA) scaling through increasd memory efficiency is needed. Analog accelerators pave way for orders of magnitude efficiency improvements for certain domains. There are building blocks in a memory-centric world. We need architectures/algorithms for 100x higher bandwidth, etc. We need memory-centric design. There will be tightly-coupled data and memory. DSLs centered around data locality and movement are necessary, and must be easy to program. 3D design and packaging are also required.
Memory CoE is building an ecosystem around prototyping hub. We must have infrastructure to enable, such as fab clean room space and leading-edge tools for technology development and building chip prototypes. We need advanced surface analytical and imaging labs, heterogenous integation, leading edge memort design and simulation capability, etc. This should be aligned to national priorities. SRC 2030 Decadal Plan for Semiconductors outlines key focus areas for post Moore’s Law development.
Advanced Memory Coalition of Excellence (CoE) will establish prototyping capabilities and ensure fast ramp from lab to fab with co-development across CoEs and project prioritization of vertical integration. We have challenges such as enabling high-performance energy-efficient computing. Also, reducing chip design complexity by system-level optimization, etc. Cross CoE activities will drive full stack innovation.
Opportunities in NSTC and NAPMP
Dr. Raja Swaminathan, CVP, Advanced Packaging, AMD, noted there are opportunities in NSTC and NAPMP. There should be aligned governance for them to ensure synergy. Silicon does not exist without packaging. Prototyping capabilities should be built in geographically distributed models encompassing upto six CoEs aligned around major technical institutes. CoEs should be around memory, logic, mixed-signal, RF, and power , architecture, design and tools, life sciences, NAPMP packaging, etc. We should identify a set of nationwide grand challenges.
AMD has recommended setting up national microelectronics education and training network, upgrade lab facilities and equipment, update curriculum development, hiring at least 100 new microelectronics faculty, support university access to industry-standard resources, and industry dynamics — manufacturing jobs are growing, but design jobs are experiencing exponential growth. EDA also needs to modernize for future chip designing.
Innovation in mixed-signal world
David H. Robertson, Senior Technology Director, Automotive, Communications and Aerospace, Analog Devices, spoke about innovation in the mixed-signal world. Markets and development are global for analog/mixed-signal capabilities. There are extreme diverse set of technologies, such as materials, devices, circuits, architectures, and systems. Core markets and technologies are various, such as aerospace and defense, automotive, communications, consumer, industrial automation, instrumentation, energy, power, intelligent buildings, healthcare, etc.
Collaboration becomes much more challenging (but not impossible), as you move closer to commercialization. Lack of access to/experience in manufacturing can create serious blind spots. Valley of death problem is half technical. CHIPS R&D funding can make a difference. US already has superior R&D intensity and superior market share. US semiconductor industry already spends big on R&D. We can convene collaborative full stack systems among our aims to fill critical gaps. We need to encourage academia, and SMEs/MSEs, and talent development.
Key priorities and innovation opportunities
Dr. Vijay Narayanan, IBM Fellow and Strategist for the Physics of AI, Senior Manager, PCM & AI Materials, IBM T. J Watson Research Center, spoke about key priorities and innovation opportunities. We need to democratize the access to advanced semiconductor design and spur design innovation. We need to accelerate the open chiplet ecosystem. We also need to reduce cost of chip design using EDA modernization.
The AI imperative is necessary to reduced-precision to increase compute efficiency. We can overcome Von-Neumann bottleneck with near-memory compute, in-memory compute, and increased memory bandwidth, etc. We need device architectures for vertical stacking. We can enable backend scaling beyond Cu-novel materials, processes, and integration.
We also need to democratize access to advanced semiconductor and HI technology. Next-gen HI technology can be used for 3D chiplet and increased bandwidth for system performance. Open chiplet ecosystem is breaking down barriers. It enables SMEs to work with large companies. Emerging open standard candidates include bunch of wires (BoW), universal chiplet interconnect express (UCIe), etc. EDA modernization is a platform for designers to scale their workloads on the cloud. They can transition EDA design flows to the cloud. AI/ML-driven design flow orchestration and design productivity improvement can also be achieved.
US Chips and Science Act: What’s in it, and implementation?
Center for the Study of the Presidency and Congress (CSPC), USA organized a conference today on the US Chips Act.
There was the opening panel discussion on the Chips and Science Act: What’s in it, and implementation? Dan Mahafee, Senior VP, Director of Policy, CSPC, was the moderator. $28 billion is now earmarked for the cutting-edge nodes, such as 5/7nm, and $10 billion for legacy nodes. He also asked how the legislation will look at the new challenges. How does it bring things from the lab to the fab?
Andy Keiser, CSPC Senior Advisor; Principal, Navigators Global; Senior Fellow, George Mason University National Security Institute, said the importance of chips has now become clearer to folks everywhere. A lot of countries, along with the US, are looking at the supply chains seriously. Chips Act has been going on for a number of years. South Korea, Japan, and EU, have started some new initiatives. Even India has started looking at chips. We also need a potential check on China. National security policy makers are looking at leading-edge nodes. There are lots of basic chips that are also needed. We have seen stand-downs of F-35s recently.
Ms. Becky Fraser, Senior Director, Government Affairs, Qualcomm, said we are very supportive of the Chips Act. An expanded semiconductor capacity is good for the ecosystem. The number of chips that we will continue to need are feature-rich nodes. Grants allocation have provided opportunity to semiconductor industry. Companies are now announcing strategic plans. Semiconductor market continues to grow. It was $556 billion in 2021, growing at 26 percent, and is expected to grow further in 2023. We will also need more of semiconductors to support the various industries.
Telecom part of plans
Mahafee said the US Government is also looking at next-gen 5G, 6G, Open RAN, etc. Ms. Diane Rinaldo, Executive Director, Open RAN Policy Coalition; Fellow, GMU NSI, said policy makers have been discussing these since a decade. We need to have enough supply for the US and for the developing world. Developing world is now catching up. With Open RAN, we are disaggregating RAN. Software, hardware, radio, etc., are all catching up in terms of deployment. We have come together and articulated policy makers with Telecom Act for the USA. We now have over 60 global companies. We are dealing with developing world looking at what will be their next build. If we are able to break open the RAN, it can be a step up, and transform the telecom sector. Open RAN is smashing expectation in sales. It is no longer a policy statement.
Ms. Becky Fraser, Qualcomm, added that looking at the public wireless fund, there is real opportunity to invest in strategic sectors in the USA. Open RAN and 6G are important. If we look at $11 billion in Chips Act, investments will get into new areas. This will increase competitiveness of the semiconductor industry. We are revitalizing the US semiconductor ecosystem. We are now looking in-depth at US semiconductor R&D investments.
We need to determine things with National Semiconductor Council, Advanced Packaging Center, etc., and see how the funds are allocated. Moving from lab to fab needs significant investment. Number of companies are coming together, having conversations. We are seeing a build around networks, public sector, etc. We are looking at chiplets, next-gen chips, etc.
This is a big package moving through. Ms. Rinaldo, GMU NSI, said DoC is an agency with 12 different bureaus. NTIA has received $48 billion for telecom networks, and $52 billion for chips. We are looking at how to set up programs, and how money is spent. President Biden signed the Chips Act several weeks ago. There are expectations as to how quickly money can go out.
Ms. Becky Fraser, Qualcomm, said the DoC has done an excellent job, moving swiftly and effectively. Emphasis is more on building the system within US Government. Applications are likely to come in within six months. We are looking at talent, systems, and information needed to implement the system. We also need fab development.
Keiser, George Mason University National Security Institute, noted that the US is matching China dollar-for-dollar, and you can build from there. There was some espionage to steal properties, which we are trying to stop. There are multitude of ways for governments to acquire new technologies. There is a level of competition that we have to contend with.
How much is the industry dependent on China? Ms. Fraser, Qualcomm, said the Chips Act is a great first step for semiconductor supply chain. Semiconductor is very capital intensive. $52 billion for chips is a concrete first step. We also have critical minerals, etc. We need to have more upstream-downstream partnerships. US has succeeded in semiconductor global value chain. We need to increase the workforce, design, materials and minerals.
Keiser, George Mason University National Security Institute, added that some critical materials and minerals are only available in China. We need to do more! TSMC, Intel, Micron, etc., have made major announcements. State governments will also become partners. Even key components have to be sourced. US Congress has put in this program. Programs are now geared towards having a life of their own. Today, 20 places are going to going to have their own technology hubs. He added memory is also necessary for national security.
Some of these US tech hubs are in places such as Boise, Reno, Portland, Bend, Spokane, Las Vegas, Phoenix, San Diego, Kansas City, Omaha, San Antonio, Pittsburgh, Atlanta, Miami, Tulsa, etc.
Develop workforce
Ms. Rinaldo, Open RAN Policy Coalition, said the entry barrier in telecom is high. We need to look at other industries that can also innovate. Money is going to help the smaller businesses. These are first steps, but they will be beneficial in the long run. The Science Committee has been quick to pass the Chips bill.
Ms. Fraser, Qualcomm, said tax incentives for the design segment are also necessary, so that leading-edge innovations in semiconductors can continue. We are customers to pure-play foundries. US is looking to expand the semiconductor manufacturing capacities. US has to be positioned for success across the entire semiconductor ecosystem.
Workforce is also a challenge. We need to continue to grow the talent pipeline. More talent will come online in next 2-5 years. A number of semiconductor companies are partnering with academic institutes in many areas. We are looking to attract larger number of the students to the semiconductor industry. We are also looking at R&D investments. We need to be doing more for academic collaborations, public investments, etc.
Ms. Rinaldo, Open RAN Policy Coalition, said we also need to look at the international community. US government also needs to make things easier for US companies in future. Also, in Congress, there is coalition on both sides of the aisle. The level of knowledge in Congress and general public has greatly increased. Keiser, George Mason University National Security Institute, noted that both sides of the aisle is collaborating. Ms. Fraser, Qualcomm, added that reality has touched different sides of the country. Semiconductors, Open RAN, and other technologies will be important for many more companies.
Glenn Nye, President and CEO, CSPC, noted we need to figure out how to co-ordinate better. We need to be fast and thoughtful, and take on roadblocks. We need to collaborate as best as possible.
On a separate note, India needs to develop new tech hubs beyond the metros and perhaps, some state capitals.
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