Pliops demonstrated its latest storage processor at the ongoing Flash Memory Summit 2019 (FMS), being held at the Santa Clara Convention Center, California, USA. The revolutionary new architecture increases data center storage efficiency by over 60X.
Pliops, based in San Jose, USA and Tel Aviv, Israel, is a storage processor company. It has 40 employees, and has deep experience in database and SSD technologies. Pliops has completed work on its core technology. The first product is to be released in Q419.
The Pliops storage processor enables cloud and enterprise customers to offload and accelerate data-intensive workloads, using just a fraction of the computational load and power consumption.
Pliops, at FMS 2019, talked about the cloud networking trends. In networking, 100Gb is currently mainstream. It is now moving to 400Gb. For the CPU, the GHz has been doubling every 20 years. Adding cores marginally adds to the performance. As for the NVMe SSDs, it is 1,000x IOPs over HDDs and 10x IOPs over SATA 8. 16TB storage is currently mainstream. The growing gap between networking and storage vs. CPU performance will increase the data center sprawl and costs.
In the key-value storage engines, among the database/storage stack, there are storage engines, such as, RocksDB, WiredTiger, InnoDB, etc. These are responsible for data persistency. They also keep the data sorted, and are traditionally based on B-trees. LSM has taken over, while RocksDB remains popular. All of these are extremely complex and prone to variable performance.
If we examine the source of key-value inefficiencies, there are instances such as: how to efficiently map variable-sized data to fixed-size blocks? Or, huge memory maps vs. multiple flash accesses, and speed vs. space efficiency.
There are high CPU and I/O costs for sorting, resorting, and garbage collection of data. There is also high read and write amplification – typically 20-100x. This either reduces the flash lifetime or requires expensive flash. It also reduces effective application bandwidth. When using disaggregated block storage, 20-100x app bandwidth required.
The thin driver layer can be added to the database/storage stack, such as the MySQL, Mongo, Ceph. Here’s where the Pliops storage processor comes in.
Elaborating on the role of hardware, Pliops listed management of highly compressed object memory map as prime. It is extremely memory-efficient, and software alternatives are much costlier. It takes care of key sorting, object garbage collection, compression and encryption, data persistency and logging. It also frees memory and compute resources to run applications, and not manage storage.
Pliops offers a 13X improvement or performance benefit over software. Comparing Pliops vs. software at MySQL, Pliops offers 5X faster queries per second, and over 7X more transactions per second. There is 20 percent NVMe flash space savings, and 9.5X write-amp improvements for flash.
Pliops offered three deployment options. First, DAS or the accelerator card. Second, accelerator card in storage engine node. Third, SEaaS — storage engine as a service.
Pliops’ solution solves the scalability challenges raised by the cloud data explosion and the increasing data requirements of AI/ML applications.
Toshiba Memory America Inc. has introduced the XFMEXPRESS today. The XFMEXPRESS is a new form-factor technology for removable, PCIe-attached, NVM Express (NVMe) memory devices developed by Toshiba Memory Corp. It aims to redefine the storage for ultra-mobile and embedded applications.
The launch took place at the ongoing Flash Memory Summit 2019 at the Silicon Valley’s premier convention center, the Santa Clara Convention Center, California, USA.
It offers a powerful combination of size, speed, and serviceability. Compact footprint includes low profile, small form-factor and an optimized mounting space. It supports PCIe 3.0 and 4.0, and PCIe x2 and x4 Lane. Removable design comes with an innovative hinge connector and a screw-less locking mechanism.
Need for new form factor?
Why do we need another form factor? It creates a best of both worlds — M2 SSDs and BGA SSDs. We are providing a new form factor that delivers an unparalleled combination of features designed to revolutionize ultra-mobile PCs, IoT devices and embedded applications.
XFMEXPRESS pairs removable memory functionality with a robust, compact package. It enables a new category of small memory devices and SSDs that are easy to service or upgrade. It will help diminish technical barriers and design constraints.
The XFMEXPRESS optimizes the mounting space for ultra-compact host devices without sacrificing performance or serviceability with a mobile-friendly footprint.
It provides leading-edge PCIe attached, NVMe performance. Having a flexible, future-proof design, XFMEXPRESS offers the necessary flexibility and scalability to stand the test of time. It is also designed to deploy current and future 3D flash memory sizes.
The XFMEXPRESS has an innovative connector design. The JAE (Japan Aviation Electronics Industry Ltd) is the development partner on the XFMEXPRESS connector design and manufacturing. Features include:
‒ Hinge type connector
‒ Low profile and small size
‒ Lock structure
‒ Device removal possible in a small space
‒ Designed to enhance heat dissipation
‒ Supports PCIe 4.0 (16GT/s).
The XFMEXPRESS form factor’s no-compromise size and low profile (14mm x 18mm x 1.4mm) offers a 252mm2 footprint, optimizing the mounting space for ultra-compact host devices without sacrificing performance or serviceability. With this minimized z-height, the XFMEXPRESS form factor is excellent for thin and light notebooks and creates new design possibilities for next-generation applications and systems.
The XFMEXPRESS target markets include notebook PCs — thin and light, and 2-in-1s, automotive — EDR and drive recorders, as well as IVI and ADAS, gaming consoles, such as VR and HMD, and others, such as portable storage, surveillance, AR/VR HMD, MFP, etc.
Toshiba Memory is demonstrating the XFMEXPRESS solution live at Flash Memory Summit, August 6-8 in booth #307.
Aspinity, a semiconductor startup funded by Alexa Fund and others, and based in Pittsburgh, USA, recently announced the first smart-sensing edge architecture to tackle the power- and data-efficiency problems in the billions of battery-powered consumer electronics, smart home systems, and predictive-maintenance devices on which we increasingly rely.
Aspinity announced its reconfigurable analog modular processor (RAMP) platform, an ultra-low power, analog processing platform, that overcomes the power and data handling challenges in battery-operated, always-on sensing devices.
Incorporating machine learning into an analog neuromorphic processor, Aspinity’s RAMP platform enables 10x power savings over older architectures. Devices can now run for months or years, instead of days or weeks, without battery recharge or replacement.
Smart-sensing edge architecture
Elaborating on Aspinity’s smart-sensing edge architecture, Tom Doyle, CEO and founder, said that Aspinity offers a fundamentally new architectural approach to conserving power and data resources in always-on devices. The scalable and programmable RAMP technology incorporates powerful machine learning into an ultra-low power analog neuromorphic processor that can detect unique events from background noise before the data is digitized.
By directly analyzing the analog raw sensor data for what’s important, the RAMP chip eliminates the higher-power processing of irrelevant data.
System designers can now stop sacrificing features and accuracy for longer battery life. Aspinity’s analyze-first approach reduces the power consumption of always-sensing systems by up to 10x and data requirements by up to 100x.
The RAMP chip’s analog blocks can be reprogrammed with application-specific algorithms for detection of different events and different types of sensor input. For example, designers can use a RAMP chip for always-listening applications, where the chip conserves system power by keeping the rest of the always-listening system in a low power sleep state, until a specific sound, such as voice or an alarm, has been detected.
Unlike the other sensor edge solutions for voice activity detection, the RAMP chip also supports voice-first devices by storing the pre-roll data required by wake word engines.
For industrial applications, designers can use a RAMP chip to sample and select only the most important data points from thousands of points of sensor data: compressing vibration data into a reduced number of frequency/energy pairs and dramatically decreasing the amount of data collected and transmitted for analysis. This is the USP for the RAMP platform.
With so many ways to program a RAMP core, as well as broad algorithm support for different types of analysis and output, the RAMP chip uniquely enables a whole new generation of smaller, lower-cost, more power- and data-efficient, battery-operated, always-on devices for consumer, IoT, industrial and biomedical applications.
Much longer battery life
Short battery life makes always-on sensing devices unattractive. Will this change? Aspinity certainly thinks so! Doyle said manufacturers of battery-powered always-on sensing devices certainly want to improve battery life because users don’t want to have to frequently recharge or replace batteries.
Is this going to cut into battery suppliers’ revenues? He added that Aspinity does not remove the need to have a battery. Rather, it improves the battery life considerably, saving up to 10X battery in always-on sensing devices and up to 100x data. Thus, battery suppliers will still sell batteries; their batteries will last longer on a single charge (for devices that have rechargeable batteries). Device manufacturers may also be able to move to smaller batteries.
Demand for always-on sensing devices surging
Why is the demand for always-on sensing devices surging? For example, there are folks who may not appreciate this. Doyle noted: “People enjoy interacting with electronic devices in an untethered way (voice-first) – and they want this to feel natural. So, they want those devices listening all the time. They also want to have smart home devices that are wirelessly connected – and they want to have industrial machinery connected to wireless sensor nodes as well. This is the user interface migration story.
Finally, how does RAMP incorporate modular, parallel and continuously operating analog blocks that mimic the brain’s efficiency? Also, wasn’t this tried earlier? The patented and innovative RAMP technology enables sophisticated digital signal processing tasks to be replicated in analog.
Aspinity has leveraged the nonlinear characteristics of a small number of transistors to enable a new architectural approach to machine learning: modular, parallel and continuously operating analog blocks mimic the brain’s efficient neural network.
These blocks are configurable for typical analog tasks such as sensor interfacing, signal processing and data conversion as well as more complex tasks such as feature extraction, event detection and classification. Each one of these blocks is implemented in a much smaller footprint than a traditional analog block and allows early event detection from raw, unstructured analog sensor data.
Did you know that upto three vertical-cavity surface-emitting laser (VCSELs) dies can be integrated in a smartphone? Alright! What’s a VCSEL? Well, I first heard about VCSELs in 1999, from Agilent Technologies, while based in Hong Kong. I have been hearing about VCSELs ever since then.
For those who wish to know more, the VCSEL is a semiconductor laser diode, with laser beam emission perpendicular from the top surface, which emit from surfaces formed by cleaving the individual chip out of a wafer (from Wikipedia).
Sylvain Hallereau, project manager, System Plus Consulting, recently said: “3D recognition, with the flood illuminator, the dot projector and the proximity sensor, are all based on VCSEL laser components. Already integrated in flagship smartphones, these functions will quickly find a home in all smartphones, causing a sharp increase in VCSEL demand.”
According to Yole Développement, in Lyon, France, the global VCSEL market should surpass $3.7 billion by 2024, growing at a 31 percent CAGR between 2018 and 2024. The consumer market segment contributes to these impressive figures with a market value of $3.4 billion by 2024.
Behind the smartphone applications, the automotive sector, with the emerging 3D sensing functionalities, is also playing a key role. Yole announced a 185 percent CAGR growth between 2018 and 2024 as well.
VCSELs in smartphones, automotives
Elaborating on how VCSELs are now finding their way into smartphones and automotives, Pierrick Boulay, LED, OLED and Lighting Systems analyst, Yole Développement, noted: “First, let’s have a look in the past. VCSELs were already used in Blackberry phones in the navigation button, but the market has remained relatively small. The main starting point is the use of VCSELs for the Face ID module implemented by Apple, in November 2017. Since then, the other smartphones OEM are using the VCSELs for the same feature in high-end smartphones.
“In the automotives, VCSELs will be used for 3D sensing applications, like driver monitoring systems or LiDAR in the next few years.”
VCSEL market projection
That’s interesting. So, how large is the global VCSEL market today? What’s the anticipated growth in the future? Also, for smartphones and auto segments?
He added: “In 2018, the VCSEL market generate revenue of $738M, driven by smartphone applications and is expected to generate revenue of nearly $3.8B in 2024. Smartphone applications will continue to drive this market, with the implementation of VCSEL in high-end products today and in middle and low-end products in the next years.
“Also, VCSELs are today used for face recognition on the front side, but they are starting to be used on the rear side for photography, and at the longer term, for augmented reality application.
“On the automotive side, things will move later, around 2021-2022, with the integration of driver monitoring system and light detection and ranging (LiDAR). The automotive market is expected to reach nearly $240M in 2024, growing at a CAGR of 185 percent between 2019 and 2024.”
Future smartphone applications
In the future, a smartphone should embed VCSELs for proximity sensing, and front and rear 3D sensing. So, are these the only applications using VCSELs? What about the others?
Boulay noted: “These applications will be the main ones using VCSELs in smartphones. 3D sensing is today implemented in luxury and high-end smartphones. In the next years, 3D sensing will also be used in middle- and low-end products, as the cost of these features will decrease. Other applications, like particle monitoring, could be integrated in smartphones, but this is expected in the long term.”
VCSELs vs EELs
Now, how are VCSELs likely to compete with the edge-emitting laser (EEL), especially for middle and short-range LiDAR?
Alexis Debray – Technology and market analyst, Yole Développement, said: “For middle- and short-range LiDAR, the detection distance will be limited to 120-150m, thus limiting the need of high-power laser source. The output power of VCSELs is directly linked with its surface. Hence, the more output power is needed, the higher the cost.
“VCSELs also have several advantages on EELs, as they have a narrow emission angle resulting in simpler optics, arrays are easy to build, and a low temperature shift. On the manufacturing side, wafer-level packaging (WLP) is possible, which will be necessary for a better integration of LiDARs in vehicles parts.”
Long-range detection challenge
The use of VCSELs for long-range detection is still challenging due to the VCSEL’s limited-output optical power, compared to EELs. How will this be overcome?
Debray added: “In the majority of long-range LiDAR using time-of-flight principle, EELs are combined with avalanche photodiodes (APDs). These sensors are low cost, developed for a wide range of wavelength, but have a limited sensitivity. Few LiDAR manufacturers are using VCSELs. However, they are using this type of laser with sensors that can detect a single photo, SPADs, to be able to detect objects at 200m.
“The downside is that, contrary to APDs, SPADs are digital, and need to use a time-to-digital converter (TDC), and potentially lose information.”
LiDAR in automotives
Finally, how is LiDAR ‘en route’ to mass production in the automotives market?
Debray, noted: “In the past months, collaborations between LiDAR companies, Tier 1s, and car manufacturers have intensified. One example is the collaboration between Innoviz, an Israeli LiDAR company, Magna, and BWM, with plans to integrate LiDARs using MEMS optical scanners in personal cars by 2021.
“In a separate collaboration, Continental plans to integrate Flash LiDAR in personal cars in a similar timeframe.”
2018 was a good year for MEMS foundries offering manufacturing services. In 2019, piezoelectric technology is seen to be increasing its momentum. Edge computing and big data are other trends favoring the MEMS industry.
Performance in 2018
First, let’s go back to the past and see how was the MEMS manufacturing market performance in 2018. Eric Mounier, fellow analyst, Photonics, Sensing & Display, Yole Développement (Yole), said: “Competition was fierce for companies manufacturing the same devices. Broadcom led the race with its RF BAW filters in the consumer market. Two battlegrounds formed around inertial and pressure MEMS for consumer and automotive applications: NXP and Bosch competing in the automotive segment, while Bosch and STMicroelectronics clashing in the consumer market.
“Regarding MEMS foundries offering manufacturing services, 2018 has been a very good year for them in general. All foundries saw their revenues increase, some slightly others by a lot. ST is still profiting from its exclusive contract with HP for IJ printheads manufacturing. EU MEMS foundries were more focused on added value than volume, while Asian foundries were mostly interested by high volumes. Further, several MEMS foundries have already added, or plan to add, PZT and/or AlN capabilities to address the upcoming piezoelectric MEMS manufacturing trend.”
MEMS industry in 2019
Now, let’s see how 2019 has been panning out, so far. According to Mounier, in 2019, piezoelectric technology has been increasing its momentum. A revolution in MEMS technology is underway: piezoelectric MEMS.
More and more gyroscopes, BAW filters, and inkjet heads are being created with piezoelectric MEMS. Now, microphones, microspeakers, autofocus, and pMUT for fingerprint sensors, ultrasound, and gesture recognition, are underway too.
Public/mainstream interest in this technology is also reflected by the increasing amount of funding in piezo tech. Another trend is edge computing, with sensors and MEMS driving a new age of technology. Big data is an industry born of recent advancements in AI and ML, built upon and fueled by a wealth of new data from ever-expanding sensor applications.
Sensors are digitizing the human experience, and as the real and virtual worlds move closer together, it will be sensors that bind them, enabling new experiences for users everywhere. Running AI at the edge, coupled with sensor fusion, will open new applications for MEMS in audio, motion, olfactometry, and imaging.
Difference in revenue
Now, there seems to be some difference in the revenue numbers for 2018. For example, after ST, others drop off, from 516, down to 66? Are the others not doing adequate development, or bagging orders?
Mounier said that the revenues of the top 30 players seem to have a big dynamic range, from $1.5B for the first (Broadcom) down to $66M for the last (Sony). The reasons stem from their various business models, in conjunction with the capacity of each MEMS device penetration in various applications:
- Players with high revenues (>$400M) established in a specific market and are the market leaders by making a specific MEMS device, i.e. Broadcom with its RF filters in the RF communications market; TI with its DLP (optical MEMS) in the consumer projector market; HP with its IJ printheads in the consumer printer market, Knowles with its MEMS microphones in the mobile/hearables market, etc.
- Players with high revenues (>$400M) that have a diversified product portfolio and that are present across many markets, i.e., Bosch and ST present in consumer/automotive markets, offering pressure, inertial MEMS; NXP in automotive offering pressure/inertial MEMS and magnetometers; TDK in consumer/automotive/industrial offering pressure, inertial, ultrasound and gas sensor MEMS, etc.
Then, why did the revenues of inkjet head players like Canon and HP rose, while that of Epson and the others shrank?
He clarified: “On one side, HP and Canon traditionally compete in the consumer and office printhead market, and typically, contest for the increased sales. HP recorded slightly positive year-over-year growth due to the increased demand for consumer printers and also because of strong adherence to its cartridge loyalty program. This recovery in the disposable printhead market is a mix of shipment increase from last year and ASP increase. Canon’s revenues decreased due to its loss of some market share to HP in the same consumer and office printer market.
“On the other side, industrial printing is still structuring, therefore the players in this market didn’t exhibit any positive growth. However, the major news from the industrial inkjet printhead manufacturer is the acquisition of Panasonic Inkjet business by Konica Minolta. Konica Minolta announced in June 2018 the acquisition of the Panasonic MEMS printhead fab. Now, it has its own MEMS manufacturing facility. Panasonic MEMS printhead will be continuously produced and Konical Minolta will ramp-up its new MEMS printhead in the next 2-3 years.
“Furthermore, Epson PrecisionCore chip factory will start production in 2019, which we think will strengthen its presence among the MEMS printhead manufacturers.”Read the rest of this entry »
Advanced packaging is said to be at the heart of innovation. Favier Shoo, Technology and Market Analyst in the Semiconductor & Software division at Yole Développement, member of Yole Group of Companies, France, and currently based in Singapore, elaborated: “In the mega-trend driven era of the new digital age, there are key market demands, such as increased I/O and package size overlaps. Low-power consumption also requires packaging innovation and is demanded by many end-applications — from IoT to datacenters.
“In order to enable these new performance and functionality requirements, the industry needs a high level of innovation for disruptive technological breakthrough.”
Savior of semicon development
How has advanced packaging emerged as the savior of future semiconductor development? According to Shoo, the main driver in the semiconductor market is changing from mobile to more scattered applications in the future – IoT, automotive, 5G, AR/VR, AI.
Advanced nodes no longer bring the desired cost-benefit, so R&D investment in new lithography solutions and devices below 10nm nodes is rising substantially.
Advanced packaging, therefore, represents an opportunity to increase product value (higher performance at lower cost) offering advantages down both the scaling and functional roadmaps.
New developments in FO landscape
Now, let’s focus on significant new developments in the Fan-Out (FO) landscape. In the core Fan Out (FO) market, the existing players are expected to go compete on cost — between wafer-level vs. panel-level solutions. PTI has commenced Fan Out panel-level packaging (FOPLP) production in 2018, and has made huge investment for this (> 1 billion US$).
Within OSATs, the player who can first satisfy new application demands for mobile and automotive will lead the way, set new standards, and capture the market. In the HD FO market, high-end (mobile APEs) and high-performance (HPCs/networking) is still led by the only significant player, TSMC.
SEMCO has started high-volume manufacturing (HVM) by FOPLP for its Samsung Galaxy smartwatch. Inevitably, the HD FO battle stage is set up for TSMC and SEMCO/Samsung Electronics.
Fan-Out packaging: As the die size scales, reducing ball pitch to have more connections within the die surface may not be the ideal roadmap for chip performance. Hence, the adoption of Fan-Out level packaging.
Fan-Out can integrate dies flexibly at reduced thickness because it eliminates IC Substrate process while also cutting the cost. In short, Fan-Out packaging provides benefits in form-factor, electrical performance and SiP integration capability.
3D TSV/hybrid bonding: TSV, hybrid bonding, or a combination of the two, are the mainstream packaging technologies that are able to provide high-end performance at the integration level reached by the actual stacking technologies.
Huge demand for HBM2 memory: HBM2 has become standard for high bandwidth memory. With 2 main current players in market, Samsung Electronics and SK Hynix, Micron is set to enter HBM business in 2020. Development for the 3rd generation is still ongoing and we can expect much improved performance from this device.
Achronix Semiconductor Corp. recently announced the Speedster7t FPGA+ family for AI/ML and high bandwidth data acceleration applications. FPGA+ is new class of technology. There is FPGA adaptability with ASIC performance. The architecture and ACE software further enables a new ease of use design paradigm.
This announcement comes closely on the heels of an earlier FPGA launch, based on TSMC’s 7nm.
Ground-breaking FPGA family
So, why does Achronix have a ground-breaking FPGA family? Steve Mensor, VP of marketing, Achronix, said: “Speedster7t is the first FPGA with a 2D NoC (network-on-chip) for enabling high-performance data paths and it will fundamentally change the design methodology for FPGA design by eliminating the challenges of creating switch networks between accelerator functions and the FPGA high-performance interfaces. Additionally, Speedster7t is the first FPGA with machine learning processors (MLP) optimised for AI/ML applications.”
Aren’t there other devices available as well? He said: “Intel AgileX does not have NoC or AI/ML-optimised DSP blocks. Xilinx Versal has a NoC that has approximately 1/10 the bandwidth, but it is not part of the FPGA fabric. It is made to move data between the ARM CPU complex, the vector engines and the FPGA fabric.
“Versal does not have AI/ML-optimised DSP blocks. Instead, they have the vector engines that are called AI engines. These are not part of the FPGA — they are separate functions located near the FPGA fabric. The AI engines will require an entirely new design framework, which may to be useful for companies that use FPGAs.”
Blending FPGA with ASIC
How has the it blended FPGA programmability with ASIC routing structures and compute engines? He added: “The 2D NoC is an ASIC function and so is the MLP. The NoC moves data at ASIC rates and the MLP completes AI/ML processing at ASIC rates.”
Elaborating on how Achrinix rethought the entire FPGA architecture, he said: “Speedster7t is the first FPGA that has a new hierarchy of routing structure, which is the NoC. The NoC allows for ASIC bandwidth performance and fundamentally simplifies the design methodology for creating accelerator functions in FPGAs.”
How are MLPs delivering the industry’s highest FPGA-based compute density, and what is the number, if any?
According to him:”The MLPs include up to 32 MAC functions per MLP. Additionally, they run at 750 MHz for AI/ML functions. Other FPGAs do not have the equivalent MAC count or performance. The mid-sized 7t1500 Speedster7t is capable of 86 TOps (tera-operations per second) and 8,600 images per second for ResNet-50.”
The Achronix 7t1500 and PCIe-based accelerator board with the 7t1500 will available in Q4 2019.
— By Ms Aanchal Ghatak & Pradeep Chakraborty