Dr. Aart de Geus, chairman and co-CEO, Synopsys, graced the ongoing SNUG India 2018, being held in Bangalore.
He delivered the keynote titled, “At the Heart of Impact,” discussing how the demand for computation power is changing virtually all industries — from automotive to healthcare to financial services.
Silicon has arrived at a state that is now making software possible that we only could dream of years ago. The world is moving into its next age: the age of smart everything. If you look at chips, there’s only one word and that’s called Moore’s Law. This is easily being the single, or most rapid sustained exponential in the existence of mankind.
The push to smaller geometries, which has been predicted as ending so many times. Moore’s Law is supposedly dead, and yet, Moore’s Law is now more expensive, but, it’s certainly not dead! We also have the opportunity to count the first 500 designs in each technology. FinFETs were impossible and too hard to do, but, here we are! The most advanced chips have all moved to this!
Let’s propose a thinking model of how to look at what EDA really is. The first question is: can you capture it on a computer? If you can capture it, can you actually model its behavior? If you can model it, can you simulate? If you can simulate, can you analyze a result? If you can understand the analysis, can you optimize, and if you can optimize, can you ultimately automate?
Digital simulation first, and then synthesis, completely changed the productivity picture in our field. The productivity push has continued. The notion of IP re-use, which, itself is not new, as transistor became gate, became register, became a small processor, became ultimately, big building blocks. The notion of a digital twin is essential.
AI is interesting, because it parallels somewhat, the history of EDA. You have to bring together data, collect the data, structure it, so that it’s usable. We have a lot of data in our programs. In the case of AI, it’s called learning, rather than simulating. That learning is then interpreted on the EDGE devices actively to ultimately, i.e., that creates some limited action field, and the long-term goal is autonomous behavior in many different fields. We have seen some remarkable advances that may initially not have gone quite as high as what we’re all familiar with, but the notion of a digital twin is essential.
There are four forces to understand. The first two, actually act in tandem. More computation allows for more machine learning, and more machine learning wants one thing more, even more machine learning, which we’ll push on more computation. This statement will drive the semiconductor industry for the next few decades.
The consumption of silicon will increase significantly. It is accentuated by one more thing: more data. Big data is a common term at this point. If you look at the number of sensors that are being put all over the world and all kinds of products, the amount of data that is becoming available is so large that it’s even difficult to make sense of it, unless you applied the very machine learning techniques that are now very rapidly evolving.
You need quantum physics to predict. Its called Ab Initio, means, from the start. It’s fundamentally going to the very basic of physics that are applicable to the atomic-molecular level. This technology is at Synopsys. We also added to this super-fine meshing to be able to describe the devices, and the ability to extract parameters.
We have invested in and are working with a number of partners on DTCO or design technology co-optimization. It has one objective. What do I tweak in the technology so that the design gets better?
If you look at the car, this is a source of data like you haven’t seen before: cameras, many RADAR, LIDAR, ultrasonic, and others. These cars are going to generate about four terabytes of data per day. This is where the cloud and AI machine learning will continue to blossom and grow at an unbelievable speed.
Simulation is going to be essential in the digital world. It will take many more dimensions. We are very much focused on the digital electronic side of things.
What made it all work is the fusion of three things. Logic, optimization, that was the heart of it, but also, in parallel, integrated timing, and the notion of libraries.
On the electronic side, we have all the necessities to the modeling and of the simulation. We have invested and grown the capability to do device simulation for photonic devices and the simulation of those. We have even incorporated RedHawk inside of IC Compiler II.
Now, EUV is coming into the picture and many other materials accentuate this. We have invested massively by working closely with all of the most advanced fabs in the world.
Vision processor is a fusion itself of multiple things. Synopsys actually has put quite a bit of effort in that as a building block. Our vision processor has a CPU that can have up to four cores, each made up of a scalar CPU, and a bit vector DSP. Around that is a convolution neural network that help do a number of the tasks. The interpretation of the neural network learning data in a common implementation platform and with all the software that makes this possible.
Safety and cars have already been a theme for us. Automotive IP does have needs. There’s a substantial number of standards around that.
Let’s also look at the notion of energy distribution. Are you going to put big cables to tank stations? How do you get it there? Is it local energy generation and by the way can we use that to deal with some of the clean energy needs to fix everything. It’s quite remarkable to find out that Tesla, which is aiming at being an electric car by increasing the autonomous car, also has a battery business, and has an energy distribution business by putting recharging stations, energy generation by owning a solar cell company.
Synopsys has invested in a number of things around security on a simple premise: all systems have inputs and outputs. They very quickly turn it to digital data, into electronic systems that are really systems on a chip, that are compute systems, really bring software, and the software itself is algorithms and proprietary code, and more dangerously so, third-party code and open source code vulnerabilities.
Today, networking the cloud is just one big computational continuum, that is now refining itself and becoming savvy. Be ready for the next phase! That absolutely has started and is upon us. The age of smart everything is happening at an incredibly fast clip and will have a very big impact. It will have an impact at a human evolutionary scale.
All the market segments are digitizing themselves. The semiconductor ecosystem is at the center of making this happen. This transformation is changing and challenging the semiconductor industry as we evolve to a world of smart everything that is networked, mobile, and also under increased pressure to become more secure. Synopsys is both humbled and privileged to be in the midst of this transformation.
Dr. Pradip K. Dutta, group VP and MD of Synopsys India and Sri Lanka, said: “As we move closer to completing two decades of SNUG in India, we are committed to making it the leading platform for the electronic design engineering community to connect with each other and learn to innovate from silicon to software. As the semiconductor industry and the ecosystem evolve with the accelerating pace of digital transformation, the center of gravity is moving to the intersection of hardware and software.”
The forthcoming International Test Conference (ITC) will be held on July 22nd-24th, 2018, at the Radisson Blu Hotel in Marathalli, Bangalore.
I must thank Navin Bishnoi, General Chair, ITC India, and director, ASIC India Design Center, GLOBALFOUNDRIES, and Veeresh Shetty, senior marketing manager, Mentor, for apprising me of developments.
The second edition of the conference, it is the world’s premier event dedicated to the electronic test of devices, boards and systems. At ITC India, design, test, and yield professionals can confront challenges faced by the industry, and learn how these challenges are being addressed by the combined efforts of academia, design tool and equipment suppliers, designers, and test engineers. The ITC India is being run under the guidance of ITC USA, and is supported by the IEEE Bangalore Section and IESA.
Let’s look at the test challenges that the conference seeks to address. Navin Bishnoi said: “DFT, test and reliability domains are seeing a huge focus with the need of standard test practices for a variety of applications across communication, automotive, computing and industrial.
“In addition, the cost of implementation and testing continues to be challenged, asking designers to look at innovative ways to optimize test, without impacting quality. ITC India brings the best minds from academia, research and industry to share best practices to enable the standard DFT/Test practices for variety of applications with reduced cost and high quality.
“The conference covers sessions on emerging test needs for topics such as: artificial intelligence, automotive and IoT, hardware security, system test, analog and mixed signal test, yield learning, test analytics, test methodology, benchmarks, test standards, memory and 3D test, diagnosis, DFT architectures, functional- and software-based tests.”
Next, what is the focus on DFT architecture and DFT strategy in automotive and other devices with low-cost testing requirements?
He added: “Today’s automotive safety-critical chips need multiple in-system self-test modes, such as power-on self-test and repair, periodic in-field self-test during mission mode, advanced error correction solutions, redundancy, etc. The conference has numerous presentations on summarizing the implications of automotive test, reliability and functional safety on all aspects of the SoC lifecycle, while accelerating the time-to-market for automotive SoCs.
“There is a strong focus on understanding the increasing use of system-level tests to screen smartphone and notebook processors for manufacturing defects by taking an in-depth look at the limitations of state-of-the-art scan test methodology. In addition, there is continuous study in the fields of DFT, diagnosis, yield learning, and root cause analysis, which use machine learning algorithms for solving various problems.”
Trends in modelling
Let us also look at the the trends in modelling and the simulation of defects in analog circuits and their applications that the conference seeks to address.
Bishnoi said that digital circuits have now evolved to standardize fault modeling and simulation. However, analog circuits have work in progress to look at new methods for modeling and simulating different types of faults using a mixed-signal fault injection methodology.
“Modeling defects in analog circuit use transient analyses that leverage different methods to inject faults. This is critical for today’s use case applications, like automotive, sensors, and industrial, which has significant analog components in the SoC. One of the trends that will be addressed in the conference is the layout-based fault modelling that is in fact a statistical analysis of process defects.
Now, to the directions made in advanced packaging technology. What’s the road ahead?
Bishnoi added: “Packaging technology has exploded with complexity in recent times for need of stacked dies, which involves change in processes, materials, equipment, as well as in the SoC implementation and sign-off. Advanced packaging enables small form-factor chips, with high-speed functionality for consumer market.
And, how are challenges in analog loopback testing for RF transceivers being addressed?
He said: “The main challenge in the implementation of loopback testing for RF transceivers is distinguishing the non-linearity effects of Rx and Tx, performance of channels during parallel testing, as well as coupling effects. Various test solutions will be discussed during the conference to address the challenges of an analog loopback testing of RF transceivers. Solutions employing the BiST techniques to have a quick TAT during manufacturing test will also be discussed.”
For those unaware, BiST or the built-in self-test, is a design technique in which parts of a circuit are used to test the circuit itself.
Finally, which version of the conference is this? Are we going to see regular ones? Bishnoi noted: “This is the second edition of the conference. We went through rigorous analysis and discussions with global leaders about the frequency and venue of the conference. It was decided to keep it annually (with the amount of growth in test/reliability space), as well as to keep it in Bangalore for the first 5 years, before we review it again to check if we should take it to other cities in India.
“The conference includes four keynotes from visionary leaders from Synopsys, Tessolve, Intel and Mentor Graphics, an exciting panel discussion on Fault Tolerance or Fault In-tolerance, as well as a variety of technical sessions and exhibits/demos from sponsors. It also has a dedicated day (on Sunday) for tutorials on six topics covering automotive, analog test, IEEE standards, machine learning in-test, system-level test and security.”
I will be present at ITC India 2018 in Bangalore, and look forward to meeting many of you, the attendees, as well! 🙂
Cadence Design Systems made a host of announcements at the ongoing 55th Design Automation Conference, at Moscone Center, San Francisco, USA. These are:
- Cadence delivers the first broad cloud portfolio for the development of electronic systems and semiconductors.
- Cadence collaborates with Amazon Web Services (AWS) to deliver electronic systems and semiconductor design for the cloud.
- Cadence and Microsoft collaborate to facilitate semiconductor and system design on the Microsoft Azure Cloud platform.
- Cadence collaborates with Google Cloud to enable cloud-based development of electronic systems and semiconductors.
- Cadence launches Liberate Trio Characterization Suite employing machine learning and cloud optimizations.
I caught up with Carl Siva, VP of Information Technology, Cloud, Cadence Design Systems Inc. and Craig Johnson, VP of Cloud Business Development, Cadence Design Systems Inc., to find out more.
First, why has Cadence chosen to go the cloud way now?
Carl Siva said: “Designs are continuing to become more complex, process nodes are getting smaller, and the volume of chip design data is increasing exponentially, and creating peak compute needs. Traditional data center models of company-owned, -housed, and -managed cannot support peak needs.
“Cadence has been engaged with cloud vendors and customers on this topic for several years. Our decision to launch our portfolio now is based on the increased customer interest and their growing confidence in the security of the cloud. Cadence’s cloud approach has been proven internally. So, it was logical to draw upon that extensive experience to drive customer adoption, so that they can achieve the productivity, scalability, security and flexibility benefits of the cloud.”
The Cadence Cloud portfolio includes customer-managed and Cadence-managed cloud environments. What’s in there and how are they different?
Craig Johnson, VP of Cloud Business Development, Cadence Design Systems Inc., said: “The Cadence Cloud portfolio offerings are targeted toward small-, mid-sized and enterprise- systems and semiconductor companies, providing improved productivity, scalability, security and flexibility benefits. For example, the platform can enable customers to gain access to dedicated compute resources in as little as five minutes.
“With the Cadence Cloud-Hosted Design Solution (the Cadence-managed option), small companies benefit from this offering because it eliminates the need for a costly internal infrastructure and the overhead from a large Computer-aided design (CAD) and IT staff, allowing these companies to focus on chip design innovation.
“Mid- to large-sized companies also benefit because the Cadence-managed environment allows them to move an entire design project or team to offload the strain on their on-premise environments. It also includes the Palladium Cloud, a managed and scalable emulation environment for customers desiring to use our hardware without the responsibilities of equipment installation or maintenance.
“With the Cadence Cloud Passport model (the customer-managed option), mid- to large-sized companies that have the means to manage their own cloud infrastructure internally and small companies that are cloud-savvy can use Cadence software tools via their current IaaS provider.
“The Cadence Cloud Passport model includes the Cloud-ready Cadence software tools that have been tested for use in the cloud, a cloud-based license server for high reliability, and access to Cadence software through familiar download mechanisms.
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Mentor, a Siemens business, has announced a strategic collaboration program with THE GAIN (The Global Accelerator for Innovation Network) – a technology accelerator company, focused on product engineering IP startups.
Both organizations will work with innovative Indian startups to accelerate, develop and customize IP to address domestic and international markets. They will focus on accelerating India’s product engineering IP ecosystem by helping companies in the early stages of entrepreneurship.
Established to advance the ESDM (electronics system design and manufacturing) ecosystem in India, the collaboration’s goal is to foster excellence in the early stages of startup companies. Both will work closely with the startups and entrepreneurs looking to establish and launch companies in the product engineering space, with a special focus on engaging with startups in the early phase of entrepreneurship.
“Mentor has established an outstanding track record of supporting, developing and accelerating startup ecosystems, both in India and across the globe,” said Raghu Panicker, Mentor’s country sales director for India. ”Through this strategic collaboration, we look forward to further accelerating the India startup ecosystem by working closely with promising product companies to make them successful.”
“India’s ESDM ecosystem is on a growth trajectory thanks to the ‘Make in India’ focus by the Indian government,” said Poornima Shenoy, CEO of THE GAIN.
“This collaboration with Mentor, a global technology leader, will have distinct benefits to startups looking to grow and succeed. It is our shared vision to collaborate and support highly successful startups in India who deliver innovative products. We are looking at accelerating the growth of at least 30 companies in the next three years.”
Outlining the specific steps Mentor-GAIN will be taking to help India’s product engineering IP ecosystem, she said: “At THE GAIN, we are looking to “excellerate” no more than five to seven start-ups per year. This is after a multi-tier rigorous selection process. Our entrepreneurs are often with deep industry knowledge and experience, who need a lead time of two-three years to prove the business and product viability.
“Tools are amongst the highest overheads in this journey. Here, the role of companies like Mentor, would be crucial. They have use cases, knowledge of decades and special schemes for entrepreneurs. This provides the right balance between cost and success. They also have leaders who understand and ‘walk the talk’.
“India needs to have more success stories with IP companies. We are looking at product engineering as a step in that direction. It is necessary for us to accelerate growth by productizing IP and leveraging global partnerships. It is not about overnight success, but about long-time multiplier returns. Our country and the industry needs to move in that direction.
“This is a unique partnership where both partners understand what works and what are the factors relevant to success.”
How does one justify ‘innovativeness’, when the two entities will support startups with innovative products?
Shenoy added: “It is a global race for innovation. We are looking for companies for the development of products, services, and applications related, to smart living and industry 4.0. India is a big market, but one, which is hugely price-sensitive.
“Our focus is on the B2B space and how soon can we get solutions out into the market in these areas. Innovation can save you money, help the environment and widen your market base. It could address niche segments and verticals. We are seeing interest from start-ups in other geographies to address this vibrant and dynamic marketplace. Global solution providers, like Mentor, function seamlessly across borders.
“At THE GAIN, we partner with innovative entrepreneurs by providing them with access to funding, active mentoring and to business. We can move to the next rung if they create MVP and validate it with their target customer base. This is a key area where they need assistance.”
Old wine! New bottle?
Finally, hasn’t this exercise been tried before? How are they confident about its success?
Shenoy said: “Every partnership is the start of a new beginning. It is only when we try that we can succeed. We are sure that as we embark on this journey on building the ecosystem and providing a platform for the Indian startups , we will learn and grow.
“We might slip up at times, but that is the beauty of a partnership. We learn together! In India, we have hardly seen any focus on this vertical. This understanding is a step in the right direction and a vital link to future success.”
Expressing his opinion on what Mentor is gaining out of this partnership, Raghu Panicker of Mentor, elaborated: “Mentor gains access to start-ups in the ideation stage itself. Mentor can, then, nurture them, and help start-ups with technologies in the areas of chips and system design. Start-ups are usually open to looking at new technologies.”
THE GAIN is a technology accelerator headquartered at Bangalore and founded by BV Naidu, former STPI director-turned-entrepreneur. The organization focuses on accelerating early-stage companies through access to funding, access to active mentoring and access to businesses.
Friends, if this interests you, please contact either Ms Poornima Shenoy at The GAIN or Raghu Panicker at Mentor. Best of luck!
NetApp has introduced the Data Visionary Engineering Center (DVC) in Bangalore. Paul van Linden, manager, EMEA and APAC EBC Program, said that as of now, there are four DVCs: in Sunnyvale and RTP North Carolina, USA, Amsterdam, the Netherlands, and now, Bangalore.
Having a DVC does make a difference. Linden said: “Partners are hugely important. In a 2017 APBM survey, 86 percent said their purchase size increased due to visit. 30 percent said that NetApp is a trusted advisor. 42 percent said that their sales cycle had reduced (by up to 9 percent). And, 79 percent said that they discovered additional products (gone up by 15 percent).” He added, “We provide proven business acceleration.”
On the question of why have a DVC in Bangalore, he said: “Global customers have some very unique requirements. Eg., they would like to have detailed conversations with coders. This (DVC) is a fantastic opportunity.”
Anil Valluri, president, Sales, India and SAARC, said: “It is a recognition of two things – one, the vibrancy of the market, and two, the huge amount of engineering talent in India. There are a lot of services being launched by the government. There is a growing market, with a lot of cutting-edge technology. We can tell people how to embrace digital transformation.
“The global SIs architecture centers are here. They can come here, and use technologies. It is a recognition of the potential of the Indian market. We can also serve as the knowledge center.”
Deepak Vishweswaraiah, MD and SVP, Data Fabric and Manageability Group, noted: “The whole digital transformation is not unique to NetApp. We are helping customers to progress on their data journey visions. Customers need to find new ways to do business. They have to find newer customers and newer ways to do business.
“We are also introducing the NetApp Cloud Volumes for Google Cloud Platform (GCP). We are now delivering data services with all the world’s largest hyper-scalers, such as Azure, AWS and Google Cloud Platform.
“We have modernized the IT architecture with Cloud Connected Flash. Powerful AI and high-performance applications with the world’s fastest enterprise all-flash array, the AFF A800 end-to-end NVMe.
“The NetApp ONTAP 9.4 storage OS improves performance, efficiency and data protection, also providing the industry’s first enterprise 30TB SSDs. It enables GDPR compliance and secures the data. New, intelligent cloud services further reduce TCO. The Active IQ provides insights for higher operational efficiency.
“We have also announced the NetApp Cloud Insights – Hybrid Cloud ITIM, delivered via SaaS. It improves customer satisfaction, pro-actively prevents failures, and optimizes to reduce cost. We have automated the tamper-proof retention of critical financial data.
“We are now accelerating our data visionary footprint in India. We have the largest R&D teams for NetApp in India.”
Earlier this week, the ESD Alliance recently signed a memorandum of understanding (MoU) to join SEMI as a strategic association partner.
As a SEMI strategic association partner, the ESD Alliance will continue to act as the central voice of the semiconductor design industry to promote its value as a vital component of the global electronics manufacturing supply chain.
Bob Smith, executive director of the ESD Alliance said: “SEMI and the ESD Alliance (formerly EDAC) have had a good relationship for many years, but there was certainly no pre-existing timetable to bring SEMI and the ESD Alliance together.
“The increasing focus on system design, and the need for manufacturing and design to be more closely linked have certainly been drivers for collaboration.
“Several years ago, SEMI expanded their mission to span the entire electronics product manufacturing chain including design. Since the ESD Alliance represents design, it is a natural fit for the ESD Alliance to fill-in this part of SEMI’s mission.
“From the ESD Alliance standpoint, we benefit by being able to leverage SEMI’s global platform to build our community. Although, we have members outside of North America, we don’t have any local presence outside of the US. SEMI has offices across the globe that will allow us to bring our programs to other areas of the world.
“Next, it is a good fit in the increasing the collaboration that’s required between design and manufacturing. In fact, many of SEMI’s member companies had asked them for deeper access to the design community.”
Now that product design has been added the to electronics manufacturing supply chain, it will bring manufacturing and design closer together by being common members of SEMI, he added.
What are the ways that SEMI gives the ESD Alliance an opportunity to further expand its reach and grow to its full potential?
Smith added: “SEMI will help expand ESD Alliance’s global presence by offering programs and events in conjunction with SEMI’s worldwide platform. Expand programs/activities in education, collaboration and networking to our members and SEMI members that are interested in design.
“We can also grow the membership further by offering more programs and being active in other geographies beyond North America.”
Lam Research is a global leader in wafer fabrication equipment and services since 1980. It is the world’s second-largest semiconductor equipment manufacturer. Lam Research India was established for software development and support in 2000. Now, it provides hardware and software engineering design services, and plays a strategic role as part of the Product Engineering and Global Operations teams.
With a centre in Bengaluru that houses over 800 employees, Lam Research India’s proximity to the customer and supplier base in Asia, as well as 24×7 operational support enabled by the time zone difference with the headquarters in Fremont, CA, makes Lam India an indispensable part of Lam.
While Lam does not manufacture in India, there is a manufacturing support system here that is involved in planning, procurement and logistics that caters to a worldwide network of suppliers and manufacturers.
Innovation in semicon
Let’s look at the work and innovation happening in the semiconductor space
Krishnan Shrinivasan, MD, Lam Research (India), said: “It is a very exciting time to be in the semiconductor ecosystem. There is a full spectrum of next-generation solutions that we have been working on for about five years now. We have made some headway in its implementation. Non-volatile memory (NVM), which is about the cloud and data storage, driven by the amount of distributed sensors that are collecting data that needs to be stored and monetized, has possibly experienced the highest growth.
“Another key transition is from two-dimensional architecture to a three-dimensional architecture. In a two-dimensional architecture, one is constantly working on shrinking, but on a single dimension. Now, we have an opportunity to continue to work on shrinking, but, also have an almost unlimited opportunity to vertically scale. We are just in the third- or fourth-generation of an inflection that will create an impact for at least ten generations to come.
“In terms of the logic roadmap, it has already transitioned from the world of planar transistor to the FinFET transistor scheme, and there are further generations of innovation in FinFET technology and a new transistor structure in later architecture.
“This roadmap is a 5-10 year one for the logic industry. While the clearest roadmap for the industry from a technology point is in NVM, all of the elements, logic and memory, including DRAM and NVM, have a technical roadmap, which is as good – if not stronger – than it has been in many years.
“The semiconductor industry is looking at an exciting decade from a technological advancement point of view. The level of innovation is being driven by an increasing number of applications for predictive medicine, autonomous vehicles, innovations in space and climate. All this would not have been possible without silicon.
“The innovation in silicon enables the development of the application space. Application development and growth can only be sustained through continuous innovation in the semiconductor industry.”
Transformative memory tech
Next, what about transformative memory technology and its latest inflection
Shrinivasan added: “The semiconductor industry is facing multiple technology inflections simultaneously. Revolutionary approaches are being sought after in place of incremental or evolutionary scaling strategies in order to provide consumers with smaller, faster and power efficient devices.
“The current inflections are focussed on multiple patterning, FinFET, advanced packaging, and 3D NAND. NAND flash has traditionally been made using two-dimensional (2D) or planar methods. However, in order to squeeze in more memory capacity without having to shrink feature dimensions, 3D NAND provides a viable option. This memory structure is different therefore, it requires new fabrication methods which are being developed. 3D NAND is being driven by several important advantages that it offers, including its ability to deliver higher capacity with a lower cost per bit.
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