Mentor Graphics

ITC India to address design, test, and yield challenges

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The forthcoming International Test Conference (ITC) will be held on July 22nd-24th, 2018, at the Radisson Blu Hotel in Marathalli, Bangalore.

I must thank Navin Bishnoi, General Chair, ITC India, and director, ASIC India Design Center, GLOBALFOUNDRIES, and Veeresh Shetty, senior marketing manager, Mentor, for apprising me of developments.

The second edition of the conference, it is the world’s premier event dedicated to the electronic test of devices, boards and systems. At ITC India, design, test, and yield professionals can confront challenges faced by the industry, and learn how these challenges are being addressed by the combined efforts of academia, design tool and equipment suppliers, designers, and test engineers. The ITC India is being run under the guidance of ITC USA, and is supported by the IEEE Bangalore Section and IESA.

NavinLet’s look at the test challenges that the conference seeks to address. Navin Bishnoi said:  “DFT, test and reliability domains are seeing a huge focus with the need of standard test practices for a variety of applications across communication, automotive, computing and industrial.

“In addition, the cost of implementation and testing continues to be challenged, asking designers to look at innovative ways to optimize test, without impacting quality. ITC India brings the best minds from academia, research and industry to share best practices to enable the standard DFT/Test practices for variety of applications with reduced cost and high quality.

“The conference covers sessions on emerging test needs for topics such as: artificial intelligence, automotive and IoT, hardware security, system test, analog and mixed signal test, yield learning, test analytics, test methodology, benchmarks, test standards, memory and 3D test, diagnosis, DFT architectures, functional- and software-based tests.”

Next, what is the focus on DFT architecture and DFT strategy in automotive and other devices with low-cost testing requirements?

He added: “Today’s automotive safety-critical chips need multiple in-system self-test modes, such as power-on self-test and repair, periodic in-field self-test during mission mode, advanced error correction solutions, redundancy, etc. The conference has numerous presentations on summarizing the implications of automotive test, reliability and functional safety on all aspects of the SoC lifecycle, while accelerating the time-to-market for automotive SoCs.

“There is a strong focus on understanding the increasing use of system-level tests to screen smartphone and notebook processors for manufacturing defects by taking an in-depth look at the limitations of state-of-the-art scan test methodology. In addition, there is continuous study in the fields of DFT, diagnosis, yield learning, and root cause analysis, which use machine learning algorithms for solving various problems.”

Trends in modelling
Let us also look at the the trends in modelling and the simulation of defects in analog circuits and their applications that the conference seeks to address.

Bishnoi said that digital circuits have now evolved to standardize fault modeling and simulation. However, analog circuits have work in progress to look at new methods for modeling and simulating different types of faults using a mixed-signal fault injection methodology.

“Modeling defects in analog circuit use transient analyses that leverage different methods to inject faults. This is critical for today’s use case applications, like automotive, sensors, and industrial, which has significant analog components in the SoC. One of the trends that will be addressed in the conference is the layout-based fault modelling that is in fact a statistical analysis of process defects.

Now, to the directions made in advanced packaging technology. What’s the road ahead?

Bishnoi added: “Packaging technology has exploded with complexity in recent times for need of stacked dies, which involves change in processes, materials, equipment, as well as in the SoC implementation and sign-off. Advanced packaging enables small form-factor chips, with high-speed functionality for consumer market.

And, how are challenges in analog loopback testing for RF transceivers being addressed?

He said: “The main challenge in the implementation of loopback testing for RF transceivers is distinguishing the non-linearity effects of Rx and Tx, performance of channels during parallel testing, as well as coupling effects. Various test solutions will be discussed during the conference to address the challenges of an analog loopback testing of RF transceivers. Solutions employing the BiST techniques to have a quick TAT during manufacturing test will also be discussed.”

For those unaware, BiST or the built-in self-test, is a design technique in which parts of a circuit are used to test the circuit itself.

Finally, which version of the conference is this? Are we going to see regular ones? Bishnoi noted: “This is the second edition of the conference. We went through rigorous analysis and discussions with global leaders about the frequency and venue of the conference. It was decided to keep it annually (with the amount of growth in test/reliability space), as well as to keep it in Bangalore for the first 5 years, before we review it again to check if we should take it to other cities in India.

“The conference includes four keynotes from visionary leaders from Synopsys, Tessolve, Intel and Mentor Graphics, an exciting panel discussion on Fault Tolerance or Fault In-tolerance, as well as a variety of technical sessions and exhibits/demos from sponsors. It also has a dedicated day (on Sunday) for tutorials on six topics covering automotive, analog test, IEEE standards, machine learning in-test, system-level test and security.”

I will be present at ITC India 2018 in Bangalore, and look forward to meeting many of you, the attendees, as well! 🙂


Mentor-THE GAIN to boost India’s ESDM startup ecosystem

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Mentor, a Siemens business, has announced a strategic collaboration program with THE GAIN (The Global Accelerator for Innovation Network) – a technology accelerator company, focused on product engineering IP startups.

MentorBoth organizations will work with innovative Indian startups to accelerate, develop and customize IP to address domestic and international markets. They will focus on accelerating India’s product engineering IP ecosystem by helping companies in the early stages of entrepreneurship.

Established to advance the ESDM (electronics system design and manufacturing) ecosystem in India, the collaboration’s goal is to foster excellence in the early stages of startup companies. Both will work closely with the startups and entrepreneurs looking to establish and launch companies in the product engineering space, with a special focus on engaging with startups in the early phase of entrepreneurship.

“Mentor has established an outstanding track record of supporting, developing and accelerating startup ecosystems, both in India and across the globe,” said Raghu Panicker, Mentor’s country sales director for India. ”Through this strategic collaboration, we look forward to further accelerating the India startup ecosystem by working closely with promising product companies to make them successful.”

“India’s ESDM ecosystem is on a growth trajectory thanks to the ‘Make in India’ focus by the Indian government,” said Poornima Shenoy, CEO of THE GAIN.

“This collaboration with Mentor, a global technology leader, will have distinct benefits to startups looking to grow and succeed. It is our shared vision to collaborate and support highly successful startups in India who deliver innovative products. We are looking at accelerating the growth of at least 30 companies in the next three years.”

Outlining the specific steps Mentor-GAIN will be taking to help India’s product engineering IP ecosystem, she said: “At THE GAIN, we are looking to “excellerate” no more than five to seven start-ups per year. This is after a multi-tier rigorous selection process. Our entrepreneurs are often with deep industry knowledge and experience, who need a lead time of two-three years to prove the business and product viability.

“Tools are amongst the highest overheads in this journey. Here, the role of companies like Mentor, would be crucial. They have use cases, knowledge of decades and special schemes for entrepreneurs. This provides the right balance between cost and success. They also have leaders who understand and ‘walk the talk’.

“India needs to have more success stories with IP companies. We are looking at product engineering as a step in that direction. It is necessary for us to accelerate growth by productizing IP and leveraging global partnerships. It is not about overnight success, but about long-time multiplier returns. Our country and the industry needs to move in that direction.

“This is a unique partnership where both partners understand what works and what are the factors relevant to success.”

Justifying innovativeness
How does one justify ‘innovativeness’, when the two entities will support startups with innovative products?

Shenoy added: “It is a global race for innovation. We are looking for companies for the development of products, services, and applications related, to smart living and industry 4.0. India is a big market, but one, which is hugely price-sensitive.

“Our focus is on the B2B space and how soon can we get solutions out into the market in these areas. Innovation can save you money, help the environment and widen your market base. It could address niche segments and verticals. We are seeing interest from start-ups in other geographies to address this vibrant and dynamic marketplace. Global solution providers, like Mentor, function seamlessly across borders.

“At THE GAIN, we partner with innovative entrepreneurs by providing them with access to funding, active mentoring and to business. We can move to the next rung if they create MVP and validate it with their target customer base. This is a key area where they need assistance.”

Old wine! New bottle?
Finally, hasn’t this exercise been tried before? How are they confident about its success?

Shenoy said: “Every partnership is the start of a new beginning. It is only when we try that we can succeed. We are sure that as we embark on this journey on building the ecosystem and providing a platform for the Indian startups , we will learn and grow.

“We might slip up at times, but that is the beauty of a partnership. We learn together! In India, we have hardly seen any focus on this vertical. This understanding is a step in the right direction and a vital link to future success.”

Expressing his opinion on what Mentor is gaining out of this partnership, Raghu Panicker of Mentor, elaborated: “Mentor gains access to start-ups in the ideation stage itself. Mentor can, then, nurture them, and help start-ups with technologies in the areas of chips and system design. Start-ups are usually open to looking at new technologies.”

THE GAIN is a technology accelerator headquartered at Bangalore and founded by BV Naidu, former STPI director-turned-entrepreneur. The organization focuses on accelerating early-stage companies through access to funding, access to active mentoring and access to businesses.

Friends, if this interests you, please contact either Ms Poornima Shenoy at The GAIN or Raghu Panicker at Mentor. Best of luck!

MOS memory investors, China to correct DRAM imbalance

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penn1According to an IC Insights report, the 47 percent full-year 2017 jump in the price-per-bit of DRAM was the largest annual increase since 1978, surpassing the previous high of 45 percent registered 30 years ago in 1988! This sounds interesting!

Are the rising DRAM prices aiding startup Chinese competitors? Are major DRAM suppliers somehow stunting global DRAM demand?

Dr. Walden C. Rhines, president and CEO, Mentor Graphics, a Siemens Business, said: “The DRAM business has always gone through cycles of imbalance between supply and demand. Growth of demand in the last 18 months has been stronger than growth of supply.

“Substantial investments in 2017 by the MOS (metal-oxide semiconductor) memory producers, as well as the addition of China to the supply chain, will correct this imbalance late this year or, at the latest, early next year.”

The DRAM price-per-Gb has been on a steep rise. To this, Dr. Rhines said: “It is a commodity, although there are many types of specialty DRAMs emerging. Because DRAMs are viewed by customers as a near-commodity, the price is heavily influenced by the availability of supply. Supply has been very tight during the last 18 months.

Malcolm Penn, chairman and CEO, Future Horizons, UK, added, “This is supply and demand, pure text-book economics.”

Are the rising DRAM prices opening the door for startup Chinese competitors?

Dr. Rhines noted: “Chinese competitors made their decision to invest in DRAM capacity long before the recent strengthening of demand in the balance of supply and demand. Of course, higher, or stable, pricing may make it easier for new producers to absorb the costs of ramping up new capacity and developing experience with a new technology.”

Malcolm Penn agreed: “Potentially yes, and to anyone else. Coca Cola were contemplating building DRAMs in the 1990s. DSRAM market boom, again, pure text-book economics. Whether or not they succeed is an entirely different matter. If the Chinese do enter the market, can they then survive the inevitable downturn and cycles? That remains to be seen!”

Can the startup Chinese DRAM producers field any competitive product soon? Dr. Rhines noted: “They probably can. But, they will have to develop a production base of “learning” to reduce cost, improve yields and maybe even reliability. This will take some time.”

Penn added: “Technically (i.e., meeting the spec), probably, yes. Reliability, probably no, for the Tier 1 customers (that will take several years to build up the production experience). Cost, definitely not!

“Their small fab scale and late learning curve start means that their die cost will be sizably higher than those of Samsung and SKH, and also Micron. Plus, their yields will be lower. Then, there’s the deep cash pockets issue to fund these ongoing cost disadvantages.”

300mm fabs
In a separate situation, some 300mm fabs closing, for example, ProMOS. Dr. Rhines said: “It’s because of an imbalance of supply and demand for the products they make, thus limiting their profitability. It could also be because they don’t see an adequate investment return from the expensive new capacity investments, and therefore, find it more attractive to phase out some of their existing capacity.”

Malcolm Penn felt that the fabs were too old and technically obsolete.

Finally, are there more IC companies making transition to fab-lite or fabless business model?

Penn noted: “There’s no-one left to change! Everyone’s now fablite or fabless, except for Intel and Samsung (logic) and the memory manufacturers.”

Dr. Rhines said: “Based upon the growth of foundry revenue vs. total semiconductor revenue growth, there must be a continuing transition of capacity away from IDMs toward foundries. In addition, IDMs like Samsung are finding it economic to build the foundry business to increase the volume base of products that utilize their technology and capital investment.”

PSS complementary to UVM: Dr. Wally Rhines

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Here is the concluding part of my discussion with Dr. Walden Rhines, chairman and CEO, Mentor, A Siemens Company.

Has the PSS been formally released? What are its implications?

RhinesDr. Rhines said: “Accellera released an Early Adopter spec for public review at DAC in June, 2017 and is currently working on completing our work in preparation for a 1.0 release in 2018. Accellera plans to have a “1.0 Preview” version available in February, 2018 (@DVCon US) for another 30-day public review period. Then, they will do one more cleanup pass, and submit to the Accellera Board for approval in May 2018.

“The expectation is that the Board will approve the Portable Stimulus Standard 1.0 version in June, 2018, prior to the DAC. Mentor plans to have Questa inFact fully updated by then, to fully support the new standard when it comes out.

“As for the implications, we expect the Portable Stimulus standard to be the next advancement in abstraction and productivity for SoC verification. It is not expected to replace UVM, but rather be complementary to UVM to improve coverage closure, verification efficiency, and effectiveness at the block level.

“The ability to re-use the verification intent expressed in PSS from a block-level UVM environment to a software-driven, embedded-processor SoC environment, on multiple platforms (simulation, emulation, FPGA prototyping, etc.), will provide a quantum leap in productivity.

“Since the Portable Stimulus specifications are declarative, tools can fully analyze the verification-intent description at the system level and generate multiple correct-by-construction implementations of use case tests, on multiple platforms, from a single specification without requiring the verification team to rewrite the tests in UVM for the blocks and C for the system.

By the way, are the semiconductor/EDA companies re-looking at designs, rather than analyze more than 500,000 defective parts every day to identify design and process problems? If yes, how?

He said: “With today’s increased design complexity – they do both – re-look at designs before manufacturing and analyze afterwards. The complexity of today’s designs and manufacturing process requires multiple approaches to achieve high yields in each new node that is rolled out.

“Design for manufacturing and for yield are a must. However, the knowledge of the specific design practices that need to be followed for a new node is developed in multiple stages: in pre-silicon, test chips, first production design and when chips reach high production volume.

* Pre-silicon: Simulation models are used for initial design rules. Many assumptions are made and care must be taken to balance the benefit with potential overdesign for a process that will mature over time.

* Test chips: Early test chips try to mimic the major features of a real design, however, limited complexity and volume means some design rules can’t be discovered at this stage.

* First production design: Additional complexity of a real design and increased volumes expose more issues that need to be fed back to design for future revisions or the next design on a node.

* High production volume and additional designs introduced: High production volume and each subsequent design can benefit from the learnings at the previous stages. Many issues during this phase are resolved with process improvements, but continuous learning still remains key.

“The challenge is not eliminating the later learning phases, as this will never go away. Rather, the challenge is for the industry to maximize the learning at each phase and establish a continuous improvement cycle in design to take advantage of the knowledge gained. This is the foundational idea in closed-loop DFM, which is a process to maximize the design for manufacturing benefit throughout all phases.

Let’s also look at verification. What is the latest regarding coverage and power across all the aspects of verification?

Dr. Rhines added: “Actually, the recent trends have expanded to multiple concerns that cut across all aspects of verification, beyond coverage and power, such as security and safety. One driving force behind these trends is the convergence of computing, networking, and communications technologies. This is driving new markets, such as the Internet-of-things (IoT) ecosystem and automotive.

“A common theme across these emerging systems is the need for security, safety, and low power–whether you are talking about IoT edge devices or high-availability systems in the cloud. These new challenges have opened innovation opportunities, enabling us to rethink the way we approach verification. For example, concerning coverage, new statistical metrics have emerged providing deep system-level analysis capabilities that leverage data analytics techniques. This insight has become essential for system-level performance analysis.
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Semiconductor industry performance a pleasant surprise: Dr. Wally Rhines

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The year 2018 is nearly upon us! And, who better than Dr. Walden C. Rhines, CEO and chairman of the Board of Directors of Mentor, a Siemens business, a leading industry personality, to provide us with an outlook for the global semiconductor industry!

Dr. Wally Rhines and I chatted about the global semiconductor and EDA industries, the Accellera Portable Stimulus Standard (PSS), and a host of other issues.

Semicon industry in 2018
First, how is Mentor predicting the global semiconductor industry to perform in 2018?

Dr. Rhines said: “The semiconductor industry performance for 2017 has been a pleasant surprise for most industry observers. The year is finally winding down, with the expectations for growth in the low 20s on the average – nearly 3-4 times as much as most observers had predicted only one year ago.

“Unit growth has consistently been 7-9 percent in recent years since the great recession. However, ASPs have been pretty consistently declining until 2017, when they were driven up mostly by memory prices for DRAMs and FLASH. Memory, once again, is behind the 2017 boom cycle. However, the rest of the IC business has also been relatively strong with growth in the higher single digits (7-8 percent), which is stronger than we have experienced in recent years.

“Memory prices are expected to soften as additional capacity comes on-line in 2018, especially as the year continues into the second half. However, the remainder of the non-memory semiconductor market should continue to have strong performance similar to 2017 (~7-8 percent) as the market fundamentals remain strong.

“Over the last several years, the semiconductor industry has experienced a wave of consolidations. I believe that we are between major waves of growth that are typical of the semiconductor industry. Historically, new semiconductor growth is ushered in by new applications that become possible when the cost per function, or some other new capability, makes the new application possible.

“In recent years, the cost per transistor for semiconductors has decreased more than 35 percent per year, just as it has, on average, for most of the last 60 years. It’s likely that continuation of this trend will, in fact, enable future waves of new semiconductor applications.

“Packaging, as well as package/chip simulation, continue to be important issues. Next generation simulation, verification, and analysis for multi-chip packaging configurations is now available. Now, designers of chips can intelligently analyze the packaging and pin-out configurations that will be most effective for cost and performance, based on a steady flow of data between the packaging engineer and the chip designer.”

EDA segment in 2018
And, how is the EDA segment looking in 2018?

According to Dr. Rhines, the EDA License and Maintenance is having a strong year in 2017. The annual growth is over 9 percent through the most recent four quarters with available data (Q3 2016 – Q2 2017).

He said: “The Semiconductor IP component of EDA achieved growth of nearly 17 percent overall, over the same period, as would be expected since Semiconductor IP is an important part of the supply chain for the broader semiconductor market.

“With expectations for the world economy and the overall semiconductor industry remaining strong, I expect semiconductor investment into design to also remain strong. EDA License and Maintenance is accounted for within the semiconductor company R&D expense budgets. Those budgets have a strong correlation to EDA License and Maintenance revenue. Therefore, I expect similarly strong growth in 2018.
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Design verification trends and role of emulation

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Sanjay Gupta, senior director of R&D, Mentor Emulation Division, Mentor, presented on the design verification trends and role of emulation.

Mentor2Verification needs are expanding beyond traditional functional verification. SoC power analysis, coverage closure and DFT validations are critical. Vertical market segment focus is crucial as verification needs are different for different verticals. Verification teams are global teams. Veloce platform addresses the modern verification challenges.

Talking about the design trends, ~31 percent of designs use over 800 million gates and ~20 percent use over 500 million gates.Next, 72 percent of designs contain embedded processors, and 49 percent designs contain two or more processers, while 16 percent designs have eight or more processors.

As for ASIC/IC completion to the original schedule, 61 percent designs were behind schedule in 2014, which increased to 69 percent during 2016. The number of required ASIC/IC spins before production had become seven spins or more in 2016.

Regarding verification trends, as for more design engineers vs. verification engineers, design engineers were growing at CAGR 3.6 percent, while verification engineers were growing at CAGR 10.4 percent, from 2007-2016. The ASIC/IC verification engineers were spending 39 percent of their time at debugging, 22 percent each at creating test and running simulation, and testbench development, and 14 percent time in test planning.

SystemVerilog was a clear leader at the ASIC/IC verification language adoption, while Accelera UVM was a clear leader at the ASIC/IC testbench methodology adoption trends.

In power and coverage, 72 percent more designs wre actively managing power in 2016 as against 59 percent in 2007. Among the power intent trends, the UPF 2x was a clear leader among notations used to describe power intent. Functional coverage is just nearly on par with code coverage, followed by assertions and constrained-random simulation, as far as the ASIC/IC dynamic verification trends are concerned.

Challenges for verification include larger, more complex chips, as well as the increasing software content. Transistor count for select ICs will likely reach 15 billion gates by 2022.

Vertical segments are facing constant innovation. In networking, SDN emergence is driving complexity, size, and port count. There is an increased importance of software. Networking is driven by Big Data, cloud and mobility.

Safety is critical verification for automotive design. Veloce delivers the functional safety verification. Emulation has moved to virtualization with Veloce2. Data-center friendliness and enterprise-level usage are prime. Veloce Strato has accelerated and moved on to the application age, and has a vertical market focus.

Crystal chip is the brain of the Veloce emulation platform. A chip is designed exclusively for emulation: fast compile and efficient, full visibility. The chip, system and software are architected together to optimize the emulation capabilities and productivity. The Veloce Strato offers the lowest cost of ownership.

Veloce power app offers low-power verification at SoC level where power controls come from the application software, handles large SoC (RTL/Gate) with full visibility, performs complete verification (e.g. OS boot) and shows accurate power numbers based on real switching activity.

You can also do low power verification with Veloce. There is broad UPF 2.x support and UPF 3.0 support is planned by the end of 2017. Veloce coverage app has comprehensive SVA assertion support, SV functional coverage, code coverage, standard UCDB support and merged with simulation UCDB, and flow to enable XML merge with other platforms.

Veloce structured around verticals

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Anoop Saha, Mentor, did a presentation on Veloce vertical solutions at the Emulation Conference in Bangalore.

MentorVeloce solutions are used across networking, storage, multimedia, mobile, CPU, automotive and military aeronautics. Veloce is structured around verticals to be segment focused, identify and address segment specific challenges, and identify gaps early on.

Veloce solutions are connecting the DUT to the external stimulus. iSolve speed adaptors connect real-life systems with the emulator. The Virtualab peripherals — VirtuaLab is the software representation of a speed adaptor. The Veloce transactor library – Veloce compatible verification IP. Transactors (VTL) to integrate with users UVM testbench and lower the abstraction layer.

In networking, for instance, the network switch is driving complexity. There is shift to SDN driving chip size and high port counts. Next, 5G is also driving new technology
and standards. Veloce for networking is offering solutions on top of core emulation platform. The verification flow is expanding to include Lab system validation. As of now, SDN is said to be creating a methodology shift. Mentor is said to be the only vendor with a complete offering.

Verification can no longer ignore firmware. Emulation enables earlier firmware development. Software debug is done with Codelink. The Veloce power app is used for broad base analysis. Veloce also offers complete solution for multimedia.

There has also been an industry shift from spec to benchmark. Many new apps target benchmarks for mobile devices. Examples are the AnTuTu benchmark, Geekbench for CPU and GPU benchmark, GFXBench, a GPU graphics centric benchmark, Android smartphone and tablet benchmark, etc.