The year 2018 is nearly upon us! And, who better than Dr. Walden C. Rhines, CEO and chairman of the Board of Directors of Mentor, a Siemens business, a leading industry personality, to provide us with an outlook for the global semiconductor industry!
Dr. Wally Rhines and I chatted about the global semiconductor and EDA industries, the Accellera Portable Stimulus Standard (PSS), and a host of other issues.
Semicon industry in 2018
First, how is Mentor predicting the global semiconductor industry to perform in 2018?
Dr. Rhines said: “The semiconductor industry performance for 2017 has been a pleasant surprise for most industry observers. The year is finally winding down, with the expectations for growth in the low 20s on the average – nearly 3-4 times as much as most observers had predicted only one year ago.
“Unit growth has consistently been 7-9 percent in recent years since the great recession. However, ASPs have been pretty consistently declining until 2017, when they were driven up mostly by memory prices for DRAMs and FLASH. Memory, once again, is behind the 2017 boom cycle. However, the rest of the IC business has also been relatively strong with growth in the higher single digits (7-8 percent), which is stronger than we have experienced in recent years.
“Memory prices are expected to soften as additional capacity comes on-line in 2018, especially as the year continues into the second half. However, the remainder of the non-memory semiconductor market should continue to have strong performance similar to 2017 (~7-8 percent) as the market fundamentals remain strong.
“Over the last several years, the semiconductor industry has experienced a wave of consolidations. I believe that we are between major waves of growth that are typical of the semiconductor industry. Historically, new semiconductor growth is ushered in by new applications that become possible when the cost per function, or some other new capability, makes the new application possible.
“In recent years, the cost per transistor for semiconductors has decreased more than 35 percent per year, just as it has, on average, for most of the last 60 years. It’s likely that continuation of this trend will, in fact, enable future waves of new semiconductor applications.
“Packaging, as well as package/chip simulation, continue to be important issues. Next generation simulation, verification, and analysis for multi-chip packaging configurations is now available. Now, designers of chips can intelligently analyze the packaging and pin-out configurations that will be most effective for cost and performance, based on a steady flow of data between the packaging engineer and the chip designer.”
EDA segment in 2018
And, how is the EDA segment looking in 2018?
According to Dr. Rhines, the EDA License and Maintenance is having a strong year in 2017. The annual growth is over 9 percent through the most recent four quarters with available data (Q3 2016 – Q2 2017).
He said: “The Semiconductor IP component of EDA achieved growth of nearly 17 percent overall, over the same period, as would be expected since Semiconductor IP is an important part of the supply chain for the broader semiconductor market.
“With expectations for the world economy and the overall semiconductor industry remaining strong, I expect semiconductor investment into design to also remain strong. EDA License and Maintenance is accounted for within the semiconductor company R&D expense budgets. Those budgets have a strong correlation to EDA License and Maintenance revenue. Therefore, I expect similarly strong growth in 2018.
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Sanjay Gupta, senior director of R&D, Mentor Emulation Division, Mentor, presented on the design verification trends and role of emulation.
Verification needs are expanding beyond traditional functional verification. SoC power analysis, coverage closure and DFT validations are critical. Vertical market segment focus is crucial as verification needs are different for different verticals. Verification teams are global teams. Veloce platform addresses the modern verification challenges.
Talking about the design trends, ~31 percent of designs use over 800 million gates and ~20 percent use over 500 million gates.Next, 72 percent of designs contain embedded processors, and 49 percent designs contain two or more processers, while 16 percent designs have eight or more processors.
As for ASIC/IC completion to the original schedule, 61 percent designs were behind schedule in 2014, which increased to 69 percent during 2016. The number of required ASIC/IC spins before production had become seven spins or more in 2016.
Regarding verification trends, as for more design engineers vs. verification engineers, design engineers were growing at CAGR 3.6 percent, while verification engineers were growing at CAGR 10.4 percent, from 2007-2016. The ASIC/IC verification engineers were spending 39 percent of their time at debugging, 22 percent each at creating test and running simulation, and testbench development, and 14 percent time in test planning.
SystemVerilog was a clear leader at the ASIC/IC verification language adoption, while Accelera UVM was a clear leader at the ASIC/IC testbench methodology adoption trends.
In power and coverage, 72 percent more designs wre actively managing power in 2016 as against 59 percent in 2007. Among the power intent trends, the UPF 2x was a clear leader among notations used to describe power intent. Functional coverage is just nearly on par with code coverage, followed by assertions and constrained-random simulation, as far as the ASIC/IC dynamic verification trends are concerned.
Challenges for verification include larger, more complex chips, as well as the increasing software content. Transistor count for select ICs will likely reach 15 billion gates by 2022.
Vertical segments are facing constant innovation. In networking, SDN emergence is driving complexity, size, and port count. There is an increased importance of software. Networking is driven by Big Data, cloud and mobility.
Safety is critical verification for automotive design. Veloce delivers the functional safety verification. Emulation has moved to virtualization with Veloce2. Data-center friendliness and enterprise-level usage are prime. Veloce Strato has accelerated and moved on to the application age, and has a vertical market focus.
Crystal chip is the brain of the Veloce emulation platform. A chip is designed exclusively for emulation: fast compile and efficient, full visibility. The chip, system and software are architected together to optimize the emulation capabilities and productivity. The Veloce Strato offers the lowest cost of ownership.
Veloce power app offers low-power verification at SoC level where power controls come from the application software, handles large SoC (RTL/Gate) with full visibility, performs complete verification (e.g. OS boot) and shows accurate power numbers based on real switching activity.
You can also do low power verification with Veloce. There is broad UPF 2.x support and UPF 3.0 support is planned by the end of 2017. Veloce coverage app has comprehensive SVA assertion support, SV functional coverage, code coverage, standard UCDB support and merged with simulation UCDB, and flow to enable XML merge with other platforms.
Anoop Saha, Mentor, did a presentation on Veloce vertical solutions at the Emulation Conference in Bangalore.
Veloce solutions are used across networking, storage, multimedia, mobile, CPU, automotive and military aeronautics. Veloce is structured around verticals to be segment focused, identify and address segment specific challenges, and identify gaps early on.
Veloce solutions are connecting the DUT to the external stimulus. iSolve speed adaptors connect real-life systems with the emulator. The Virtualab peripherals — VirtuaLab is the software representation of a speed adaptor. The Veloce transactor library – Veloce compatible verification IP. Transactors (VTL) to integrate with users UVM testbench and lower the abstraction layer.
In networking, for instance, the network switch is driving complexity. There is shift to SDN driving chip size and high port counts. Next, 5G is also driving new technology
and standards. Veloce for networking is offering solutions on top of core emulation platform. The verification flow is expanding to include Lab system validation. As of now, SDN is said to be creating a methodology shift. Mentor is said to be the only vendor with a complete offering.
Verification can no longer ignore firmware. Emulation enables earlier firmware development. Software debug is done with Codelink. The Veloce power app is used for broad base analysis. Veloce also offers complete solution for multimedia.
There has also been an industry shift from spec to benchmark. Many new apps target benchmarks for mobile devices. Examples are the AnTuTu benchmark, Geekbench for CPU and GPU benchmark, GFXBench, a GPU graphics centric benchmark, Android smartphone and tablet benchmark, etc.
Mentor, A Siemens Business, held a one-day conference on emulation in Bangalore and Hyderabad. I am thankful to my friends, Veeresh Shetty and Montu Makadia, for helping me attend this conference.
Shankar Bhat, Director, Engineering, Qualcomm India Pvt Ltd, in his keynote, titled 5G and Beyond – Emulation Challenges, said that a shrinking time to market, and stringent DPPM requirements drive the future of verification. Verification scope will extend from just hardware verification to software enablement. The emulation footprint in verification will significantly improve.
He added that mobile has been making a leap every 10 years. Today, it is redefining everything by creating the connectivity fabric for everything and bringing new levels of on-device intelligence. The long-term vision is to transform everything through intelligent connected platforms.
There is likely to be $12 trillion worth of 5G-related goods and services in 2035. Mobile is driving technology nodes and innovation. Verification focus has expanded from functionality to coverage to performance, on to power to yield and DPPM (defective parts per million). There is an over 30 percent NRE (non-recurring engineering) cost on design verification and emulation.
Post silicon validation and software testing time has been shirking. The post silicon test content, and software need to be fully validated before silicon arrival. Here, emulation plays a significant role in software readiness.
Regarding the key verification challenges, these are:
* Increased complexity: Test counts have increased, and there are much complex power structure and power domains. Also, there are challenging performance scenarios.
* Long simulation time: Simulator efficiency is not scaled. It is not able to complete all verification before tape out.
* Software enablement: Software expects fully verified design and settings.
* Customer enablement and DPPM reduction.
Emulation has several advantages. It has significantly faster run time, 1000X+ compared to simulation. It mimics hardware and closure to silicon. There is quick test portability between platforms.
Emulation will play significant role in design qualification, in both pre- and post-silicon phases. Software enablement will help achieve faster time-to-market. The challenges faced by emulation are a high NRE cost, limited debug capability, compilation time is still high, there are limited power verification capabilities. There are higher hardware costs as well in gate level verification, as it is difficult to fit the full SoC into the FPGA.
Emulation will play a significant role in hardware and software co-simulation. Tool portability is key. Verification will use multiple tools and flow. There will be the interpretability of tests, and data will be critical. EDA companies need to develop cost-effective emulation platforms.
Earlier, welcoming the audience, Ruchir Dixit, Technical Director-India, Mentor, said that the status quo is uncomfortable. He compared the cost of laying a metro network in Bangalore, which can cost between Rs. 8,000-14,000 crores. For emulation, while, it was expensive, it was about time that developers got used to it.
Artificial Machines enables smart product innovation with strategic partnerships with Mentor Graphics and Qualcomm
There are a lot of things in electronics manufacturing happening across, in China, Japan, Korea and Taiwan. When that activity in electronics manufacturing happens in India, it is a matter of great pride for the country. The company bringing pride to India is the Pune-based Artificial Machines.
Artificial Machines was founded in April 2008. Headquartered in Pune, India, it has sales office on Wall Street, New York, USA. It is focusing on IoT, smart machine design, and artificial intelligence (AI).
Manish Buttan, CEO, Artificial Machines, said: “We are one of the oldest IoT companies. We work with automotive and electronics companies. The HAZE platform was developed in 2015. We are focused on converting traders to makers. We are designing over 20 product lines in consumer electronics.
“We are currently building the TV platform for Videocon and the Videocon Aryabot 2 AC, which is in progress right now. For Eureka Forbes, we have done a few water purifiers. We are also working on a few products for Tata Housing including a door phone, smart lock, smart camera, fire safety, and several products for Godrej & Boyce.
“We are a design house, and designers at the PCB level. We make everything in India. The idea is to develop the IP. We can connect anything built on the HAZE platform. For example, a video doorphone has built-in VoIP. We are lowering the automation costs as well.”
What is HAZE?
Artificial Machines has developed the HAZE platform. The HAZE platform is not just an IoT platform. It is a smart product innovation platform.
“We will develop artificial intelligence for cars by 2018. We will also build the entire electronics for the cars,” Buttan added.
Artificial Machines has partnered some of the largest OEMs in India that have licensed the HAZE platform to develop a range of products in India. Buttan said: “As of today, we have five licensees – Eureka Forbes, Godrej & Boyce. Tata Housing, Usha International, and Videocon. Their products will soon show the ‘Powered by HAZE’ Logo.
“All HAZE Platform Intellectual Property belongs to Artificial Machines. Our customers are promoting the platform by adding our logo to their products. The HAZE License requires that the primary components be purchased through us. The HAZE IP is free to license for customers and we charge a subsidized customization fee for modify HAZE for their requirements. We are heading into a $20-$50 million turnover over the next five years.
“PCBs are being made in India. Also, in China. With Usha, we are doing smart fans, air coolers and lighting brands. With Godrej & Boyce we are doing refrigerators, ACs, smart washing machines, etc.
Over the years, Artificial Machines has participated in developing products such as the Mahindra XUV BlueSense App, Savant home automation System, Vidyo conference platform, Lifeshield home security system, Brookstone grill monitoring app / baby monitor app, and the Videocon Aryabot AC, which are in the market.
Products to be launched include a few water purifiers, smart refrigerator, and next-gen air conditioners. Products that will be completing this year include air coolers, smart lighting, Android TVs, Android refrigerators, video door phones, smart locks, smart cameras, fire safety equipment, and washing machines.
Roles of Mentor Graphics and Qualcomm
What role does Mentor Graphics play in all of this? Mentor Graphics came into the picture, and gave Artificial Machines their tools. Mentor PCB development and validation process involves over 75 processes of reliability. Mentor Graphics has strategically partnered with Artificial Machines and invested EDA tools worth $15 million.
This makes Artificial Machines have the world’s best design tools in PCB design, embedded, automotive, chip design, and manufacturing validation.
Buttan said: “We have a strategic partnership with Mentor Graphics. All of the tools are available to traders. We also have an agreement with Qualcomm. Each OEM can innovate their ideas.”
Qualcomm has been very supportive with the Snapdragon chip licensing to Artificial Machines. Microchip is a premium partner for low-and mid-segment processors. All of these give Artificial Machines some of the widest range of processors and platforms to work with – Bare Metal, Linux and Android. This makes it easy for customers to build Android hardware with HAZE licensing.
Artificial Machines also works closely with several large global manufacturers. Having in-house Valor manufacturing validation tools allows it to provide pre-validated hardware for manufacturing.
Thanks to Mentor Graphics for introducing me to this company.
Mentor Graphics Corp. recently announced the Veloce StratoM emulation platform.
The Veloce Strato platform is Mentor’s third generation data-center friendly emulation platform. It is said to be the only emulation platform with full scalability across both software and hardware. Mentor is also launching the Veloce StratoM high-capacity emulator and Veloce Strato OS enterprise-level operating system.
So, how is the Veloce StratoM platform suitable for data centers than previous version?
According to Montu Makadia, one of the worldwide ATM – Emulation experts at Mentor Graphics ; with the Veloce StratoM emulator, there are no major changes to the lab requirements.
There is the same footprint, lower total power consumption, and lower total cooling requirement (air-cooled, air extraction from top). There is an added flexibility on the door and panel (new in Veloce Strato) that makes system maintenance easier.
The Veloce Strato Platform plans for highest effective capacity (up to 15BG) available. Does it really go up to 15BG? If yes, where are the test results?
According to a Mentor Graphics’ spokesman, as of now, no test results are required. Connecting emulators via a sophisticated connection method is common for Veloce. In this case, the Veloce Strato Link can be used to connect multiple Veloce StratoM emulators to reach 15BG capacity.
“We have installations at companies that will not allow us to talk about them by name. These are large, multinational companies with very advanced verification and validation requirements. The installations have gone extremely well and deployment is underway and happening without issue,” the spokesman added.
Mentor is saying there will be a roadmap to 15BG over five years and beyond? What if others come up with a faster system in between?
The spokesperson said: “We can’t predict what other emulation vendors will do in the next five years. We have done our competitive research and believe that we are uniquely positioned to have, both, the largest capacity available in 2021, as well as the emulation platform with the highest RoI.”
Finally, how is the Veloce Strato OS enterprise-level operating system a step above the earlier OS?
The Veloce Strato OS is the centerpiece of the technology for the overall Veloce architecture. The Veloce operating system basically enables three things: The first is the primary core compiler flow. When you use an emulator, you need to compile the design. You synthesize and partition, and move from an RTL/netlist to something that is mapped to the hardware (P&R).
The Veloce Strato OS delivers an integrated, fully automated, single step compilation flow with about 3x faster compilation time and with a 100 percent compile success rate. The compilation time and a 100 percent compile success is one of the key differentiators compared to an FPGA-based emulator.
The OS enables all the use models of verification with a unified compilation, runtime and debug flow. That includes traditional ICE (physical targets-based stimulus), the other virtual use models (SW device models) and testbench acceleration (SW test benches, UVM, SV, SC, TLM, etc.).
The third unique attribute is advanced debug. In addition to the waveform support, it supports Livestream to view a set of important signals, key register for long emulation runs as tests are progressing and Veloce’s unique ‘save and restore’ replay to restore emulation sessions instantaneously at a specified time point for detailed debug activities without re-running the emulation from the beginning.
Here is the concluding part of my discussion with Dr. Walden C. Rhines, chairman and CEO, Mentor Graphics.
Getting billion-gate design correct
In EDA, is there now some chance of getting a billion-gate design correct on first pass?
Dr. Rhines said: “Absolutely! Today’s methodology is up to the task and customers have already reported “billion gate equivalent” designs, i.e., 4 billion transistor, correct on first pass. Correct logic is a much easier challenge than full production readiness on first pass!
“Achieving targeted power dissipation and timing has been more of a challenge but that’s where recent tool improvements are having their greatest impact. Almost all designs of this size now go through exhaustive verification, including power analysis, using emulation. That change in methodology has increased the cycles of verification by more than three orders of magnitude.
“Beyond simply achieving functional silicon with acceptable power and timing, more and more companies are now using EDA tools to assure a rapid ramp to high yield in production. This requires use of a whole new generation of “design for test” tools directed at defect driven yield analysis.
“By our measures, some of the top semiconductor companies analyze more than 500,000 defective parts every day to identify design and process problems.”
Standardization of SoC verification flow
Next, what is the status of the standardization of SoC verification flow today?
He said that Mentor Graphics has long worked on providing leading functional verification products. “We are doubling down on perfecting tools that are part of an enterprise platform where common testbench stimulus, verification IP, and standard verification languages can be used up and down the tool chain. However, the flow belongs to the customer.
“We do not try to enforce a “standard verification flow”. We are happy to accommodate unique customer needs and trust our customer to know the unique requirements of their own markets.
It would be interesting to know what has been happening regarding the coverage and power across all aspects of verification?
According to Dr. Rhines, power management debug has permeated all aspects of traditional HDL based verification. For large SoCs, debugging power-management related problems is a very difficult task. Power is managed wholly or in part by software. Increasingly, validation of power managed designs, including power estimation, requires hardware accelerated solutions such as emulation and prototypes.
New releases of the UPF standard include lots of new capabilities that help verify power usage but that do require additional effort to analyze. Examples include dynamic power related messages, automatic power specific assertion generation and support for the entire flow from simulation through emulation and prototypes.
In addition, lots of designs now use new tools for power management verification, static analysis, rule based power checks and power-aware logic equivalence checking.
Similarly, what is happening in active power management today?
He said that active power management creates the need for functional verification. Traditionally, power has been managed via clock gating, power gating and dynamic voltage and frequency scaling.
The first two methods (clock and power gating) directly impact functionality necessitating the need for things like isolation with clamp values on inputs or outputs to a power gated block of logic, retention registers and gating logic for clocks, as well as the associated control signals or registers and the state machines, which manage the transitions from one state to another.
Verification of the active power management logic and control states necessitates the need for UPF support in verification solutions. The challenge in debugging power management issues drives the value in dynamic checks to ensure valid power down and up sequences, save/restore or resetting/write-before-read behavior of registers in power domains and proper activation and de-activation of isolation logic values.
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