Mentor Graphics

Silicon lifecycle challenges and expanding role of test: ITC India 2020

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Brady Benware, VP & GM Silicon Lifecycle Solutions, Mentor, A Siemens Business, delivered a keynote on “Silicon Lifecycle Challenges and the Expanding Role of Test”, at the ongoing ITC India 2020.

There is a new context for ICs. It is creating tremendous social benefit. The global smart cities market is expanding at a CAGR of 19 percent. It is expected to reach $189.5 billion in 2023. There will be challenges involved. Traditional challenges will continue, such as 5nm to 3nm change. There is system technology co-optimization (STCO) as well.

Worldwide fabless semiconductor company funding has been dominated by AI apps. The others are communications/high speed and 5G, silicon photonics, MEMS and sensors, etc. There is the Cerebras wafer scale engine for AI apps.

More of human experience and wellness depends today on electronics. We are getting to a situations where we no longer look at them as an inconvenience. Functional safety in IC designs is increasing. IC designs with functional safety has increased from 48 percent in 2016 to 59 percent in 2018. Security concerns are also increasing. Vulnerabilities also have serious financial ramifications, even when they are never exploited.

There are two test innovation vectors to meet full lifecycle requirements. There is greater complexity as more design-for-test occurs, and increasing lifecycle requirements as design for more-than-test happens. There are also growing challenges with static test bandwidth allocation. Programmable bandwidth eliminates the trade-off. Adapter nodes decouple core and top DFT requirements. It enables additional compression. More gates and pins drive the new test access requirements.

Brady Benware.

High bandwidth scan test can be done for leveraging high speed IOs (SERDES). Comprehensive safety subsystems are also available. You can detect and respond to degradations. Advanced automotive features require faster testing. More efficient LBIST is needed for lifecycle management.

Security and optimization challenges require more than structural monitoring. There are functional monitoring areas as well, such as hardware or software bugs, malicious attacks, use-case and workload surprises.

Siemens has acquired UltraSOC, to be part of Mentor’s Tessent product family, for silicon lifecycle management. Embedded analytics is a separate subsystem today. There are non-intrusive, hardware-based analytics, and provide broad visibility to analyze software and system, everywhere in the SoC. You can design for function, and augment for deployment. There is lifecycle resilience and optimization.

The test community is the right community to tackle the lifecycle challenges. It can innovate within the expanded role. You need pass/fail and insightful data, structural risks and functional risks, and standalone and statistical. There are exciting times ahead with the expanding role of test.

Predicting semiconductor business trends after Moore’s law: Dr. Wally Rhines

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Predicting Semiconductor Business Trends After Moore’s Law is a book written by Dr. Walden C. Rhines, CEO, Rhines Consultants and CEO Emeritus, Siemens PLM Software and Mentor, a Siemens Business. It is a SemiWiki project.

In the book, he begins with how the semiconductor learning curve provides a roadmap. According to him, Texas Instruments’ (TI) unique approach for semiconductors lay in the use of the learning curve to drive a pricing strategy early in the life of a new component.

Dr. Wally Rhines

While Moore’s Law is becoming obsolete, the learning curve will never be. Instead, the cumulative number of transistors produced will stop moving so quickly to the right on the logarithmic scale. Then, the prices will not decrease as rapidly, as they have in the past. The visible effect of improved learning will diminish.

A graph shows how the cumulative unit volume of transistors used in memory components is increasing much faster than unit volume of transistors in other types of chips.

He says that if the EDA industry doesn’t keep its learning curve parallel to the semiconductor industry learning curve, the cost of EDA software as a percent of semiconductor revenue would increase. There would have to be cost reductions elsewhere in the semiconductor supply chain to offset it.

About Moore’s Law
Dr. Rhines goes on to say that ‘Moore’s Law’ has been extrapolated for more than 50 years. It is not a ‘law’. It is an empirical observation that became self-fulfilling after some adjustments. He cites revisions by Gordon Moore to the Moore’s Law, at least twice, in 1975 and 1997. And, later, in 2003. These repeated revisions affirm that “Moore’s Law” was not actually a law of nature, but an interesting, if temporary, phenomenon.

Dr. Rhines says that today, many people worry that the inevitable end of Moore’s Law will leave us with a stagnant semiconductor industry, with no guideposts to drive new silicon technology directions. Fortunately, these people need not worry. The learning curve is valid forever (when measured in constant currency, corrected for governmentally-induced inflation) as long as free market economics prevail, i.e., negligible trade barriers, no regulatory price controls, etc.

In 1825, Benjamin Gompertz proposed a mathematical model for time series that looks like an ‘S-curve’. The Gompertz Curve has been used for a variety of time dependent models, including the growth of tumors, population growth and financial market evolution.

The actual rate of growth of shipments of silicon transistors is predicted to increase until about 2038. At that time, the Gompertz Curve suggests that the increase in the rate of growth will become zero, and the rate of increase will be less each year, until we reach saturation, sometime in the 2050 or 2060 timeframe. By then, we should have developed lots of alternatives.

In another chapter, there is a graph detailing how the top 50 semiconductor companies’ share of the market has decreased 10 points in 10 years. He adds that it’s difficult for semiconductor companies to re-invent themselves as new growth markets emerge. Large semiconductor companies tend to grow at about the overall semiconductor market average growth rate, while the new entrants grow much faster, albeit from a smaller revenue base. Gradually, these small companies climb the ranks on their way to top 10.

Elsewhere, he talks about how EDA has evolved to an extent that the complex chips with tens of billions of transistors frequently produce first pass functional prototypes from the manufacturer.

International semiconductor competition
Later, he touches upon the international semiconductor competition. Semiconductor industry evolution was largely a US phenomenon. Japan became a significant competitor, especially in the late 1970s, and early 1980s. Then came Korea. Next, there was the evolution of worldwide leadership in the silicon foundry business by Taiwan, which is truly remarkable. TSMC also recognized the value of being a dedicated foundry, with no products of its own to compete with its customers.

Despite China’s rise as the world’s largest assembler of consumer electronic equipment, the Chinese semiconductor industry has evolved slowly. The largest Chinese semiconductor foundry, SMIC, is said to be two technology nodes behind TSMC in manufacturing capability, as of 2019. The Chinese government is dedicated to changing this situation.

China has done the expected. They have focused upon developing non-US capabilities for all their components. Since China buys more than 50% of all semiconductor components in the world, and uses more than 15% of the world’s semiconductor supply in equipment designed by Chinese companies, this is now a big problem for the US semiconductor industry. It is probably not reversible.

While China’s direction is not likely to change, we still have the possibility of convincing the rest of the world that the US can be treated as a reliable supplier. Hopefully, there will be policies articulated by the US that convey that confidence, and restore the US position as a leader in free trade.

AI, edge computing and 5G
Towards the end of this engrossing book, Dr. Rhines touches upon artificial intelligence (AI). He says, and I agree, that AI is not a new technology. Here is the cover of High Technology magazine in July 1986. Dr. Rhines is the person on the left, and George Heilmeier, former head of DARPA, is on the right. “We tried hard in the 1980s, but the infrastructure had not developed to a level where AI would provide profitable opportunities,” he added.

Today we have overcome all these limitations. AI and ML have taken on a life of their own. They have become limited, however, by the processing power available. Traditional von Neuman general purpose computing architectures are inadequate to handle the complex AI algorithms. The result: a new generation of computer architecture is evolving.

On edge computing, he says that the edge nodes will require mixed technologies. Simulating digital logic connected to analog, RF and other technologies is not easy. A whole new family of EDA tools is required.

One of the great opportunities for the semiconductor industry is the increased number of base stations required to support the infrastructure of 5G and the larger number of antennas in a phone. It’s likely that about a dozen companies will lead the way in supplying the complex image processing subsystems required for autonomous vehicles.

May I take this opportunity to thank Dr. Wally Rhines for sending me a copy of this superb book. Friends, you can read this too on SemiWiki. It’s really a brilliant read! Enjoy! 🙂

Trends that shook the world 2010-2019!

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You’re a good soldier, choosing your battles
Pick yourself up and dust yourself off and back in the saddle
You’re on the front line, everyone’s watching
You know it’s serious we’re getting closer, this isn’t over
The pressure is on, you feel it, but you’ve got it all, believe it
When you fall get up oh oh, and if you fall get up oh oh
Tsamina mina zangalewa, ’cause this is Africa
Tsamina mina eh eh, Waka waka eh eh
Tsamina mina zangalewa, this time for Africa! 😉
By Shakira, from World Cup Soccer, 2010! 😉

We have come to the end of a very interesting decade! While it was not so engrossing as the 2000s, there were several developments worth noting. But first, let me take you all back to March 15, 2016!

Around 2.30am, I was in the bathroom. All of a sudden, my legs simply gave way! I didn’t know what was happening to me. Also, there was a sudden increase of chest pain! I clung on to the bathroom door, and somehow crawled to my bedroom. There, I tried to wake up my wife! By the time she was up, I was lying down on the floor, sweating heavily, and blacking out! Mind you, I never drink!

My wife and brother rushed me to Sodhi Nursing Home, where the doctor diagnosed me with a severe heart attack. He recommended that I be immediately taken to Action Balaji Hospital. There, the doctors took one look at me, and rushed me to the operation theater. I was later told that I had a massive heart attack, with 99 percent blockage in my veins. I don’t even know what the doctors did, but here, I am before you, presenting my state! This is a trend, I never even imagined, would happen to me!

Given here are some of the global technology trends and happenings that shook the world during the last decade:

Mobile Internet, Bluetooth and Wi-Fi
Back in late 2000, at the ITU World Telecom event in Hong Kong, the first mobile phones with Internet browsing were being touted. Back then, mobile Internet was all the rage! As, were 3G and Bluetooth! This was the 3G technology based on W-CDMA and also, TD-SCDMA. Those were also the days when ‘WAP is CRAP’ made more headlines, and bore the brunt of many ‘telecom jokes’! Today, we can’t even imagine a life without the mobile Internet! And, we are greatly bothered if we can’t access a page on our mobiles!!

In early 2002, I wrote an article for Electronics Business News Asia (EBN Asia), Singapore, on Bluetooth, which was still trying to find its bearings. I can’t locate that article anymore! Some of the comments are worth remembering. One comment was whether Bluetooth and Wi-Fi could co-exist! Today, the world is into launching Wi-Fi 6 and Bluetooth 5.1!

March 2011, we saw the Japanese earthquake – The Japanese earthquake and tsunami stunned the global electronics and semiconductor industries!

Tsunami and earthquake
The preliminary assessment of Texas Instruments’ manufacturing sites in Japan revealed that the fab in Miho suffered substantial damage during the earthquake. Teams are working to reinstate production in stages, reaching full production in mid-July. TI’s fab in Aizu-Wakamatsu was damaged, but was being re-started with full production estimated by mid-April. TI’s third fab in Hiji was undamaged and running at normal capacity.

Sony Group Operations were said to have been affected by the Pacific coast of Tohoku earthquake, tsunami and related power outages. For Elpida, the Hiroshima Plant suffered little impact as it is located in Hiroshima in the southwest of Japan, However, the Akita Elpida memory plant is not in operation as of the time of the announcement due to power shut down caused by the earthquake, and it is hoped that normal business will resume when the power returns.

Tsunami hits Japan!

Iwate Toshiba Electronics did not report any casualties, but as of March 15, there was power lost, with limited partial recovery to start from March 13. As of March 15, 12:00pm, seven factories out of 22 of the Renesas Group’s factories in Japan temporarily shut down production.

The Shin-Etsu group reported that as of 1pm, March 15 (Japan Time), necessary inspections were carried out at Shin-Etsu Chemical Kashima Plant (Kamisu, Ibaraki Prefecture) and Shin-Etsu Handotai Shirakawa Plant (Nishigo Village, Fukushima Prefecture), both of which were out of operations.

Mitsui Chemicals Group reported the effects of the Kanto-Tohoku earthquake on its operations. The operations at the Kashima Works (Kamisu City, Ibaraki Prefecture), was suspended since the earthquake. Operations were resumed after assessment of damage by the earthquake and tsunami.

At its Ichihara Works (Ichihara, Chiba Prefecture), production at the ethylene plants was according to schedule. The operations at Mitsui DuPont Polychemicals and Chiba Phenol plants were suspended since the earthquake.

At the Mobara Branch Factory (Mobara City, Chiba Prefecture), operations at acrylamide and paint toner binder resin plants have been suspended since the earthquake. After assessing effect of scheduled “rolling” blackout, operations were resumed.

USB 3.0 also became widely available, while 22nm chips entered mass production. Consumer-level robotics were also booming.

Birth of EVA
In May 2011, the Embedded Vision Alliance was born! Over 15 leading technology companies, came together in Oakland, USA, to ‘speed up the adoption of computer vision capabilities in electronic products.’ BDTI, Xilinx, and IMS Research initiated the EVA, and were joined by Analog Devices, Apical, Avnet Electronics, CEVA, CogniVue, Freescale, NVIDIA, National Instruments, Texas Instruments, Tokyo Electron Device, MathWorks, Ximea, and XMOS as the founding members.

Still in June 2011, June 8 happened to be World IPv6 Day. Google, Facebook, Yahoo!, Akamai and Limelight Networks were among some of the major global organizations offering content over IPv6 networks on a 24-hour test flight! World IPv6 Day’s goal is to motivate organizations — ISPs, hardware vendors, OS vendors, web companies, etc., to prepare their services for IPv6, as IPv4 addresses ran out! IPv6 was designed to succeed the IPv4.

End of Harry Potter, Steve Jobs
In July 2011, we saw the end of the spectacular Harry Potter movies! Right from the time Harry confronts Helena Ravenclaw or the ‘Grey Lady’, the Death Eaters attacking Hogwarts, the very brave resistance put up by the school inhabitants, led by Prof. Minerva McGonagall, the tragic death of Severus Snape at the hands of Voldemort and his pet snake, Nagini, and Snape’s final meeting with Harry, following which, Harry views Snape’s pensieve and learns about his love for Lily Potter, up to the time Harry enters the Forbidden Forest to meet his death! Or, was it Harry, or Voldemort, who dies? It’s all breath-taking!

October 2011, Steve Jobs, the master of the game, is gone! I first had a look at the Apple Mac, while at SBP Consultants & Engineers, back in 1988. I was surprised to find a computer that could do desktop publishing so well! By then, Jobs had gone out of Apple, fired by John Sculley, then Apple’s CEO, sometime in 1985. Jobs returned to Apple in 1996, a time when he had floated PIXAR and NeXT — the company Apple eventually bought, and returned Jobs to Apple. The rest is history!

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Trends in MEMS Testing

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MEMS has been driving innovation at the silicon level, and at the packaging and testing of devices. Given this scenario, it would be wise to estimate the evolution of MEMS devices, and how they are driving packaging and test strategies.

Stephen Whalley

Packaging and test strategies
Stephen Whalley, strategic advisor, SEMI-MEMS & Sensors Industry Group (SEMI-MSIG), said: “MEMS devices are the driving force in system innovation across multiple markets, such as smart transportation and vehicles, smart cities and buildings, smart agriculture, smart medical, and the Internet of Things, etc.

“This explosive growth in MEMS is also driving innovation at the silicon level, and consequently, in the packaging and testing of the devices. The vast majority of MEMS devices require a cavity of some sort, which can be categorized as vacuum, hermetic at various atmospheric conditions with inert gas, or open cavities that sense the surrounding environment (examples are acoustic devices and chemical sensing devices).

Allyson Hartzell

Allyson Hartzell, managing engineer, Veryst Engineering, elaborated: “Also, coupled in many packages are other die. Examples are ASICS and other MEMS devices. Innovative methods for creating the cavities by chip-to-chip solder and metallic bonding keep a ‘lid’ on the thermal budget of sensitive transistors on ASICs and other CMOS devices that are housed in the MEMS packaging.

“When it comes to standard packaging aspects, wire bonds and solder bumps are still popular options. Capping with sealing materials, such as glass and metals/solders are also used. TSVs are now commonplace.

“Wafer level packaging (WLP), over molding into a JEDEC configuration, SOIC, and high-reliability metal and ceramic packaging are varied, but also used in semiconductor packaging. Therefore, testing strategies have a starting point through the semiconductor industry.

“As packaging becomes smaller and smaller, the cavities are smaller, and so, their internal environment is harder to control. Thus, testing requires more steps than the electro-mechanical testing of yesteryear’s single chip inertial packaged devices. MEMS process development requires cavity environmental gas testing, as nano-liter cavities are not easily tested by earlier methods such as the residual gas analysis (RGA). RGA could go by the wayside in lieu of humidity and pressure sensors patterned into the nano cavities themselves.

“Traditional getters are no longer easily fitting into tiny cavities. MEMS process development includes getters patterned right into the cavities itself. Gettering in small cavities that are not vacuum cavities could be required to reduce the moisture that causes MEMS device drift.

“Yield and reliability testing strategies are different as the cavity size reduces, as more chips (including MEMS) are integrated into a package, and handling the tiny packages during testing to keep proper orientation, without mechanical shock exposure, has to be designed into the test protocol. Packaging with interposer type methods and TSVs can use fan-out test strategies, already developed in semiconductor testing, for testing in a format that mirrors WLP and JEDEC type package dimensions and solder balls.”

“Yet, for some parts, such as environmental sensors, using methods such as tape-on-reel must be vetted for adhesive outgassing that can tie up surface states and reduce sticking coefficients during the operation of the devices. Testing of environmental devices requires some controlled testing environments with analytical chemistry characterization methods incorporated into the test platform. The devices drive the test strategies, and cost is reduced if the standard packaging outlines and the electrical contacts are designed from the beginning.”

John Stabenow, director of Marketing at Tanner EDA, part of Mentor, a Siemens business, said: “Multi-MEMS devices, as part of system-in-package solutions, are becoming more main stream. SiP devices allow edge device designers a better plug-and-play opportunity for complex subsystems that include not just the sensing (MEMS) technology, but, as well as MCUs, RF and power management components in a single unit. The modular design of a SiP solution allows for faster time-to-market, and more predictable design outcomes.”

Mary Ann Maher, CEO and founder, SoftMEMS, noted: “Key issues for packaging and test are the need to support multiple sensors in the same package. IC-typical applications require multi-sensor fusion. MEMS on flexible substrates is driving new packages and test strategies. MEMS on flex must be tested under bending and flexing.”

Adrian Arcedera, senior VP, MEMS, Sensors & WB BGA Products, Amkor, elaborated: “The growth of MEMS devices — from automotive and industrial markets into the consumer market — drove the need for shorter package development time, and the steep ramp up to mass production, while continuing to require the management of packaging stresses to the MEMS structure. These market changes ushered the need for standard packaging platforms.”

Gerard John, senior director, Advanced Engineering, Amkor, added: “Test strategies change and evolve at the same rate as the packaging strategies. From a test perspective, the accuracy and performance of low-cost MEMS devices are coming close to those of expensive counterparts. This calls for test stimulus that can provide 10x higher accuracies than the device under test. To reduce the cost of test (CoT), test strategies include, increasing the sites tested in parallel, reducing the number of test insertions, and designing multi-functional stimulus.”

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Semiconductor design activity accelerating: Dr. Wally Rhines, Mentor

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Dr. Walden C. Rhines, CEO Emeritus, Mentor, a Siemens Business, is in Bangalore, India, at Mentor U2U India, 2019. He delivered the keynote during the day-long conference.

Dr. Walden C. Rhines.

Why is the semiconductor industry design activity accelerating? Dr. Rhines said that the acceleration of semiconductor revenue growth, in terms of the annual growth of ICs has been 2.8 percent in a 5-year CAGR from 2011-2016. It was 22.2 percent in 2017 and 2018E (estimated) is 15.5 percent, according to VLSI Research, Jan. 2019. There has been an acceleration in R&D investment, with semiconductor R&D spending touching 7.5 percent in 2018.

Memory prime driver
Fabless semiconductor venture capital investment by year, all rounds, has been $3,118 million in 2018 YTD (year to date). Memory was the primary driver of semiconductor growth in 2017. Memory is now almost 40 percent of IC revenue vs. 27 percent in 2016.

Memory average selling prices (ASPs) increased dramatically in 2017, and in H1 of 2018. Memory prices peaked in Q1, but are expected to decline in 2019. Negative memory ASP year-to-year growth in Q418 and forecast for next four quarters, with MOS logic at 6 percent, MOS memory at 57 percent, and analog devices at -8 percent. Memory unit volume now needs to grow faster than logic!

Memory now dominates transistors manufactured. 3D NAND allows memory to scale faster than logic or SoCs. Despite 55 percent revenue growth in 2017, the memory unit volume growth is below the long-term trend line. Will non-memory growth remain strong when memory ASPs decline?

New companies in semicon design
New companies are now entering the world of semiconductor design. Amazon has just become a chip maker. Bosch has opened a billion-dollar wafer fab. Google has built its first chip for machine learning. Facebook plans to build its own chips as part of hardware push.

The Internet has greater than 22 billion connections today. Of these, 81 percent of the connections are things. Things are growing at 15 percent CAGR, wireless mobile at 11 percent CAGR, and stationary/desktop at 5 percent CAGR.

The Industrial Internet and connected cities are 79 percent of the market today. Connected vehicles are showing the fastest growth. Connected homes are growing at CAGR 18 percent, connected vehicles at CAGR 23 percent, wearables at CAGR 21 percent, Industrial Internet at CAGR 21 percent, and
connected cities at CAGR 7 percent, as of the end of 2018.

Chinese investment growing
Chinese investment is now moving from manufacturing to design. The Chinese government’s incentives for semiconductor investment have been rising. The government-backed China IC Investment Fund is worth US$ 47.4 billion (Yuan 300 billion).

The China semiconductor initiative has accelerated new startup formation. IC design enterprises have gone up from 715 in 2015, to 1,380 in 2017. China’s fabless companies have also become much larger, from 479 enterprises in 2006 to 715 in 2015. And, this number is only rising.

China fabless semiconductor companies by market segment has 935 unique companies – who can be in multiple sub-segments. There are 961 companies in power devices, 267 in analog devices, 266 in MEMS/sensors, 260 companies are fab owners, while 209 are in RF devices. Interface chips have 179 companies, memory devices have 135, full custom devices have 124. Video compression has 82 companies, while vision processing/AI/ML has 35 and there are 34 photonics suppliers. All other categories (semi and system) have 1,325 companies.

Neuromorphic computing
Neuromorphic computing is said to be for the next wave of automation. The
Evolution of non-von Neumann computer architectures will improve processing speed, reduce power and integrate more memory.

Traditional Von Neumann computer architectures are not efficient for pattern recognition. Computer architectures are a long way from human brain pattern recognition and power dissipation. Large number of computer cycles are required to perform the same level of pattern recognition as the human brain.

Neural networks are a fundamental building block for AI-related machine learning. Today’s artificial intelligence scenario looks like this: in 2017, more than 300 million smartphones shipped with some form of neural-networking capabilities. In 2018, 800,000 AI accelerators were shipped to data centers. Every day, 700 million people use some form of smart personal assistant like an Amazon Echo or Apple’s Siri.

India’s strengths in AI
TheIndian industrial companies are among the early adopters of AI. Early adopters are defined by BCG as businesses that have fully implemented more than one AI use case in multiple industrial operations areas. India ranks third, at 19 percent, behind the USA, at 25 percent, and China, at 23 percent, respectively.

India’s design activity is accelerated by investment activity. There is the Semiconductor Fabless Accelerator Lab (SFAL), which the IESA launched in December 2018. It has investment by the Government of Karnataka. SFAL plans to accelerate 20 startups in the next three years, and 50 in next five years. It will support the existing fabless companies with a goal of at least 2-3 products out of the accelerator over the next two years.

There is also the Fabless Chip Design Incubator (FabCI), launched in 2018 by IIT Hyderabad. It is an incubator for fabless chip design startups. Funded by the Ministry of Electronics and IT, technology partners are Cadence Design and Mentor. Its goal is to incubate at least 50 ‘Make-in-India’ chip design companies.

IITs are supporting the AI education. IIT Hyderabad offers a Master’s degree in AI. It is adding a Bachelor’s program in AI during the 2019-20 academic year. IIT Kharagpur has a six-month AI certificate course. IIT Madras has the Robert Bosch Center for Data Science and Artificial Intelligence. India has a strong AI skillset, and ranks third, behind the USA and China.

There are two key requirements for brain-like pattern recognition — memory improvements and processor architecture improvements. In memory improvements, there are increased capacity, hierarchical memory, memory cell connectivity, and invariant memory. Processor architecture improvements have parallelism, error tolerance, continuous feedback and integration with memory.

Major wave of new ‘domain-specific’ architectures
There is the end of the Moore’s Law and faster, general-purpose computing, and a new golden age. Software-centric, modern scripting languages are interpreted, dynamically typed and re-use is encouraged. Hardware-centric, the only path left is domain-specific architectures. Just do a few tasks, but extremely well. The combination of software and hardware gives domain-specific languages and architectures.

Startups dominated by application specific architectures in the worldwide fabless company VC funding show AI and ML topping at $1,834 million between 2012-18. AI is NOT a new technology. It is a technology that arrived before its time, in 1986. (Dr. Rhines is among the heavyweights involved).

Reasons for AI adoption delay in the 1980s were lack of big data to analyze, as there was no Internet or IoT to collect sizable data sets. There was limited computing power, and limitation of traditional computer chip architectures. There was a need for more advanced algorithms. Besides, there was lack of ‘killer’ applications to make money! What’s different today? All of these limitations are going away.

24 fabless AI companies received VC funding in 2018. Some are AIMotive Gmbh, Beijing Intengine Tech, Hailo Technologies, Mythic, Syntiant and Xanadu Quantum Tech. Also, the early round China fabless funding passes the USA.

If you look at the domain-specific AI/deep learning controllers, there are 39 for vision/facial recognition, 9 for voice/speech/sound/pattern recognition. 17 are for autonomous driving/ADAS, three each for disease diagnosis AI and optical computing AI, 2 for smell/odor recognition, 23 for data center/cloud AI/HPC, 6 for unknown/stealth mode, 3 for space/military apps, 2 for cryptocurrency, 21 for edge computing, 4 for robotics/motion control/collision avoidance, 8 for deep learning training, and 1 for intelligent wireless control. Pattern recognition dominates the new AI designs.

Microsoft has developed custom deep neural network chip for HoloLens. HoloLens is an untethered mixed-reality device. It has local compute for low-latency (fully battery powered). It includes custom holographic processing unit (HPU), custom AI coprocessor, custom time-of-flight depth camera, four gray-scale cameras, IMU, other sensors, and infrared camera.

EMOSHAPE has developed an emotion processor unit (EPU), which has the capacity to feel, perceive or experience subjectively. Emoshape has developed its own CPU optimized to handle emotional data. The technology has the potential to change computer games, virtual reality and augmented reality applications, said Roberta Cozza, research director, Gartner.

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Global semicon industry likely to grow +4.4pc in 2019: Dr. Wally Rhines, Mentor

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Happy new year, to all of you. 🙂 And, it gets even better, having a discussion with Dr. Walden C. Rhines, CEO and Chairman of the Board of Directors of Mentor, A Siemens Company, on the global semiconductor industry trends for the year 2019.

Semiconductor industry in 2018, and 2019
First, I needed to know how did the global semiconductor industry performed last year? And, what is the way forward in 2019.

Dr. Walden C. Rhines.

Dr. Wally Rhines said: “2018 was another strong growth year for the global semiconductor. IC bookings for the first 10 months remain above 2017 levels and silicon area shipments for the last six quarters have also been above the trends line, with fourth quarter YoY growth 10 percent. And, IC revenues overall continue to have strong double-digit growth for 2018, with fourth quarter YoY growth of nearly 23 percent.

“However, analysts are expecting much more modest growth in 2019. Individual analyst predictions for growth in 2019 vary from -2 to +8 percent, with the average forecasts at +4.4 percent.

“Much of this is due to the softening memory market, along with concerns about tariffs, inflation and global trade war. While the rest of the IC business has been relatively strong with Samsung and Intel noting solid demand for ICs for servers and PCs, sentiment by senior managers of semiconductor companies is near a record low level. So, I’m not expecting much growth, if any, in 2019 and more likely a decline.

EDA in 2019
On the same note, how is the global EDA industry performing, and what’s the path in 2019?

He said: “Revenue growth of the EDA industry continues to be remarkably strong, fueled by new entrants into the IC design world, like networking companies (e.g. Google, Facebook, Amazon, Alibaba, etc.) and automotive system and Tier1 companies, as well as a plethora of new AI-driven fabless semiconductor start-ups. Design activity precedes semiconductor revenue growth so it would not be surprising to continue to see strong EDA company performance even with a weak semiconductor market in 2019.

“EDA venture funding has rebounded, reaching a 6-year high of $16.5M showing a renewed confidence in the future of EDA. The major companies all have sighted better than expected results. On the semiconductor side of EDA there seem to be more technology challenges than the industry has faced in a long time.

“Some of those include new compute architectures, the emergence of photonics, increased lithographic complexities involving EUV and other techniques, new and more complex packaging, massive increases in data, and the multiplication of sources of design data (often created according to differing standards).

“The challenges on the system side of EDA are multiplying as expected. It is becoming more difficult to be at the leading edge when designing end-products in silos. Embedded software, mechanical, PCB, packaging, electrical interconnect, networking (access to the intranet) and security are just a few of the domains that need to work closer together in a more integrated manner. The increasing complexity is also making each of the domains more challenging. This all pushes new materials and methodologies into each of the domains listed above.”

Five trends in semicon for 2019
I wanted to find out about the top five trends in semicon for 2019.

He said: “The top five semiconductor technology trends include:
* the ongoing ramp of next-generation technologies, led by Machine Learning, Artificial Intelligence and cloud, and SaaS demand on the datacenter,
* the roll-out of IoT – especially in manufacturing,
* 5G development,
* computing on the edge, and
*the increasing semiconductor content within electrical devices.”

Self-driving cars pushing boundaries of IC testing: Nilanjan Mukherjee, Mentor

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Nilanjan Mukherjee, Engineering director, Tessent, Mentor A Siemens Business, presented the opening keynote on day 2 of the ITC 2018, on self-driving cars and how they are pushing the boundaries of IC testing.

IMG_20180724_112645Automotive ICs will grow from 7.4 percent in 2017 to 9.3 percent by 2021. New entrants are attracted by new revenue opportunities. Leading auto makers are planning to launch self-driving cars, such as Tesla, GM, Hyundai, Renault-Nissan, Toyota, Volvo, etc., as per the Boston Consulting Group. According to McKinsey & Co., 57 percent of customers globally, trust self-driving cars.

Increasing detection capabilities require higher compute performance. Higher compute requirements are accelerating the process node requirements. For the next decade, the number of gates will double every 2 years. There will be 2x more compression every 2 years, just to maintain the test cost. There is a huge increase in transistor processing, and trends will continue with the future 5nm/3nm nodes. Further scaling will require density increase, in addition to the pitch scaling.

Test requirements ensure that semiconductor devices remain defect free. They should also ensure that any new defects are quickly detected throughout the device’s operational lifecycle. Low defective parts per billion – the implications of defective parts in automotive apps, are more severe than in consumer apps. The defect coverage should cover all circuitry.

More defects and lower DPPB require better coverage. There are complete defect excitation considerations. The defects are prioritized by their physical likelihood.

Automotive grade ATPG provides a complete set of critical area-based fault models for manufacturing tests. Cell-aware test benefits are well documented. Additional user–defined fault models (UDFM) are targeting inter-cell defects and interconnect bridges and open defects. We have to find ways to reduce the test time for analog parts.

Typically low coverage is 70-90 percent for analog parts. Fault simulation allows one to determine portions not being tested. There is a need to eliminate the manual FMEDA metric estimates that are required for ISO-26262. The fault simulator can report the metrics automatically, eliminating untolerated faults, and achieving higher ASIL rating.

There are multiple modes of in-system testing. Key-on tests have very little time budget. Limited functions are tested. Key-off tests see comprehensive testing. The budget is 10x times that of key-on tests. Finally, online tests are challenging. They are periodic and incremental.

Mission-mode controller is the in-system test controller. It automates communication between the test instruments and the service processor.

The new VersaPoint test point technology gives 2-4 percent SAF coverage vs. LBIST (logic built-in self test) test points. That’s 2X-3X reduction in test time at 90 percent coverage. It also reduces deterministic ATPG pattern counts by 2-4X.

VersaPoint test points with observation during shift helps in fast in-system logic monitoring. This helps on an average to reduce the test times by 3-4X.

Requirements for future in-system test solutions:
* Able to apply any type of test.
* Able to add, modify and update the in-system tests during the entire lifecycle of an IC.
* Minimal system memory and incremental data.

Programmable deterministic BIST for FuSa (functional safety) include two levels of highly compressed patterns. This reduces the memory required to store the patterns on the chip.

In the non-destructive memory BIST, there are traditional memory BIST constraints. Memory is tested in small bursts of activity by making sure that the original contents of the memory is restored after test.

Austemper acquisition by Siemens brings solutions across all areas. It is a completely functional safety solution. There is safety analysis, so you can design an automotive for safety. It also has safety verification, and multi-domain fault injection, providing evidence to achieve ASIL compliance.

Automotive ICs have redefined the standard for quality of manufacturing.

ITC India to address design, test, and yield challenges

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The forthcoming International Test Conference (ITC) will be held on July 22nd-24th, 2018, at the Radisson Blu Hotel in Marathalli, Bangalore.

I must thank Navin Bishnoi, General Chair, ITC India, and director, ASIC India Design Center, GLOBALFOUNDRIES, and Veeresh Shetty, senior marketing manager, Mentor, for apprising me of developments.

The second edition of the conference, it is the world’s premier event dedicated to the electronic test of devices, boards and systems. At ITC India, design, test, and yield professionals can confront challenges faced by the industry, and learn how these challenges are being addressed by the combined efforts of academia, design tool and equipment suppliers, designers, and test engineers. The ITC India is being run under the guidance of ITC USA, and is supported by the IEEE Bangalore Section and IESA.

NavinLet’s look at the test challenges that the conference seeks to address. Navin Bishnoi said:  “DFT, test and reliability domains are seeing a huge focus with the need of standard test practices for a variety of applications across communication, automotive, computing and industrial.

“In addition, the cost of implementation and testing continues to be challenged, asking designers to look at innovative ways to optimize test, without impacting quality. ITC India brings the best minds from academia, research and industry to share best practices to enable the standard DFT/Test practices for variety of applications with reduced cost and high quality.

“The conference covers sessions on emerging test needs for topics such as: artificial intelligence, automotive and IoT, hardware security, system test, analog and mixed signal test, yield learning, test analytics, test methodology, benchmarks, test standards, memory and 3D test, diagnosis, DFT architectures, functional- and software-based tests.”

Next, what is the focus on DFT architecture and DFT strategy in automotive and other devices with low-cost testing requirements?

He added: “Today’s automotive safety-critical chips need multiple in-system self-test modes, such as power-on self-test and repair, periodic in-field self-test during mission mode, advanced error correction solutions, redundancy, etc. The conference has numerous presentations on summarizing the implications of automotive test, reliability and functional safety on all aspects of the SoC lifecycle, while accelerating the time-to-market for automotive SoCs.

“There is a strong focus on understanding the increasing use of system-level tests to screen smartphone and notebook processors for manufacturing defects by taking an in-depth look at the limitations of state-of-the-art scan test methodology. In addition, there is continuous study in the fields of DFT, diagnosis, yield learning, and root cause analysis, which use machine learning algorithms for solving various problems.”

Trends in modelling
Let us also look at the the trends in modelling and the simulation of defects in analog circuits and their applications that the conference seeks to address.

Bishnoi said that digital circuits have now evolved to standardize fault modeling and simulation. However, analog circuits have work in progress to look at new methods for modeling and simulating different types of faults using a mixed-signal fault injection methodology.

“Modeling defects in analog circuit use transient analyses that leverage different methods to inject faults. This is critical for today’s use case applications, like automotive, sensors, and industrial, which has significant analog components in the SoC. One of the trends that will be addressed in the conference is the layout-based fault modelling that is in fact a statistical analysis of process defects.

Now, to the directions made in advanced packaging technology. What’s the road ahead?

Bishnoi added: “Packaging technology has exploded with complexity in recent times for need of stacked dies, which involves change in processes, materials, equipment, as well as in the SoC implementation and sign-off. Advanced packaging enables small form-factor chips, with high-speed functionality for consumer market.

And, how are challenges in analog loopback testing for RF transceivers being addressed?

He said: “The main challenge in the implementation of loopback testing for RF transceivers is distinguishing the non-linearity effects of Rx and Tx, performance of channels during parallel testing, as well as coupling effects. Various test solutions will be discussed during the conference to address the challenges of an analog loopback testing of RF transceivers. Solutions employing the BiST techniques to have a quick TAT during manufacturing test will also be discussed.”

For those unaware, BiST or the built-in self-test, is a design technique in which parts of a circuit are used to test the circuit itself.

Finally, which version of the conference is this? Are we going to see regular ones? Bishnoi noted: “This is the second edition of the conference. We went through rigorous analysis and discussions with global leaders about the frequency and venue of the conference. It was decided to keep it annually (with the amount of growth in test/reliability space), as well as to keep it in Bangalore for the first 5 years, before we review it again to check if we should take it to other cities in India.

“The conference includes four keynotes from visionary leaders from Synopsys, Tessolve, Intel and Mentor Graphics, an exciting panel discussion on Fault Tolerance or Fault In-tolerance, as well as a variety of technical sessions and exhibits/demos from sponsors. It also has a dedicated day (on Sunday) for tutorials on six topics covering automotive, analog test, IEEE standards, machine learning in-test, system-level test and security.”

I will be present at ITC India 2018 in Bangalore, and look forward to meeting many of you, the attendees, as well! 🙂

Mentor-THE GAIN to boost India’s ESDM startup ecosystem

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Mentor, a Siemens business, has announced a strategic collaboration program with THE GAIN (The Global Accelerator for Innovation Network) – a technology accelerator company, focused on product engineering IP startups.

MentorBoth organizations will work with innovative Indian startups to accelerate, develop and customize IP to address domestic and international markets. They will focus on accelerating India’s product engineering IP ecosystem by helping companies in the early stages of entrepreneurship.

Established to advance the ESDM (electronics system design and manufacturing) ecosystem in India, the collaboration’s goal is to foster excellence in the early stages of startup companies. Both will work closely with the startups and entrepreneurs looking to establish and launch companies in the product engineering space, with a special focus on engaging with startups in the early phase of entrepreneurship.

“Mentor has established an outstanding track record of supporting, developing and accelerating startup ecosystems, both in India and across the globe,” said Raghu Panicker, Mentor’s country sales director for India. ”Through this strategic collaboration, we look forward to further accelerating the India startup ecosystem by working closely with promising product companies to make them successful.”

“India’s ESDM ecosystem is on a growth trajectory thanks to the ‘Make in India’ focus by the Indian government,” said Poornima Shenoy, CEO of THE GAIN.

“This collaboration with Mentor, a global technology leader, will have distinct benefits to startups looking to grow and succeed. It is our shared vision to collaborate and support highly successful startups in India who deliver innovative products. We are looking at accelerating the growth of at least 30 companies in the next three years.”

Outlining the specific steps Mentor-GAIN will be taking to help India’s product engineering IP ecosystem, she said: “At THE GAIN, we are looking to “excellerate” no more than five to seven start-ups per year. This is after a multi-tier rigorous selection process. Our entrepreneurs are often with deep industry knowledge and experience, who need a lead time of two-three years to prove the business and product viability.

“Tools are amongst the highest overheads in this journey. Here, the role of companies like Mentor, would be crucial. They have use cases, knowledge of decades and special schemes for entrepreneurs. This provides the right balance between cost and success. They also have leaders who understand and ‘walk the talk’.

“India needs to have more success stories with IP companies. We are looking at product engineering as a step in that direction. It is necessary for us to accelerate growth by productizing IP and leveraging global partnerships. It is not about overnight success, but about long-time multiplier returns. Our country and the industry needs to move in that direction.

“This is a unique partnership where both partners understand what works and what are the factors relevant to success.”

Justifying innovativeness
How does one justify ‘innovativeness’, when the two entities will support startups with innovative products?

Shenoy added: “It is a global race for innovation. We are looking for companies for the development of products, services, and applications related, to smart living and industry 4.0. India is a big market, but one, which is hugely price-sensitive.

“Our focus is on the B2B space and how soon can we get solutions out into the market in these areas. Innovation can save you money, help the environment and widen your market base. It could address niche segments and verticals. We are seeing interest from start-ups in other geographies to address this vibrant and dynamic marketplace. Global solution providers, like Mentor, function seamlessly across borders.

“At THE GAIN, we partner with innovative entrepreneurs by providing them with access to funding, active mentoring and to business. We can move to the next rung if they create MVP and validate it with their target customer base. This is a key area where they need assistance.”

Old wine! New bottle?
Finally, hasn’t this exercise been tried before? How are they confident about its success?

Shenoy said: “Every partnership is the start of a new beginning. It is only when we try that we can succeed. We are sure that as we embark on this journey on building the ecosystem and providing a platform for the Indian startups , we will learn and grow.

“We might slip up at times, but that is the beauty of a partnership. We learn together! In India, we have hardly seen any focus on this vertical. This understanding is a step in the right direction and a vital link to future success.”

Expressing his opinion on what Mentor is gaining out of this partnership, Raghu Panicker of Mentor, elaborated: “Mentor gains access to start-ups in the ideation stage itself. Mentor can, then, nurture them, and help start-ups with technologies in the areas of chips and system design. Start-ups are usually open to looking at new technologies.”

THE GAIN is a technology accelerator headquartered at Bangalore and founded by BV Naidu, former STPI director-turned-entrepreneur. The organization focuses on accelerating early-stage companies through access to funding, access to active mentoring and access to businesses.

Friends, if this interests you, please contact either Ms Poornima Shenoy at The GAIN or Raghu Panicker at Mentor. Best of luck!

MOS memory investors, China to correct DRAM imbalance

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penn1According to an IC Insights report, the 47 percent full-year 2017 jump in the price-per-bit of DRAM was the largest annual increase since 1978, surpassing the previous high of 45 percent registered 30 years ago in 1988! This sounds interesting!

Are the rising DRAM prices aiding startup Chinese competitors? Are major DRAM suppliers somehow stunting global DRAM demand?

Dr. Walden C. Rhines, president and CEO, Mentor Graphics, a Siemens Business, said: “The DRAM business has always gone through cycles of imbalance between supply and demand. Growth of demand in the last 18 months has been stronger than growth of supply.

“Substantial investments in 2017 by the MOS (metal-oxide semiconductor) memory producers, as well as the addition of China to the supply chain, will correct this imbalance late this year or, at the latest, early next year.”

The DRAM price-per-Gb has been on a steep rise. To this, Dr. Rhines said: “It is a commodity, although there are many types of specialty DRAMs emerging. Because DRAMs are viewed by customers as a near-commodity, the price is heavily influenced by the availability of supply. Supply has been very tight during the last 18 months.

Malcolm Penn, chairman and CEO, Future Horizons, UK, added, “This is supply and demand, pure text-book economics.”

Are the rising DRAM prices opening the door for startup Chinese competitors?

Dr. Rhines noted: “Chinese competitors made their decision to invest in DRAM capacity long before the recent strengthening of demand in the balance of supply and demand. Of course, higher, or stable, pricing may make it easier for new producers to absorb the costs of ramping up new capacity and developing experience with a new technology.”

Malcolm Penn agreed: “Potentially yes, and to anyone else. Coca Cola were contemplating building DRAMs in the 1990s. DSRAM market boom, again, pure text-book economics. Whether or not they succeed is an entirely different matter. If the Chinese do enter the market, can they then survive the inevitable downturn and cycles? That remains to be seen!”

Can the startup Chinese DRAM producers field any competitive product soon? Dr. Rhines noted: “They probably can. But, they will have to develop a production base of “learning” to reduce cost, improve yields and maybe even reliability. This will take some time.”

Penn added: “Technically (i.e., meeting the spec), probably, yes. Reliability, probably no, for the Tier 1 customers (that will take several years to build up the production experience). Cost, definitely not!

“Their small fab scale and late learning curve start means that their die cost will be sizably higher than those of Samsung and SKH, and also Micron. Plus, their yields will be lower. Then, there’s the deep cash pockets issue to fund these ongoing cost disadvantages.”

300mm fabs
In a separate situation, some 300mm fabs closing, for example, ProMOS. Dr. Rhines said: “It’s because of an imbalance of supply and demand for the products they make, thus limiting their profitability. It could also be because they don’t see an adequate investment return from the expensive new capacity investments, and therefore, find it more attractive to phase out some of their existing capacity.”

Malcolm Penn felt that the fabs were too old and technically obsolete.

Finally, are there more IC companies making transition to fab-lite or fabless business model?

Penn noted: “There’s no-one left to change! Everyone’s now fablite or fabless, except for Intel and Samsung (logic) and the memory manufacturers.”

Dr. Rhines said: “Based upon the growth of foundry revenue vs. total semiconductor revenue growth, there must be a continuing transition of capacity away from IDMs toward foundries. In addition, IDMs like Samsung are finding it economic to build the foundry business to increase the volume base of products that utilize their technology and capital investment.”