SAP India recently collaborated with ITC and L&T Public Charitable Trust to launch ‘code unnati’ a multi-year, collaborative, digital literacy and software skills development initiative in India.
code unnati has six partners – NASSCOM Foundation, HOPE Foundation, Pratham InfoTech Foundation, Agasatya International Foundation, Samarthanam Trust for the Disabled, and UNDP India.The initiative aims to achieve the UN’s sustainable goals of: no poverty, quality education, decent work and economic growth, and partnerships for the goals.
In the pilot phase till next year, the initiative will focus on the rural areas of Andhra Pradesh, Telengana, Maharashtra, Karnataka, Gujarat, Rajasthan, as well as the urban disadvantaged demographies in Bangalore, Mumbai, Delhi-NCR, Kolkata, Ahmedabad, Pune, Vizag and Hyderabad.
Innovations through collaboration – Making of a digital literate society
There was a panel discussion, titled ‘Innovations through collaboration – Making of a digital literate society’. Shrikant Sinha, CEO, NASSCOM Foundation, said that the collaborations themselves need to be scaled up.
Dr. Madhav Chavan, founder, Pratham Foundation, said that optimum results have to be defined. He urged for digital literacy to go mobile.
Clement Chauvet, chief-skills and business development, UNDP India, noted that by using Project Disha, UNDP has managed to put 1 million girls/women to have some opportunity in life. He added that there is a need to bridge the information gap. There is also a need to ensure that the recepients were digitally literate as well. There should be a practical, blended element to spread literacy.
Ms Gayatri Mishra Oleti, senior deputy GM and head Operations, L&T Public Charitable Trust, said there are many ITC applications and all had benefitted. The question is: how do we reach out to the last mile people?There is a need to partner with the local governments.
Dr. Asheesh Ambasta, exective VP and head of Social Investments, ITC Ltd, said that multi-stakeholder partnerships are of importance. According to him, the learning with multiple partners is how do you align them with the set of project priorities? There is a need to identify roles for each partner, and set up a mechanism to review the program regularly.
Krishnan Chatterjee, head of marketing, SAP Indian Sub-continent, added that there is something empowering about technology. It can reduce inefficiencies and waste. He cited the example of Kolkata’s Maatir Manush, a program where they photograph 3-5 million farmers regarding crop queries.
Deb Deep Dasgupta, president and MD, SAP Indian Sub-continent, said that digital India promises that India will go on to become the world’s third-largest digital economy by 2025-30. However, lot of work needs to be done as only 10 percent of the Indian population is digitally literate.
He said that code unnati is India’s first-ever corporate-citizen initiative. These are:
a) Provide employable software IT skills for youth and women
b) Digital literacy for all
c) Provide employment to at least 50 percent of the youth trained
d) Digtal enablement of the Gram Panchayats.
How digital empowerment will make India more inclusive
There was a second panel discussion on ‘How digital empowerment will make India more inclusive.’
CT Sadanandan, VP Corporate Services & CSR, Tata Communications, said that awareness and the availability of an infrastructure should be present. Stakeholders at corporate India can make a difference.
Ms Kabi Sharman, India head, Pyxera Global, said corporate skills and knowledge are not being shared by the NGOs. There is also a need to understand people’s lives better by interacting with the local population.
Ajith Basu, Agasathya International Foundation, pointed out two key questions, namely, who are we going to teach, and how can we enable a child to learn! The idea is to inspire learning. There must be more collaborative learning.
Ian Correa, board member, HOPE Foundation, said there is a need to focus on the journey itself. And, if possible, to acquire special skills. The poor people of India require opportunities. Together, we can plug the gaps.
Mahantesh GK, CEO, Samarthanam Trust for Disabled, said the acceptance of being disabled is itself key. Technology and opportunity go together. Digital revolution has already brought massive progress. More needs to be done.
Here is the concluding part of my discussion with Dr. Walden C. Rhines, chairman and CEO, Mentor Graphics.
Getting billion-gate design correct
In EDA, is there now some chance of getting a billion-gate design correct on first pass?
Dr. Rhines said: “Absolutely! Today’s methodology is up to the task and customers have already reported “billion gate equivalent” designs, i.e., 4 billion transistor, correct on first pass. Correct logic is a much easier challenge than full production readiness on first pass!
“Achieving targeted power dissipation and timing has been more of a challenge but that’s where recent tool improvements are having their greatest impact. Almost all designs of this size now go through exhaustive verification, including power analysis, using emulation. That change in methodology has increased the cycles of verification by more than three orders of magnitude.
“Beyond simply achieving functional silicon with acceptable power and timing, more and more companies are now using EDA tools to assure a rapid ramp to high yield in production. This requires use of a whole new generation of “design for test” tools directed at defect driven yield analysis.
“By our measures, some of the top semiconductor companies analyze more than 500,000 defective parts every day to identify design and process problems.”
Standardization of SoC verification flow
Next, what is the status of the standardization of SoC verification flow today?
He said that Mentor Graphics has long worked on providing leading functional verification products. “We are doubling down on perfecting tools that are part of an enterprise platform where common testbench stimulus, verification IP, and standard verification languages can be used up and down the tool chain. However, the flow belongs to the customer.
“We do not try to enforce a “standard verification flow”. We are happy to accommodate unique customer needs and trust our customer to know the unique requirements of their own markets.
It would be interesting to know what has been happening regarding the coverage and power across all aspects of verification?
According to Dr. Rhines, power management debug has permeated all aspects of traditional HDL based verification. For large SoCs, debugging power-management related problems is a very difficult task. Power is managed wholly or in part by software. Increasingly, validation of power managed designs, including power estimation, requires hardware accelerated solutions such as emulation and prototypes.
New releases of the UPF standard include lots of new capabilities that help verify power usage but that do require additional effort to analyze. Examples include dynamic power related messages, automatic power specific assertion generation and support for the entire flow from simulation through emulation and prototypes.
In addition, lots of designs now use new tools for power management verification, static analysis, rule based power checks and power-aware logic equivalence checking.
Similarly, what is happening in active power management today?
He said that active power management creates the need for functional verification. Traditionally, power has been managed via clock gating, power gating and dynamic voltage and frequency scaling.
The first two methods (clock and power gating) directly impact functionality necessitating the need for things like isolation with clamp values on inputs or outputs to a power gated block of logic, retention registers and gating logic for clocks, as well as the associated control signals or registers and the state machines, which manage the transitions from one state to another.
Verification of the active power management logic and control states necessitates the need for UPF support in verification solutions. The challenge in debugging power management issues drives the value in dynamic checks to ensure valid power down and up sequences, save/restore or resetting/write-before-read behavior of registers in power domains and proper activation and de-activation of isolation logic values.
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It has always been a great pleasure chatting up with Dr. Walden (Wally) C. Rhines, chairman and CEO of Mentor Graphics. It has been a while since we discussed the global semiconductor industry in such detail, and therefore, the latest experience is even more memorable.
First, I asked Dr. Wally Rhines how is Mentor predicting the global semicon industry to perform in 2017?
He said that the growth of the semiconductor market has averaged anywhere between 3-5 percent throughout the 2000’s. In most recent years, since 2008/2009, IC units have grown consistently at a rate of 6-8 percent,, indicating continued demand for semiconductor technology.
ASPs have been drifting downward for a long time with only a handful of exceptions since 1995. The trend appears to be moderating in the last decade, but the downward pressure in pricing has pushed the overall revenue to 3-5 percent growth rate mentioned earlier.
For 2017, most industry research firms and analysts are expecting a relatively positive year (the average forecast across 10 semiconductor research firms is currently at 5.5 percent). Mentor Graphics expects that number to be very conservative due to changing dynamics in the semiconductor industry and how the market is actually measured.
Dr. Rhines said: “Within the last decade there has been an emergence of systems companies designing chips for internal consumption. Those chips are typically not measured at all, or are only partially measured if they are produced by a foundry company. We see the trend in several important areas like smartphone manufacturers.
“Apple and Samsung have been manufacturing their own application processors for some time. However, there is an ever increasing list of other market leaders following with their own designs.
“We are also seeing a number of companies involved with cloud services or other data center intensive companies designing chips for their internal consumption. Unless something unexpected occurs, 2017 should be a good year for the semiconductor industry with growth above average.”
Next, how has been the growth in EDA for 2016? How will the performance be in 2017? Where does Mentor come in all of this?
According to Dr. Rhines, EDA had a strong year in 2016 with total growth of about 9 percent overall, including SIP. Tools alone had growth of about 7.5 percent. Demand for tools continues to look strong for the industry as there remains a strong focus on the leading-edge driving the need for advanced design technology.
Moore’s law continues to drive the industry into smaller nodes as companies are preparing for 10nm, 7nm and 5nm nodes. Advanced nodes continue to drive EDA tool adoption in manufacturing and design.
Additionally, increased challenges and methodologies in functional verification drive technology adoption in enterprise verification including areas like emulation, which had a resurgence in 2016 after several flat years.
Dr. Rhines elaborated: “We are seeing increased activity in areas like ESL as well with ESL Synthesis having its best year ever. PCB design is also enjoying a resurgence in growth as designs become more complex and new design methodologies like System of Systems design begin to emerge.
“In 2016, Mentor Graphics reported an all-time record of $1.285 billion, an 8.6 percent growth or a full point higher than industry tool growth of 7.5 percent. The proposed merger with Siemens should bring additional resources to Mentor’s R&D and customer support capability so our fourth quarter results suggest that customers are pleased with the outlook.”
Part II of this interview appears in April where I will be discussing standardization of SoC verification flow, billion-gate design, power management, etc.
Thanks are due to Raghu Panicker, country sales director, and Veeresh Shetty, marketing manager – Europe and India, Mentor Graphics.
Gionee has launched its first flagship mobile phone of the year, the A1, in India.
The new model offers longer battery life, 4010 mAh battery, with ultrafast charging capability, and enhanced picture quality to capture great selfies. It has a stunning 16MP front camera, which offers clearer and more beautiful selfies. The A1 is loaded with a faster and safer fingerprint unlock, and Android 7.0 Nougat with Amigo 4.0, amongst a host other innovative features.
Gionee also unveiled #Selfiestan, a world of selfies that celebrates inclusiveness of varied expressions of today’s Hindustani. The unique campaign, #Selfiestan, is targeted at the growing breed of selfie enthusiasts in India. Selfies have undergone a socio cultural shift in the country to be the most powerful tool of inclusive expression.
Arvind R Vohra, country CEO and MD, Gionee India, said: “Today’s generation views the world from their front camera. They live for creating and celebrating experiences out of moments. At Gionee, we want to celebrate this inclusiveness by dissolving boundaries and creating a world of equals where every moment is worth capturing. Through #Selfiestan, Gionee plans to give India a sense of ownership and belonging by creating a world of Hindustan ki selfies. With the new A1, we take our first step towards building #Selfiestan.”
I am really intrigued by this headline! First, SEMI, and now, The Information Network, are making the forecast for China!! However, what has been India doing? Nothing!!
Massive investments in Mainland China are finally showing benefits as the ratio of ICs made in China versus those imported into China increased from 27 percent in 2015 to 29.1 percent in 2016, according to the annual update of The Information Network report entitled “Mainland China’s Semiconductor and Equipment Markets: A Complete Analysis of the Technical, Economic, and Political Issues.” Driving the growth of ICs made in China are a large number of fabs that are in construction and planning production over the next few years, said Robert Castellano, president, The Information Network.
Next, most of the advanced semiconductor packaging is done in China. There are over 150 foreign and domestic packaging companies based in China. Tied to the packaging industry is the need for back-end semiconductor equipment. With its robust IC program, China represents a strong growth area for advanced packages, used to house and protect the ICs. These advanced packages include 3D, TSV (through silicon vias), FOWLP (fan-out wafer level packaging) and flip chip.
According to The Information Network:
* Investments by the Chinese government and foreign semiconductor manufacturers have started having an impact on meeting China’s internal IC semiconductor needs.
* A surge in semiconductor growth in China merely means these same number of chips won’t be made elsewhere — a buying opportunity for semiconductor manufacturer stocks.
* Large equipment companies will benefit from new fabs built but will face increased pricing pressure from new semi manufacturers because their traditional customer base has changed.
* Smaller semiconductor equipment suppliers will benefit from a new customer base that had been traditionally buying from the same vendor.
* Rudolph Technology is an example that benefited last year, positioning itself with its product line and strategic focus on building a sales infrastructure in China.
According to SEMI, USA, China is projected to be the top spending region for fab equipment in 2019 and 2020. Of the 20 more fab projects, SEMI is tracking up to 16 potential 300mm fabs to be constructed or beginning to ramp up throughout the forecast, with the investment targeted for the memory and foundry sectors.
Is India even listening?
India continues to remain cautiously optimistic on business performance as far as the business outlook is concerned. The graying of salary increases in India is a reflection on how India Inc. is coming of age. The macro question remains: if this represents a blip or a trend! These are among the findings of the 21st Annual India Salary Increase Survey by AON Hewitt.
The survey projects a drop in pay increases to an average of 9.5 percent across industries. While the inequity of pay remains a concern, the key reasons cited by the various employees across 1,000+ firms for voluntary attrition are role stagnation and limited growth opportunities.
For almost a decade, manufacturing firms in India are budgeting higher salary Increases than services firms. A lower base and higher expectations has driven this behavior. Although, with increasing pressures on margins and improved salary base, the difference in the budgets has been gradually declining since 2013. Along with high performance – high potential and hot skills remuneration are now gaining acceptance.
The gradual slowing of pay increases and higher emphasis on productivity and performance indicates the ‘graying’ of salary budgets for India. Some industries are impacted more than others – and AON Hewitt sees faster moderation of pay increases in industries such as technology, telecom, consumer etc.
Inspite of lower salary increase budgets, top performers will continue to get lucrative hikes as companies focus on performance and criticality. While attrition was contained at a broader level, key talent attrition takes a hit. Differentiated people and pay practices slowly taking the edge away from compensation for Key Talent Management.
Projections for 2017 include salary increase projections across consumer Internet companies, life sciences, professional services, chemicals, entertainment media, automotive/vehicle manufacturing, and consumer products.
The study, the largest and the most comprehensive of its kind in India, analysed data across 1,000+ companies.
Anandorup Ghose, partner at Aon Hewitt India, said: “Political changes and economic headwinds have had an impact on business performance. However, the trend this year reflects a gradual slowing of pay increases and higher emphasis on productivity and performance – quite literally a ‘graying’ of salary budgets for India.
“The last year has shown organizations take a strong view towards performance differentiation and not only have bell curves become sharper, the pay differentiation between top and average performers has also increased.”
The Confederation of All India Traders (CAIT) and MasterCard have announced a 90-day ‘Digital Apnao Vyapar Bhadao’ campaign to accelerate the adoption of digital payments among traders in India.
In this campaign, CAIT and MasterCard will organize 500 camps across 50 cities in India over the next 90 days. It aims to on-board 5 lakh merchants and traders by bringing together financial institutions and other payments facilitators under one roof.
The camps will follow a three-step process of completing KYC documents, opening merchant accounts and helping them adopt the right digital payments solutions for their businesses.
Ravi Aurora, senior VP, Global Policy Affairs and Community Relations, MasterCard, said that the stress is on trade, As of now, around 10,000+ merchants have been asking for PoS devices daily. There is a need for more incentives across SMEs and consumers, so that they do not go back to cash-based commerce.
This step is in line with the Indian government’s multiple objectives of combating tax evasion, drive electronification, and prevent circulation of counterfeit currency. As of now, India has 1.5 million PoS locations and 0.2 million ATM locations. MasterCard is committed to a ‘less-cash society.’
Praveen Khandelwal, secretary general, CAIT, said that digital payments are very important for traders. It is also a pre-condition to embrace GST. He added that the first camp will be held today, Feb. 7, in Nagpur, followed by other cities, including, the metros.