Dr. Wally Rhines
Here is the concluding part of my discussion with Dr. Walden Rhines, chairman and CEO, Mentor, A Siemens Company.
Has the PSS been formally released? What are its implications?
Dr. Rhines said: “Accellera released an Early Adopter spec for public review at DAC in June, 2017 and is currently working on completing our work in preparation for a 1.0 release in 2018. Accellera plans to have a “1.0 Preview” version available in February, 2018 (@DVCon US) for another 30-day public review period. Then, they will do one more cleanup pass, and submit to the Accellera Board for approval in May 2018.
“The expectation is that the Board will approve the Portable Stimulus Standard 1.0 version in June, 2018, prior to the DAC. Mentor plans to have Questa inFact fully updated by then, to fully support the new standard when it comes out.
“As for the implications, we expect the Portable Stimulus standard to be the next advancement in abstraction and productivity for SoC verification. It is not expected to replace UVM, but rather be complementary to UVM to improve coverage closure, verification efficiency, and effectiveness at the block level.
“The ability to re-use the verification intent expressed in PSS from a block-level UVM environment to a software-driven, embedded-processor SoC environment, on multiple platforms (simulation, emulation, FPGA prototyping, etc.), will provide a quantum leap in productivity.
“Since the Portable Stimulus specifications are declarative, tools can fully analyze the verification-intent description at the system level and generate multiple correct-by-construction implementations of use case tests, on multiple platforms, from a single specification without requiring the verification team to rewrite the tests in UVM for the blocks and C for the system.
By the way, are the semiconductor/EDA companies re-looking at designs, rather than analyze more than 500,000 defective parts every day to identify design and process problems? If yes, how?
He said: “With today’s increased design complexity – they do both – re-look at designs before manufacturing and analyze afterwards. The complexity of today’s designs and manufacturing process requires multiple approaches to achieve high yields in each new node that is rolled out.
“Design for manufacturing and for yield are a must. However, the knowledge of the specific design practices that need to be followed for a new node is developed in multiple stages: in pre-silicon, test chips, first production design and when chips reach high production volume.
* Pre-silicon: Simulation models are used for initial design rules. Many assumptions are made and care must be taken to balance the benefit with potential overdesign for a process that will mature over time.
* Test chips: Early test chips try to mimic the major features of a real design, however, limited complexity and volume means some design rules can’t be discovered at this stage.
* First production design: Additional complexity of a real design and increased volumes expose more issues that need to be fed back to design for future revisions or the next design on a node.
* High production volume and additional designs introduced: High production volume and each subsequent design can benefit from the learnings at the previous stages. Many issues during this phase are resolved with process improvements, but continuous learning still remains key.
“The challenge is not eliminating the later learning phases, as this will never go away. Rather, the challenge is for the industry to maximize the learning at each phase and establish a continuous improvement cycle in design to take advantage of the knowledge gained. This is the foundational idea in closed-loop DFM, which is a process to maximize the design for manufacturing benefit throughout all phases.
Let’s also look at verification. What is the latest regarding coverage and power across all the aspects of verification?
Dr. Rhines added: “Actually, the recent trends have expanded to multiple concerns that cut across all aspects of verification, beyond coverage and power, such as security and safety. One driving force behind these trends is the convergence of computing, networking, and communications technologies. This is driving new markets, such as the Internet-of-things (IoT) ecosystem and automotive.
“A common theme across these emerging systems is the need for security, safety, and low power–whether you are talking about IoT edge devices or high-availability systems in the cloud. These new challenges have opened innovation opportunities, enabling us to rethink the way we approach verification. For example, concerning coverage, new statistical metrics have emerged providing deep system-level analysis capabilities that leverage data analytics techniques. This insight has become essential for system-level performance analysis.
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The year 2018 is nearly upon us! And, who better than Dr. Walden C. Rhines, CEO and chairman of the Board of Directors of Mentor, a Siemens business, a leading industry personality, to provide us with an outlook for the global semiconductor industry!
Dr. Wally Rhines and I chatted about the global semiconductor and EDA industries, the Accellera Portable Stimulus Standard (PSS), and a host of other issues.
Semicon industry in 2018
First, how is Mentor predicting the global semiconductor industry to perform in 2018?
Dr. Rhines said: “The semiconductor industry performance for 2017 has been a pleasant surprise for most industry observers. The year is finally winding down, with the expectations for growth in the low 20s on the average – nearly 3-4 times as much as most observers had predicted only one year ago.
“Unit growth has consistently been 7-9 percent in recent years since the great recession. However, ASPs have been pretty consistently declining until 2017, when they were driven up mostly by memory prices for DRAMs and FLASH. Memory, once again, is behind the 2017 boom cycle. However, the rest of the IC business has also been relatively strong with growth in the higher single digits (7-8 percent), which is stronger than we have experienced in recent years.
“Memory prices are expected to soften as additional capacity comes on-line in 2018, especially as the year continues into the second half. However, the remainder of the non-memory semiconductor market should continue to have strong performance similar to 2017 (~7-8 percent) as the market fundamentals remain strong.
“Over the last several years, the semiconductor industry has experienced a wave of consolidations. I believe that we are between major waves of growth that are typical of the semiconductor industry. Historically, new semiconductor growth is ushered in by new applications that become possible when the cost per function, or some other new capability, makes the new application possible.
“In recent years, the cost per transistor for semiconductors has decreased more than 35 percent per year, just as it has, on average, for most of the last 60 years. It’s likely that continuation of this trend will, in fact, enable future waves of new semiconductor applications.
“Packaging, as well as package/chip simulation, continue to be important issues. Next generation simulation, verification, and analysis for multi-chip packaging configurations is now available. Now, designers of chips can intelligently analyze the packaging and pin-out configurations that will be most effective for cost and performance, based on a steady flow of data between the packaging engineer and the chip designer.”
EDA segment in 2018
And, how is the EDA segment looking in 2018?
According to Dr. Rhines, the EDA License and Maintenance is having a strong year in 2017. The annual growth is over 9 percent through the most recent four quarters with available data (Q3 2016 – Q2 2017).
He said: “The Semiconductor IP component of EDA achieved growth of nearly 17 percent overall, over the same period, as would be expected since Semiconductor IP is an important part of the supply chain for the broader semiconductor market.
“With expectations for the world economy and the overall semiconductor industry remaining strong, I expect semiconductor investment into design to also remain strong. EDA License and Maintenance is accounted for within the semiconductor company R&D expense budgets. Those budgets have a strong correlation to EDA License and Maintenance revenue. Therefore, I expect similarly strong growth in 2018.
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Here is the concluding part of my discussion with Dr. Walden C. Rhines, chairman and CEO, Mentor Graphics.
Getting billion-gate design correct
In EDA, is there now some chance of getting a billion-gate design correct on first pass?
Dr. Rhines said: “Absolutely! Today’s methodology is up to the task and customers have already reported “billion gate equivalent” designs, i.e., 4 billion transistor, correct on first pass. Correct logic is a much easier challenge than full production readiness on first pass!
“Achieving targeted power dissipation and timing has been more of a challenge but that’s where recent tool improvements are having their greatest impact. Almost all designs of this size now go through exhaustive verification, including power analysis, using emulation. That change in methodology has increased the cycles of verification by more than three orders of magnitude.
“Beyond simply achieving functional silicon with acceptable power and timing, more and more companies are now using EDA tools to assure a rapid ramp to high yield in production. This requires use of a whole new generation of “design for test” tools directed at defect driven yield analysis.
“By our measures, some of the top semiconductor companies analyze more than 500,000 defective parts every day to identify design and process problems.”
Standardization of SoC verification flow
Next, what is the status of the standardization of SoC verification flow today?
He said that Mentor Graphics has long worked on providing leading functional verification products. “We are doubling down on perfecting tools that are part of an enterprise platform where common testbench stimulus, verification IP, and standard verification languages can be used up and down the tool chain. However, the flow belongs to the customer.
“We do not try to enforce a “standard verification flow”. We are happy to accommodate unique customer needs and trust our customer to know the unique requirements of their own markets.
It would be interesting to know what has been happening regarding the coverage and power across all aspects of verification?
According to Dr. Rhines, power management debug has permeated all aspects of traditional HDL based verification. For large SoCs, debugging power-management related problems is a very difficult task. Power is managed wholly or in part by software. Increasingly, validation of power managed designs, including power estimation, requires hardware accelerated solutions such as emulation and prototypes.
New releases of the UPF standard include lots of new capabilities that help verify power usage but that do require additional effort to analyze. Examples include dynamic power related messages, automatic power specific assertion generation and support for the entire flow from simulation through emulation and prototypes.
In addition, lots of designs now use new tools for power management verification, static analysis, rule based power checks and power-aware logic equivalence checking.
Similarly, what is happening in active power management today?
He said that active power management creates the need for functional verification. Traditionally, power has been managed via clock gating, power gating and dynamic voltage and frequency scaling.
The first two methods (clock and power gating) directly impact functionality necessitating the need for things like isolation with clamp values on inputs or outputs to a power gated block of logic, retention registers and gating logic for clocks, as well as the associated control signals or registers and the state machines, which manage the transitions from one state to another.
Verification of the active power management logic and control states necessitates the need for UPF support in verification solutions. The challenge in debugging power management issues drives the value in dynamic checks to ensure valid power down and up sequences, save/restore or resetting/write-before-read behavior of registers in power domains and proper activation and de-activation of isolation logic values.
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It has always been a great pleasure chatting up with Dr. Walden (Wally) C. Rhines, chairman and CEO of Mentor Graphics. It has been a while since we discussed the global semiconductor industry in such detail, and therefore, the latest experience is even more memorable.
First, I asked Dr. Wally Rhines how is Mentor predicting the global semicon industry to perform in 2017?
He said that the growth of the semiconductor market has averaged anywhere between 3-5 percent throughout the 2000’s. In most recent years, since 2008/2009, IC units have grown consistently at a rate of 6-8 percent,, indicating continued demand for semiconductor technology.
ASPs have been drifting downward for a long time with only a handful of exceptions since 1995. The trend appears to be moderating in the last decade, but the downward pressure in pricing has pushed the overall revenue to 3-5 percent growth rate mentioned earlier.
For 2017, most industry research firms and analysts are expecting a relatively positive year (the average forecast across 10 semiconductor research firms is currently at 5.5 percent). Mentor Graphics expects that number to be very conservative due to changing dynamics in the semiconductor industry and how the market is actually measured.
Dr. Rhines said: “Within the last decade there has been an emergence of systems companies designing chips for internal consumption. Those chips are typically not measured at all, or are only partially measured if they are produced by a foundry company. We see the trend in several important areas like smartphone manufacturers.
“Apple and Samsung have been manufacturing their own application processors for some time. However, there is an ever increasing list of other market leaders following with their own designs.
“We are also seeing a number of companies involved with cloud services or other data center intensive companies designing chips for their internal consumption. Unless something unexpected occurs, 2017 should be a good year for the semiconductor industry with growth above average.”
Next, how has been the growth in EDA for 2016? How will the performance be in 2017? Where does Mentor come in all of this?
According to Dr. Rhines, EDA had a strong year in 2016 with total growth of about 9 percent overall, including SIP. Tools alone had growth of about 7.5 percent. Demand for tools continues to look strong for the industry as there remains a strong focus on the leading-edge driving the need for advanced design technology.
Moore’s law continues to drive the industry into smaller nodes as companies are preparing for 10nm, 7nm and 5nm nodes. Advanced nodes continue to drive EDA tool adoption in manufacturing and design.
Additionally, increased challenges and methodologies in functional verification drive technology adoption in enterprise verification including areas like emulation, which had a resurgence in 2016 after several flat years.
Dr. Rhines elaborated: “We are seeing increased activity in areas like ESL as well with ESL Synthesis having its best year ever. PCB design is also enjoying a resurgence in growth as designs become more complex and new design methodologies like System of Systems design begin to emerge.
“In 2016, Mentor Graphics reported an all-time record of $1.285 billion, an 8.6 percent growth or a full point higher than industry tool growth of 7.5 percent. The proposed merger with Siemens should bring additional resources to Mentor’s R&D and customer support capability so our fourth quarter results suggest that customers are pleased with the outlook.”
Part II of this interview appears in April where I will be discussing standardization of SoC verification flow, billion-gate design, power management, etc.
Thanks are due to Raghu Panicker, country sales director, and Veeresh Shetty, marketing manager – Europe and India, Mentor Graphics.