EDA
New leaders can capture the chiplet revolution
TechInsights, USA, organized a fireside chat today on the global semiconductor industry.
G. Dan Hutcheson, Vice Chair, TechInsights, said, the Chinese economy has been starting to recover now. We are also getting into a new PC up-cycle. Companies are also trying to move their centers of excellence to the other countries. We are seeing a normal upside right now. You do get some variation in supply over the period of 12 months. We are also moving into the 2nm era next year.
The magnificent seven for everybody includes: Apple, Amazon, Google, Meta, Microsoft, Nvidia, Tesla, etc. Microsoft and Apple came out of the PC era. Amazon and Google came out in the 2000s. Nvidia came out of semiconductors. Tesla happened later. Apple is still riding on the smartphone. We also have the growing EV market. AI has also been emerging strong. However, AI stocks were worst performing among semiconductors stocks last week.
Nvidia has done a double lock-up recently. It has GPUs and whole system. They are re-architecting the way the data center works. Nvidia is, where it is today. We now need a new technology to be the next big thing. When Apple iPhone first came in, it started a new revolution. It always surprises you!
We will have new leaders in future. We will also see new leaders capturing the growing chiplet revolution. The foundries that exist would not have been possible without the EDA revolution. Chiplets have now emerged as the new revolution.
We have neural network processors already. We also have cellphone APUs. There are some really cool things coming that will help organizing your life, especially using the smartphone.
AI is seeing huge explosion in entrepreneurial pursuit. Several AI chip startups will be coming up. GPUs always had an innate advantage. GPUs chips were power hungry. We now need to partition that down to smaller parts. PCs had closed architecture partnership between Intel and Microsoft. We later saw the explosion of innovation around apps. AI is more of a curiosity right now. IBM used it to help physicians diagnose cancer. Today, it has become routine. AI solutions will take step forward, and bring real value.
China needs to catch up
As for domestic Chinese companies in AI, China is developing its own core technology. Taiwan has been incredibly successful as it has access to the global technologies. China also needs to do lot of classical innovation to get forward. Doing a lot of innovation can be very cultural. Silicon Valley is one example to follow. We are hoping that China can catch up, and get back to the order, and we can get back the global order.
AI will be used on chips to improve MCU/MPU performance. Synopsys is a world leader that enables all of that. We are also seeing new process technologies being developed. However, we still need the human intelligence to make all of this happen. AI, as a tool for engineers, may make them struggle. People were locked into their tools earlier. You have to be really good at using all the weapons at your disposal. If you don’t, you can be left behind. We are also going to go through another productivity surge in future
Regarding alternatives to silicon, he said that God was bullish on silicon. It has proved to be the best material. Today, we have substrates with specific functions. We have to get around the interconnect level. Data centers are migrating further down to the new chips. Quantum does replace it! However, it will co-exist with silicon.
Lead times are delivered largely by the complexity of the problem addressed. Today, we have about 2,000 process steps, but the lead time is still 12-13 weeks. We have to address complexity. We had the case of just-in-time. We may create disaster if we moved to just-in-case. Shrinking lead times requires you to decrease utilization. We saw lead times decrease to 60 percent, using utilization. Intel had increased utilization by increasing hot spots.
We also need to look at the supply chain. As we become more efficient, we may also be dealing with even more complexity. We cannot see that either happen, or decrease, in the forseeable future. Regarding NAND demand, we are witnessing the incoming demand, at least from data centers.
Japan getting back mojo!
Finally, which country can emerge as a semiconductor powerhouse? Japan is finally getting over lost decades. Japan is coming back certainly. It appears that Japan has got back its mojo after a long time. China is also going to grow. India has an advantage of cheap labor force. India may have difficulty in duplicating the success of software. It has advantages and disadvantages.
Japan and South Korea are much ahead right now. The US recovery is also taking place. Mexico is starting to rise. That’s driving new factories inside Mexico. Canada has a liberal immigration policy. Some of the best and brightest are present there. There is always opportunity. With technology, you need to run faster, work smarter, etc.
He hoped that everyone is safe in Taiwan, following the earthquake. Despite the severity of the tremors, the impact on Taiwan’s semiconductor manufacturing capacity appears to be limited. TSMC has done, and been doing incredible work in the future.
SEIDA, and China, may develop nodes of smaller geometries! Is the world curious?
Semiconductor Intelligent Design Automation (SEIDA), from China, is all in the news today.
As per reports, some former executives from SiemensEDA (formerly, Mentor Graphics), have together established an electronic design automation (EDA) company in Hangzhou, China, called SEIDA. It is said to be headed by Liguo “Recoo” Zhang, formerly of SiemensEDA. SEIDA aims to “enable chip success.” SEIDA also plans to launch optical proximity correction (OPC) software sometime this year.
Malcolm Penn, CEO and Founder, Future Horizons noted: “Indeed! The more the west pushes back, the more innovative China becomes.” He added: “SEIDA is a perfect example of why a containment strategy never works. It’s like trying to slay a hydra! You cut off one head, and two more emerge!” Well, IFS 2024 is just around the corner. We will probably get to hear what more Malcolm has to say regarding SEIDA.
Lung Chu, President, SEMI China, elaborated: “Similar to semiconductor equipment, EDA tools are another so-called “choke-point” that are being targeted for export controls. In the last few years, there have been ~50 new EDA start-ups getting funded in many niche market segments. OPC is one of the most critical and difficult tools to get customer acceptance, since these are the last software tools used by the foundry/fab, before production, to assure yield.”
Regarding this hype over SEIDA, Jaswinder Ahuja, Corporate VP and MD, Cadence Design India, said that he is aware of the company.
On the importance of optical proximity correction (OPC) for EDA, Ahuja added: “OPC is extremely important for manufacture-ability, and becomes even more important as we progress to smaller geometries.” There you go! With this EDA tool, China can probably develop nodes of smaller geometries!! This is something that it was lacking all this time. So, is the world watching, and, is it aware of such things happening? Is the world really curious?
Any cause for worry?
Further, is there any reason for Siemens EDA to be worried from SEIDA? Ahuja can think of several reasons. The two most important reasons are: has there been intellectual property theft, and the other is the competitive risk. As for the effect on the other EDA players, Cadence does not operate in this space. However, both Mentor (SiemensEDA) and Synopsys do.
Can China break through US chip restrictions with SEIDA? Ahuja cautioned that this is just one piece of a larger puzzle. China seems resolute, and we should take that seriously.
Now, there has been long dominance of global EDA industry by three leading players — Cadence, Synopsys, and Mentor Graphics (SiemensEDA). With the possible arrival of SEIDA, at best, these three players may lose some clout in China market. However, that probably won’t be the case elsewhere.
China is looking at developing a stronger domestic semiconductor industry in future. China has programs like “Thousand Talents,” that provide incentives for skilled Chinese experts to return from overseas. However, developing advanced chips isn’t that easy! Its mastery also involves national security implications.
SEIDA is said to have support from several Chinese investors, including Semiconductor Manufacturing International Corp. (SMIC). Can SEIDA actually develop OPC in such short time? If yes, did they take any IP inappropriately? Are they working in open source, for that matter? Alright, is there any good EDA tool that works in open source?
KiCad is an open-source software suite for EDA. Programs handle Schematic Capture and PCB Layout with Gerber output. FOSSEE or Free/Libre and Open Source Software for Education project promotes the use of FLOSS tools in academia and research. AWS has deployed OpenROAD project for open-source EDA via low-cost and easy-access cloud solution. Developers are generally spread everywhere, and there’s very little anyone can do about any open source project.
On the other hand, it is probably alright for China to develop an EDA tool. It will help them grow the semiconductor segment across China. But, that’s where the buck will probably stop! There are 194 other countries where China may find difficult to get in. There could be a few, but that’s about it! Still, do not count out China.
The big three EDA players will still have a very large market to service in the future. Maybe, there could be some slight adjustments in their respective revenue balance sheets. There could even be the emergence of newer, and better EDA tools in the future. Just don’t count out anything!
Jan-Peter Kleinhans, director of technology and geopolitics, Stiftung Neue Verantwortung, Germany, told Reuters that it would be challenging to develop OPC from scratch without access to existing IP in the two years of SEIDA’s existence.
I also contacted Jan-Peter Kleinhans head of Technology and Geopolitics, Stiftung Neue Verantwortung, Berlin, Germany. So far, there has been no response. Nor did I hear from SEIDA, so far. 🙂
Finally, a humble request to all EDA folks: please forgive me if I have missed anything! Or, in case I have not given any tool a proper look. I am just a student of semiconductors. 🙂
My humble attempt at summarizing National Semiconductor Technology Center (NSTC)!
Friends, I have tried my level best to summarize the vision and strategy for the National Semiconductor Technology Center (NSTC) document released today by US Department of Commerce, NIST, Chips.gov, respectively. Putting everything in about 1,350 words isn’t easy! I hope to provide more information soon!
CHIPS for America has outlined the vision for the National Semiconductor Technology Center (NSTC). It states how the NSTC will accelerate America’s ability to develop chips and technologies of the future to safeguard America’s global innovation leadership.
NSTC’s programs are intended for the entire ecosystem: fabless companies, research institutions, community colleges, state and local governments, national labs, foundries, integrated device manufacturers, equipment vendors, materials suppliers, labor unions, and investors.
NSTC has three high-level goals:
- Extend America’s leadership in semiconductor technology.
- Reduce the time and cost of moving from design idea to commercialization.
- Build and sustain a semiconductor workforce development ecosystem.
Mission statement
NSTC has mission statement of US leadership, looking at the industries of the future, have a focal point of core of centrally operated, in-house research, engineering, and program capabilities, combined with a network of directly funded and affliliated entities that takes advantage of regional expertise and assets. Besides research and engineering, and the semiconductor ecosystem, it will be advancing and enabling, by engaging in and support research through collaboration, technical exchanges, convenings, and grant programs. It will also look at disruptive innovation.
NSTC and Microelectronics Commons will expand the number of concepts and ideas that can transition from proof-of-concept to the market. NSTC will be part of a whole-of-government strategy to advance and enable innovations in microelectronics R&D. National Advanced Packaging Manufacturing Program (NAPMP) will likely fund the Advanced Packaging Pilot Facility, and the Heterogeneous Integration Technical Center.
Manufacturing USA network currently consists of 16 public-private partnerships, where members from industry, educational institutions, and government work together. The Chips Act authorizes the establishment of up to three new Manufacturing USA institutes focused on advancing semiconductor manufacturing.
The CHIPS Metrology Research Program enabled by the Act is focused on creating advances and breakthroughs in measurement science, standards, materials characterization, instrumentation, testing, and manufacturing capabilities that will accelerate the development of metrology for next-generation microelectronics technology. The Chips Program Office (CPO) funding notice includes the suggestions for incentives applicants’ R&D plans.
To further advance electronic design automation (EDA) and circuit-design industries, the NSTC should work to facilitate development of standards for process and assembly design kits so that heterogenous systems can be better integrated in EDA tooling flows.
Technical centers
The semiconductor community has provided extensive input to the requirements for potential technical centers. NSTC will embark on a prioritization process to ensure that highest priority needs are met with funds available. Identified needs for NSTC to consider include:
- Baseline CMOS (complementary metal-oxide semiconductor): Fully functional and supported CMOS process flow at 22 nm or below with a capacity of 10,000 wafer starts per month on 300 mm wafers.
- CMOS R&D process: Front-end short loops supporting < 3 nm technology R&D at a capacity of 2,000 wafers per month using extreme ultraviolet technology enabling the development of leading-edge materials, devices, and process and metrology tools.
- Manufacturing test vehicles that provide low-cost patterned and functional substrates that can be used to provide data through electrical test, to enable materials, equipment, process, and device development and optimization, especially for CMOS+X enabled technologies.
- Extended metrology capacity to enable R&D in a production environment including rapid failure analysis to shorten prototype development cycles, extensive in-line process monitoring capabilities, and off-line characterization facilities.
- Space and flexibility to accommodate next-generation or prototype processing and metrology tools so that they can be demonstrated in a production environment.
- Back-end short loop processing from specialized capabilities enabling ‘fab-to-lab’ finishing of R&D devices and high-quality processing of novel materials and devices, while maintaining process and material segregation.
- Power electronics: Power management devices often require non-silicon substrates (e.g., silicon carbide, gallium nitride) and specialized designs, tools, and processes.
- RF, mixed signal, and analog: Communication and sensing applications require diverse capabilities distinct from leading-edge CMOS.
- Photonics: Advancements in quantum, sensing, and interconnect are all possible at the intersection of light and electronics.
- Microelectromechanical systems: Sensors for mobile, automotive, health care, and IoT. are all growth areas that require resources distinct from traditional CMOS flow.
- Bioelectronics: The convergence of microfabrication and biotechnology brings new opportunities, but also increased complexity and significant integration challenges.
- Mature node: NSTC may seek to have capacity at a mature node (e.g., 130 nm), with such a facility well suited to certain research programs and workforce education.
- Design tools: New design tools and methodologies to accelerate the generation of circuit IP; virtualize devices, circuits, and processes; and enable co-design, simulation, and heterogeneous integration.
For chiplets, the Department expects NSTC to work with NAPMP to create a chiplet program that plays a leading role in driving the standards in 2D and 2.5D heterogenous integration, and establishing long-term vision in 3D integration of memory and logic beyond existing standards in stacked memory.
Design enablement gateway
The semiconductor community has provided extensive input to the requirements for a new hosted design environment. Specifications that have been identified include:
- A complete set of resources needed for the design, simulation, and tape-out of integrated systems to be made in the U.S., without proprietary information leaving cloud environment.
- A well-structured, version-controlled interchange system between all participants within a multiparty ‘nondisclosure agreement ecosystem’ to facilitate sharing IP as needed by the members, especially circuit design-IP surrounding foundry process design kits.
- An ‘app-store’-like environment where users can exchange integrated circuit design-IP under standardized licensing and support terms for basic R&D as well as for commercial use, as determined by the owner of the circuit design-IP.
- A catalog of IP generated from NSTC-sponsored projects, along with a pre-defined set of contractual obligations to determine the ownership of that IP; IP may be owned or co-owned by members or the NSTC itself.
- A catalog of circuit design-IP from NSTC-sponsored projects and, to the extent possible, of other federal agencies, that is made available for license at a reasonable cost.
- A resource to help trace the provenance of circuit design-IP, both to ensure it is secure and to prevent piracy of proprietary information.
- Collaboration between commercial EDA vendors and universities or startups to consider interoperability via industry standard tool formats or APIs that would allow EDA innovations (open source or proprietary) to more tightly integrate and leverage commercial tool investment, adoption, and support.
The community has suggested options in licensing that NSTC could consider in partnership with providers of EDA tooling and integrated IP:
- Enabling the contribution of circuit design-IP under standard contributor license agreements.
- Allowing NSTC members to access NSTC EDA resources using their own existing licenses (‘bring your own license’).
- Subsidizing EDA and circuit design-IP license access for U.S. government agencies, universities, and early-stage startups.
- Developing, promoting, and supporting existing or new licensing models that improve community access, such as a non-commercial, research-only licenses at low or no cost.
Workforce plans
February 28, 2023, Notice of Funding Opportunity for Commercial Fabrication Facilities requires companies seeking funding from the CHIPS Incentives program to submit workforce development plans for the workers who will construct and operate their facilities.
NSTC should convene industry and educational institutions to identify hiring needs, challenges in existing workforce pipeline, and evidence-based strategies to overcome those challenges. NSTC should consider convening a group of experts focused on workforce to guide its efforts and investments.
NSTC should create and host a publicly accessible clearinghouse of education and workforce development information to increase standardization and transparency in the field. NSTC also seeks to encourage broad participation across the entire semiconductor ecosystem. NSTC will stay relevant only if it is serving the needs of its members.
NSTC will provide systems-level research and development with the sophisticated tools, resources, and capabilities needed to build the foundational semiconductor technologies of the future.
State of global electronic design automation market (EDA) today
At the ongoing SEMI Silicon Valley and Northeast Chapters conference, Jay Vleeschhouwer, Software Research, Griffin Securities, presented on the state of EDA: A view from Wall Street.
The combined enterprise values of Cadence Design and Synopsys are ≈$112 billion, or more than 11x combined estimated revenues for 2023 and 10.5x estimated 2024 revenues. Six years ago, the combined enterprise values of Cadence, Synopsys and Mentor was ≈$23 billion (prior to the acquisition of Mentor by Siemens).
The material increase in value has been sustained by a combination of bookings growth, including growth across multiple product categories; increasing backlog; increasing operating income (up 155 percent over the past half-decade), and increasing operating cash flow (up 170 percent over the past half-decade).
We estimate that EDA industry revenue increased by 12.5-13 percent in 2022 to over $11.7 billion. Based on our estimate for Ansys, Cadence, and Synopsys, the industry could increase by high-single-digits in 2023, or more, depending on Siemens EDA.
Ansys, Cadence, and Synopsys, could increase by high single-digits in 2023, or more, depending on Siemens EDA. The big two — Cadence and Synopsys — accounted for over 70 percent of the estimated industry in 2022. Mentor, or Siemens EDA has sustained its pre-acquisition share of 1/5th of the industry revenues.
The big four — Cadence, Synopsys, Ansys, and Mentor — account for over 90 percent of the industry revenues. In 2023, we estimate Cadence revenue will rise 4 percent to $3.67 billion. Synopsys will rise over 13 percent to $5.24 billion. Ansys EDA business will increase by 7-8 percent to over $400 million. Siemens EDA business model remains one of upfront revenue.
The industry has continued to consolidate. Cadence and Synopsys – the big two – accounted for ≈70 percent of the estimated industry revenues in 2022, as compared with ≈65 percent three years ago, and 57-58 percent a decade ago. Mentor has largely sustained its pre-acquisition share of one-fifth of industry revenues, or very nearly one-fifth, with the exception of 2022.
Big two rule!
The combined big two EDA bookings were $8.86 billion in 2022, down slightly from 2021, resulting in a three-year CAGR of 20 percent. We are estimating $8.1-$8.2 billion for 2023, and more than $9.6 billion by 2025 – consistent with an expectation of better than mid-single-digit bookings growth and continued increases in backlog.
The combined big two backlog was more than $12.7 billion as of the end of 2022, up over $4.6 billion since 2019. We are estimating as much as $13 billion by the end of 2023. One of the most important product mix changes over the past 5-10 years has been the growth of hardware-based verification (emulation and prototyping).
The combined Cadence-Synopsys hardware revenues were nearly $850 million in 2022, a new high, more than doubling from 2019, in addition where the combined EDA IP revenues were ≈$1.75 billion in 2022 (≈20 percent of combined revenue), vs. less than $1.1 billion in 2019, and less than ≈$450 million a decade ago. The big two core EDA revenues were $5.65 billion in 2022, up 15 percent, resulting in a three-year CAGR of 13 percent.
Combined EDA big two operating income in 2022 was $3.11 billion, or 35.7 percent of revenues, vs. $1.574 billion in 2019, or 27.6 percent of revenues. Increase in operating income and operating margin has been one of the most important structural changes
in the financial profile of the big two. For 2023, we are estimating combined income of $3.51 billion, or 36.5 percent of the estimated revenues, and $4.69 billion by 2025, or ≈41 percent of the estimated revenue.
Combined EDA bookings were $8.86 billion in 2022, down slightly from 2021, with a three-year CAGR of 20 percent. We are estimating $8.1-$8.2 billion for 2023, and over $9.6 billion by 2025 – consistent with an expectation of better than mid-single-digit bookings growth and continued increases in backlog. Combined big two backlog is estimated to be $13 billion by end of 2023.
The ongoing demand across multiple product categories by both semiconductor and systems customers has been fundamentally conducive to EDA revenue growth. This phenomenon is very likely to continue!
According to industry data, “IC implementation”, “synthesis”, “RTL simulation”, “analog/mixed-signal simulation”, “analysis”, “custom layout”, and “hardware-based verification” have each had multiple consecutive periods of growth on a trailing-twelve-month (TTM) basis . “Physical verification” and “PCB” have trended higher, but can be inconsistent due to the mostly upfront revenue model. Siemens remains the largest by revenue in these two categories, each among the largest in EDA.
Each of the EDA big four – Synopsys, Cadence, Mentor, and Ansys – participates in at least two of the growing categories.
Two arms races underway
There are two arms races underway in technology — software development and silicon development. Investments in silicon development – by semiconductor companies, still the majority of EDA revenues, and the always important class of “systems” companies, e.g., Apple, Microsoft, – are dependent upon EDA’s role as a source of essential technologies and services, and are sustaining the EDA industry’s revenue, income, and cash flow momentum.
EDA industry growth has been sustained by growing demand among multiple EDA tool categories – as compared with earlier periods of more narrowly based growth. This has been, and is likely to remain, an important phenomenon, supported by the
growth of semiconductor R&D budgets and systems customer product engineering budgets. These customer investments are in turn sustaining, and enabled by, EDA investments in R&D:
In 2022, combined Cadence-Synopsys R&D was $2.99 billion (≈34 percent of the revenues), vs. $2.116 billion in 2019, and $1.06 billion a decade ago. Cumulative combined R&D over the past half-decade was $12.1 billion. We are estimating $3.3 billion for 2023 and more than $3.65 billion by 2025.
One key change has been growth of hardware-based verification, including emulation and prototyping. Combined EDA IP revenues in 2022 were over $1.75 billion. Big two core EDA revenue was $5.65 billion in 2022, up 15 percent, with three-year CAGR of 13 percent. For 2023, we are estimating combined income of $3.51 billion, or 36.5 percent of estimated revenues, and $4.68 billion by 2025, or 41 percent of estimated revenues.
The ongoing demand across multiple product categories by semiconductor and systems customers has been conducive to EDA revenue growth, and that will continue. TTM also increased by product category. The leading category here is custom layout, with IC implementation, and PCB close behind.
Semiconductor R&D has shown growth. A composite of two dozen semiconductor companies showed total R&D of more than $63.8 billion in 2022, up 16 percent. Intel accounted for ≈28 percent of this total. Total R&D spending, excluding Intel, was up 16 percent in 2022, to more than $46.3 billion. AMD’s proforma R&D increased by 29 percent, Intel’s by 15 percent, NXP’s by 11 percent, Nvidia’s by 39 percent, ST’s by 10 percent, Qualcomm’s by 14 percent, and Renesas’ by almost 14 percent.
Intel’s commercial EDA spending – over $700 million last year – accounts for as much as a high-single-digit percent of EDA industry revenues. About three-fourths of its spending is with Synopsys, plus Cadence, Siemens and Ansys, etc. R&D begets bookings and backlog.
Perspectives in semiconductors: cycles, technologies, and outlooks
Dan Hutcheson, Vice Chair, TechInsights, presented perspectives in semiconductors: cycles, technologies, and outlooks. Has the silicon cycle moderated? Demand side is driven by Keynes acceleration principle. Supply is driven by technology and lags in the supply chain. Large production ramp-ups precede downturns is questionable.
The inventory amplitude drives IC ASP volatility. As do wafer size and cleanroom revolution. TSMC was the early adopter, and became universal with 300mm fabs. There has also been 20+ years of improved inventory control. Hence, there has been lower cycle-city. The 200mm holiday is now over. More than Moore capacity expansion is matching More Moore. More than Moore is no longer a friction source. Everything that could be integrated has been integrated. Average long-term growth forecast has been 5 percent for electronics, 7 percent for IC, etc.
Where will be in 10 years? We will be at $1.3 trillion revenue for semiconductors. We will need to double the number of fabs, as well as the number of people working. Smart automotive is the new queen of the market. EVs have ~2X ICE chip content. EVs are growing at ~12X.
We are forecasting the global semiconductor industry for 2023 to close at $581 billion, a dip by 6 percent over 2022. We had huge shortage in automotive chips during 2020-21. We are now seeing the same for memory chips. We had an inventory glut in 2022.
We are now on the path to a trillion dollars in a decade. IC supply/demand has held in tight conditions. At present, electronics retail prices have been falling. For semiconductor fabs, there are plans to add ~25 percent of the current capacity. Also, customer complaints regarding the inventory about extreme shortages were sign of multiple bookings. We now need to be cautious about a double dip in 2024-25, as well as inflation and hoarding.
CHIPS funding key to address memory wall, democratize access to advanced semiconductor design, develop open chiplet ecosystem
Following the landmark enactment in August 2022 of the CHIPS and Science Act to re-invigorate domestic semiconductor manufacturing and research, the Semiconductor Industry Association (SIA) and the Boston Consulting Group (BCG) released a report titled American Semiconductor Research: Leadership Through Innovation, identifying five key areas of the semiconductor R&D ecosystem that should be strengthened by the new law’s R&D funding.
The report highlights the importance of government-industry collaboration on two historic new entities—the National Semiconductor Technology Center (NSTC) and the National Advanced Packaging Manufacturing Program (NAPMP)—created by the CHIPS and Science Act. The study also calls for CHIPS funding to be used to bridge key gaps in the current semiconductor R&D ecosystem. Doing so, will help pave the way for sustained US chip innovation leadership.
Eric Breckenfeld, Director of Technology Policy, SIA, said Chips R&D implementation is to promote the collaborative R&D ecosystem aligned with industry technology agenda. It needs to support transition pathways for innovative technologies, and upgrade research infrastructure for early-stage ecosystem. It can also establish and extend access for mid-stage development and prototype infrastructure, convene industry, academia, and government for collaborative innovation partnerships, etc. Semiconductor incentives include construct, expand or modernize fabs located in the USA. NSTC aims to strengthen security of supply chain and economic competitiveness, and public-private partnership. NIST or commerce includes National Advanced Packaging Manufacturing Program.
Innovative technologies face transition barriers at multiple stages. They have to go through basic research, applied research, pathfinding and prototyping, piloting, and scaling to volume production. There is scaling up production of pilot manufacturing processes to commercially useful volumes. There are funders and performers in the NSTC/NAPMP and Valley of Death. Funders include DoE Office of Science, NIST, SBIR/STTR, etc. Performers include DoE National Labs, Universities and NNCI, NIST Laboratories, etc.
NAPMP priority
Gilroy Vandentop, Director of Corporate University Research, Intel, stated that there are so many participants and stakeholders. There are several challenges facing us. A white paper will also be released soon. Intel hopes for an industry-supported board. Shrinking the feature size is never going to drop down. We think there will be some capacity in the Intel Oregon facility. NAPMP is another priority area for Intel.
We need different academic groups to work together. We need good partnership with the academia. We will also need to focus on workforce development. We need to make that scalable and accessible. We also need to focus on marketing. We allow students to develop chips using our technology. We like what the Semiconductor Academy has been doing. We need to get started with workforce development right away. Chip programs will help them get into manufacturing.
SRC can help broaden the student population. More internships are needed. Jump 2.0 program is also ongoing. SRC is ramping up sustainability programs. Sustainability research will also have to grow at SRC.
Dr. Vijay Narayanan, IBM Fellow, said workforce development is critical. We need to start early with high school programs, etc. We also need to have regional clusters, and democratize the semiconductor education. Capturing that is going to be very important.
Addressing memory wall
Steve Pawlowski, CVP, Advanced Memory Systems, Micron, said the cost of moving data has been rising. Data movement energy for even today’s most-efficient memory solutions can be >100x the energy required for compute. Reducing that ratio is critical. Some workloads require even more data/compute. Addressing the memory wall is critical to long-term leadership.
Looking at memory trends, domain-specific architectures (DSA) scaling through increasd memory efficiency is needed. Analog accelerators pave way for orders of magnitude efficiency improvements for certain domains. There are building blocks in a memory-centric world. We need architectures/algorithms for 100x higher bandwidth, etc. We need memory-centric design. There will be tightly-coupled data and memory. DSLs centered around data locality and movement are necessary, and must be easy to program. 3D design and packaging are also required.
Memory CoE is building an ecosystem around prototyping hub. We must have infrastructure to enable, such as fab clean room space and leading-edge tools for technology development and building chip prototypes. We need advanced surface analytical and imaging labs, heterogenous integation, leading edge memort design and simulation capability, etc. This should be aligned to national priorities. SRC 2030 Decadal Plan for Semiconductors outlines key focus areas for post Moore’s Law development.
Advanced Memory Coalition of Excellence (CoE) will establish prototyping capabilities and ensure fast ramp from lab to fab with co-development across CoEs and project prioritization of vertical integration. We have challenges such as enabling high-performance energy-efficient computing. Also, reducing chip design complexity by system-level optimization, etc. Cross CoE activities will drive full stack innovation.
Opportunities in NSTC and NAPMP
Dr. Raja Swaminathan, CVP, Advanced Packaging, AMD, noted there are opportunities in NSTC and NAPMP. There should be aligned governance for them to ensure synergy. Silicon does not exist without packaging. Prototyping capabilities should be built in geographically distributed models encompassing upto six CoEs aligned around major technical institutes. CoEs should be around memory, logic, mixed-signal, RF, and power , architecture, design and tools, life sciences, NAPMP packaging, etc. We should identify a set of nationwide grand challenges.
AMD has recommended setting up national microelectronics education and training network, upgrade lab facilities and equipment, update curriculum development, hiring at least 100 new microelectronics faculty, support university access to industry-standard resources, and industry dynamics — manufacturing jobs are growing, but design jobs are experiencing exponential growth. EDA also needs to modernize for future chip designing.
Innovation in mixed-signal world
David H. Robertson, Senior Technology Director, Automotive, Communications and Aerospace, Analog Devices, spoke about innovation in the mixed-signal world. Markets and development are global for analog/mixed-signal capabilities. There are extreme diverse set of technologies, such as materials, devices, circuits, architectures, and systems. Core markets and technologies are various, such as aerospace and defense, automotive, communications, consumer, industrial automation, instrumentation, energy, power, intelligent buildings, healthcare, etc.
Collaboration becomes much more challenging (but not impossible), as you move closer to commercialization. Lack of access to/experience in manufacturing can create serious blind spots. Valley of death problem is half technical. CHIPS R&D funding can make a difference. US already has superior R&D intensity and superior market share. US semiconductor industry already spends big on R&D. We can convene collaborative full stack systems among our aims to fill critical gaps. We need to encourage academia, and SMEs/MSEs, and talent development.
Key priorities and innovation opportunities
Dr. Vijay Narayanan, IBM Fellow and Strategist for the Physics of AI, Senior Manager, PCM & AI Materials, IBM T. J Watson Research Center, spoke about key priorities and innovation opportunities. We need to democratize the access to advanced semiconductor design and spur design innovation. We need to accelerate the open chiplet ecosystem. We also need to reduce cost of chip design using EDA modernization.
The AI imperative is necessary to reduced-precision to increase compute efficiency. We can overcome Von-Neumann bottleneck with near-memory compute, in-memory compute, and increased memory bandwidth, etc. We need device architectures for vertical stacking. We can enable backend scaling beyond Cu-novel materials, processes, and integration.
We also need to democratize access to advanced semiconductor and HI technology. Next-gen HI technology can be used for 3D chiplet and increased bandwidth for system performance. Open chiplet ecosystem is breaking down barriers. It enables SMEs to work with large companies. Emerging open standard candidates include bunch of wires (BoW), universal chiplet interconnect express (UCIe), etc. EDA modernization is a platform for designers to scale their workloads on the cloud. They can transition EDA design flows to the cloud. AI/ML-driven design flow orchestration and design productivity improvement can also be achieved.
OpenROAD project: Open source platform for IC design innovation
Andrew B. Kahng, CSE and ECE Departments, UC San Diego, presented the OpenROAD project: Open source platform for IC design innovation, at the 2022 IEEE Symposium on VLSI Technology and Circuits in Hawaii, Circuits Workshop 2.
There is the crisis of hardware design. ASIC design is in advanced nodes, and there are barriers of cost, expertise, and even risk. Innovators also cannot evaluate SWaP, PPA of their design ideas. OpenROAD proposes the ease of use and runtime. It directly attacks the crises of design and innovation. RTL-to-GDS can be available in 24 hours, and there are no human-in-the-loop, with tape-out GDS, and open source that runs in 24 hours.
With OpenROAD, you can unleash system and design innovation. There can be tool customization to system and app needs. Foundation for hardware innovation can be found in the DoD/DIB. It also provides foundation for research and education, and workforce development.
Open ROAD and chip design are progressing together. There is SKY 130, with 260+ tape-outs on Google-SkyWater, e-fabless chip-ignite shuttle and commercial offering. Also, there is GF12, a mixed-signal SoC, and Intel 22/16, an Army Research Labs project in flight. OpenROAD is supporting GF12, Intel 22/16, TSMC65, GF55, SKY90, SKY130, and more. Army Research Labs is also working with University of Michigan. University of Washington is working on BlackParrot dual-core in GF12LP.
OpenROAD is now part of VLSI system design, with over 2,500 enrollments in the OpenLane/OpenROAD courses and workshops across 85 countries and 26 languages. There are novices to experts, working on trust, and 3DIC, AI/ML.
What’s next?
So, what’s next? OpenROAD is looking at 12nm tapeout-capable, with integrated architecture, database, and timer. It is looking at improved performance, power efficiency and area, ML and auto-tuning. It is on the road to EDA 2.0 with intelligence and cloud. There is COPILOT, or cloud optimized physical implementation leveraging OpenROAD technology. Some of the engaged contributors include IBM, Google, DoD, etc.
OpenROAD is a front-runner in open-source semiconductor design automation tools and know-how. The project reduces barriers of access and tool costs to democratize system and product innovation in silicon.
At VLSI-SoC 2020, there was talk about open-source EDA. If we build it, who will come? There are inherent contradictions or tensions to grapple with. Academic research meets tapeout-clean RTL-to-GDS in foundry nodes. There are factors such as research success vs. open-source EDA success. There is no human-in-the-loop tool vs. flexibility for the new, such as 2.5D, secure IC areanas, etc.
We are looking at how open source can meet business viability. The system needs will be better served in future. We can also edit the source code. We are growing the technology. We are also using ML for intelligence and self-adaptation. Cloud deployment can scale up quality and efficiency. We are always keeping in mind the critical mass and critical quality.
Using ML and AI in EDA tools
DVClub Europe recently organized a conference on using ML and AI in EDA tools.
Daniel Hansson, Founder, Verifyter, Cadence, talked about bug prediction. Bug prediction involves locating bugs without running simulation. Bugs are found/fixed faster using less simulation time.
We use it in PinDown, our automatic debugger of regression failures. PinDown predicts bad commits before simulation starts. PinDown then validates bug reports by repairing faulty code to make the test pass again before bug report is issued.
Yassine Eben Aimine, Field Applications Engineer, and OneSpin, A Siemens Business, spoke about leveraging AI/ML in OneSpin.
AI is the ability of non-organic life to perform tasks often attributed to human intelligence. It is typically done by silicon chips. ML is the process by which systems can learn from data, to recognize patterns. Use cases where learning patterns from data can be useful are image classification, object detection, tracking or alignment, face or person detection or recognition, speech recognition, and EDA!
OneSpin 360 products includes apps for ML, and ML in apps. ML design verification includes SystemC formal verification, and FPU app. Floating-point computations are increasingly important for AI apps. OneSpin FPU app can formally prove correctnes. There are OneSpin connectivity and register apps.
Accelerating verification and implementation
Frank Schirrmeister, Senior Group Director, Solutions & Ecosystem, Cadence Design Systems, talked about accelerating verification and implementation with ML for EDA.
Intelligent systems require ubiquitous hyperconnectivity. EDA enables AI/ML designs. There are optimized flows to enable AI/ML chips and systems (for users). AI/ML is enabling EDA too! AI/ML can be used to increase the productivity of EDA flows. There are optimized flows to enable AI/ML chips and systems. EDA keeps design cost in check. We are now targeting high-effort aspects of the design flows.
AI/ML provides opportunities in EDA. These can be across functional verification, digital implementation, library characterization, custom IC implementation, design for manufacturing, PCB synthesis, and system design and analysis. Verification is part of chip development efforts. ML also comes in functional verification. Test run from regression specification is generated from ML model. Regression is finished faster, and with same coverage.
ML in functional verification accelerates verification throughput by reducing the simulation cycles with matching coverage on randomized test suites. Cadence’s Xcelium-ML provides up to 5x efficiency at same coverage. There is smart proof in formal verification. Cadence has third-generation JasperGold formal verification platform.
ML is used for better performance and productivity. ML optimizes delay prediction. All optimization is done on customer data, at customer site. With the Intelligent Chip Explorer, ML optimizes the flow (SI congestions). It adjusts tool and library options, and constraints, and parallel runs in cloud.All optimization is done on customer data, at customer site. Cadence Cerebrus Intelligent Chip Explorer re-imagines chip design.
AI/ML brings productivity improvements. In functional verification, there is up to 5X reduction in simulation cycles (same coverage), and up to 4X (2X average) better out-of-the-box proofs. For digital implemetation, there is up 20 percent better PPA, and up to 10X productivity. Library characterization sees accelerated library development. Example: 47 percent of libs interpolated 98 percent+ pass rate.
In custom IC implementation, there is accurate response surface model of the device or block, and layout group prediction. DFM sees hotspot prediction, and in-design detection and fixing. PCB synthesis sees faster design closure and routability. System design and analysis sees reduction in simulation time.
AI-based test content synthesis
David Kelf, CEO, Breker Verification Systems Inc., discussed AI-based test content synthesis.
Test content composition efficiency is critical. A transformational approach is test content synthesis. Breker technology includes test suite synthesis and Verification OS. Two test suite synthesis components used AI-based planning algorithms. Planning algorithms are at the heart of optimized test generation and test scheduling.
There are AI-based planning algorithms and verification. You can solve for a plan of steps that will achieve outcomes. There are AI planning algorithms for test generation. Breker patented scheduling synthesis interleaves tests across resources. There is need to ensure resources are used correctly, and possible bottlenecks are exercised. This is another opportunity for end-in-mind synthesis.
Harnessing analytics for electronics industry renaissance: Lip Bu-Tan, Cadence
CadenceLive India 2021 was held recently. Delivering the opening keynote, Lip Bu-Tan, CEO, Cadence Design Systems Inc., and Chairman of Walden International, discussed harnessing the power of analytics to drive the electronics industry renaissance.
There are exponential opportunities today. The industry trends are 5G, hyperscale computing, AI/ML, autonomous vehicles, and industrial IoT. 5G is ramping up, and several new devices are now available. In autonomous vehicles, L2 and L3 are already present. L4 will come later, and L5 is awaited. Industrial IoT is increasingly proliferating. AI/ML is influencing everything. Hyperscalers are the most exciting. Trends are driving the needs for high-performance compute, high bandwidth communications, and high density storage. Analysts are predicting double-digit growth for semiconductors.
A few years ago, some people were thinking that semiconductors was a sunset industry, but not any more. The data-centric era is driving the renaissance in semiconductors. We are currently facing supply chain issue, due to overwhelming demand. It is a great time to be in the semiconductor and electronics industries.
Data driving silicon renaissance
Data is driving the silicon renaissance. Data generated in the last two years has been 90 percent. Less than 2 percent of data is analyzed today. It will probably go down to 0.5 percent over the next five years. There is 80 percent of unstructured data. There is over 400X increase in data over the next decade. In data processing, there are data centers, servers, in-memory, and Big Data. For data analysis, there is need for filtering and making sense of the data. Wireless and wired transmission takes care of the data transmission. DRAM, NVM, etc., are driving data storage.
Hyperscalers are blazing the trail. Hyperscaler capex was estimated at $120+ billion in 2020. There is end-to-end participation in the data cycle. It is driving innovation for new technologies, such as compute, connectivity, storage, packaging, and software-defined. All of this is pushing the design envelope for custom silicon, advanced process nodes, latest IP protocols, advanced packaging, and multiphysics. System-level optimization is needed for integration across compute, networking, memory, storage, and software.
AI is a key generational trend. We are at the very beginning. Data is sent for deeper analysis to the cloud data center using AI. Powerful compute analyzes the data in the cloud. There are some issues with cloud-heavy, edge-light configuration, such as privacy, bandwidth and latency. Eg., banking and medical data may not be all sent to the cloud. To address this issue, more and more AI processing is moving to the edge. There is retraining at the edge. Edge analytics and real-time decision making is also possible. This is important for surveillance and autonomous vehicles.
There are several other secular growth drivers. These are increasing design complexity, more IP blocks, shift-left paradigm, electrification of vehicles, system companies building silicon, advanced nodes, advanced packaging, silicon startups, and Apac. EDA spend as a percent of semiconductor R&D reached about 18 percent in 2020. Design starts by technology nodes are expected to grow 22.3 percent CAGR for <=7nm nodes from 2020-2027, and 0.5 percent CAGR for >7nm nodes from 2020-2027.
Cadence’s intelligent system design strategy is perfectly balanced for consumer, hyperscale, mobile, communications, automotive, etc. Cadence applies pervasive intelligence. It is cloud-enabled and has partnerships with ecosystem leaders. Cadence is doing organic innovation, as well. There is the Palladium Z2 and Protium X2, as well as Tensilica Vision Q8 and P1 DSPs. There are also the Clarity 3D Solver Cloud, Allegro X, Spectre FX Simulator, and Sigrity X.
Cadence focuses on design excellence. This applies to More Moore and More Than Moore, best-in-class engines, complete platforms, design and DSP IP, ML powered, etc. It has digital, custom, and verification platforms, and IPs.
Advanced packaging
Advanced packaging holds the key to heterogenous integration. Moore’s Law is slowing down. There are talks about modular vs. monolithic. This enables optimal process node selection. Chiplets provide challenges and opportunities, and are very promising. A platform solution is essential. Advanced packaging is a massive growth market at 32.5 percent CAGR up to 2025. 3D IC development and design is also happening.
System analysis leads to building out a multiphysics platform. There is integration with implementation and verification. Cadence also has a multiphysics platform. Cadence and Green Hill have a software partnershio for system security. This is a $3 billion systems market opportunity. They can deliver integrated hardware and software system solutions.
Pervasive intelligence forms the core of Cadence. Using AI/ML to increase productivity of EDA flows, there is the data analytics platform, and flows to enable optimized AI/ML chips and systems with the best PPA.
Cadence is also expanding cloud flexibility. There are customer- and Cadence-managed clouds. Virtual cloud products, such as Virtuoso ADE Cloud and Clarity 3D Solver Cloud are new additions. This is an example of continuing innovations on the cloud.
Cadence Cerebrus to revolutionize intelligent chip design
Cadence Design Systems Inc. introduced the Cerebrus intelligent chip explorer last week. It is said to be the fist ML-enabled digital full flow that can revolutionize the intelligent chip design strategy.
Rod Metcalfe, Rod Metcalfe, Product Management Group Director, Digital & Signoff Group at Cadence, said the Cerebrus intelligent chip explorer marks the start of the next revolution in digital chip design where machine learning (ML) plays an important role in making the design process dramatically faster.
With the addition of Cerebrus to the broader digital product portfolio, Cadence is extending its digital design leadership with the industry’s most advanced ML-enabled digital full flow, from synthesis through implementation and signoff.
Chip design challenges
So, what are chip design challenges Cerebrus is trying to solve via ML? Metcalfe said the process to design chips is long and complicated. Couple the process with the increased number of chips in today’s electronics, and proliferation of emerging technologies, and engineers quickly find themselves in a design bottleneck.
Cerebrus is all about improving productivity through ML and scalability via the cloud. ML automates chip design processes so that engineers can complete projects “intelligently”, faster and with fewer mistakes. The cloud provides engineering teams with access to massive compute power so they can rapidly meet complex design requirements.
Customers can leverage the following Cerebrus capabilities to achieve improved productivity:
Re-inforcement ML: Quickly finds flow solutions human engineers might not naturally try or explore, improving power, performance and areas (PPA) and productivity.
ML model re-use: Allows design learnings to be automatically applied to future designs, reducing the time to better results.
Improved productivity: Lets a single engineer optimize the complete RTL-to-GDS flow automatically for many blocks concurrently, allowing full design teams to be more productive.
Massively distributed computing: Provides scalable on-premises or cloud-based design exploration for faster flow optimization.
Easy-to-use interface: Powerful user cockpit allows interactive results analytics and run management to gain valuable insights into design metrics.
Now, isn’t this what the competition is also doing? Then, how is Cerebrus better? He said that Cerebrus is differentiated because it uses automated, re-inforcement learning-driven full flow optimization to generate better PPA more quickly, improving engineering team productivity and making more effective use of the available compute resources.
Secondly, Cerebrus offers a re-usable model for faster convergence on the next design. Lastly, Cerebrus provides a replayable result using the customer’s production flow environment.
Improving PPA
Next, Cerebrus can improve PPA and productivity across many nodes and multiple end-applications. Metcalfe added that the powerful combination of Cerebrus and the Cadence RTL-to-signoff flow improves engineering productivity by up to 10X versus a manual approach while also providing up to a 20 percent PPA. These gains are made possible by the unique Cerebrus reinforcement machine learning engine. Customers can utilize Cerebrus across a variety of process nodes and several end-apps, including consumer, hyperscale computing, 5G communications, automotive, and mobile apps.
Now, power, performance, and area scaling (PPA) is no longer sufficient. The focus is on power efficiency, performance, area, cost, and time to market. How is Cadence addressing those? He said SoC designs are quickly migrating to new process nodes, and rapidly growing in size and complexity, leaving engineering teams working tirelessly to keep up. The whole chip design process must become more automated, improving the productivity of engineering teams so that new products can be delivered to market on schedule.
By using completely automated, machine learning-driven RTL-to-GDS full flow optimization technology, Cerebrus can deliver better PPA results more quickly than a manually tuned flow, which improves engineering team productivity.
Cerebrus uses the latest distributed computing technology resources, either on-premises or in the cloud, to enable efficient and scalable chip implementation. Also, design teams using Cerebrus can support more SoC projects, enabling products to get to market more quickly.
Finally, he elaborated on Cadence’s Intelligent Chip Explorer and Intelligent System Design strategies. The Cadence Cerebrus Intelligent Chip Explorer is a new machine learning (ML)-based tool that automates and scales digital chip design, enabling customers to efficiently achieve demanding chip design goals. Cerebrus is part of the broader Cadence digital full flow, providing customers with a fast path to design closure and better predictability. The new tool and the broader flow support the company’s Intelligent System Design strategy, which enables pervasive intelligence for design excellence.
EDA software adoption by IT companies contributing to growth: Dr. Wally Rhines
The electronic design automation (EDA) industry revenue increased 12.6 percent in Q2-2020 to $2,783.9 million, compared to $2,472.1 million in Q2-2019, with most categories logging double-digit increases, as per the Electronic System Design (ESD) Alliance Market Statistics Service (MSS).
The four-quarter moving average, which compares the most recent four quarters to the prior four quarters, increased by 6.7 percent. The ESD Alliance is a SEMI Technology Community.
Dr. Walden (Wally) C. Rhines, Executive Sponsor, SEMI EDA Market Statistics Service, President and CEO, Cornami, and CEO Emeritus, Mentor, A Siemens Business, said that the EDA industry is experiencing amazingly strong growth right now, at least through the second quarter.
“We just reported 12.6 percent worldwide growth in revenue compared to the same quarter as last year. The last four quarters show growth of 6.7 percent. In the second quarter of 2020, every category tracked by the ESDA Market Statistics Program grew in double digits, except PCB design and services. Even so, PCB is still on track to be the fastest growing segment in 2021 with 12.4 percent growth in the last 12 months.”
Right now, all the segments are increasing. Will this trend continue, going forward?
Dr. Rhines said: “Of course, no one can predict the future. But, the underlying fundamentals causing current growth suggest that this is not a short-term effect. The biggest contributor right now is the adoption of EDA software by companies that have not historically designed their own electronics. That includes the IT community of companies like Google, Facebook, Amazon, Alibaba, and many more. In addition, the other systems companies in areas like automotive electronics are doing their own chip and board designs, while continuing their dependence upon tier one providers like Bosch, Denso, and many more.”
So, what is the growth likely for EDA during 2021? According to him, Japan grew at a very strong 9 percent rate in Q2-20 versus Q2-19. But, for the last 12 months, it has been flat. Korea EDA revenue decreased about 10 percent over the past 12 months, compared to prior years, and was flat in Q2-20 vs. Q2-19.
And, how are the semiconductor markets in Korea and Japan looking right now? Dr. Rhines noted that Japan is relatively flat. Korea has easier comparisons with last year, since the decrease in semiconductor revenue in 2019 was heavily influenced by memory price declines. He would expect that Korea will grow its semiconductor sales more than the overall world average in 2020 due to some recovery in memory pricing, influenced by the strong demand for server capacity in data centers.
Logic performance
Next, will logic performance improvement at fixed power slow down in 2021? How do you get around that? Dr. Rhines said that semiconductor logic revenue was relatively flat in 2019 despite the overall semiconductor market decline. It appears to be continuing that trend in 2020. The year 2021 will depend upon a post Covid-19 economic recovery. That is by no means certain, and it’s probably influenced by other factors, such as the elections in the USA.
Will there also be more heterogeneous integration, enabled by 3D technologies? “Absolutely! Heterogeneous integration is growing rapidly,” noted Dr. Rhines. And, multi-chip 2D and 3D packaging has made many new capabilities possible. Integration of PCB layout tools with IC design environments also helped. The support of foundries, like TSMC, with their “3D Fabric”, has helped too. Chiplets are an interesting extension to this packaging capability. It is interesting to see what AMD and Intel are doing in this space.
NVM and edge AI on the rise
Further, does the industry see the emerging non-volatile memories on the rise? He added that non-volatile memories are currently leading the transistor cost learning curve for the semiconductor industry. About 512 layers in flash memories is achievable, making for amazing NAND flash capacity in a single package. At this same time, it is a period of growing interest in new memory process technologies, like MRAM, ReRAM, FRAM, and more. Cost per bit continues on the long-term learning curve, and the continued doubling of total memory storage, both appear very predictable.
On the same token, I asked for his thoughts on the edge AI chip industry, going forward. As per Dr. Rhines, edge AI is entering a new wave of growth. It is inevitable that the intelligence in the cloud will make its way downward to embedded systems. It always has in the past as silicon capability allows us to compute locally that which we used to compute centrally in mainframes or servers.
“Dozens of new post-Von Neumann neuromorphic computing architectures have been funded as chip startups starting in 2017 and the pace continues at about $2 billion of venture investment per year in these companies. Working for one of these companies, Cornami, that promises orders of magnitude further performance and power dissipation improvements gives me some visibility into this trend. It is not slowing down.”
Finally, does the NAND industry need to consolidate to generate sufficient returns? He said that most semiconductor mergers and acquisitions are no longer driven by manufacturing economies of scale, unlike the 1970s and 1980s. Memory manufacturing efficiency does, however, depend upon scale. Samsung has nearly 30 percent of the market, and is very profitable, although, the commodity nature of memory makes the revenue and pricing more volatile than non-memory semiconductor products.
“Behind Samsung, we have Kioxia (formerly Toshiba), Micron, Western Digital (SanDisk) and SK Hynix. I suspect that harvesting economies of scale from merging any of these companies would be difficult because of the differences in products, processes and geographic locations. But, it could certainly happen!”
PRADEEP's TECHPOINTS 