global semiconductor industry

Strengthening global semiconductor supply chain in an uncertain era

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Semiconductor Industry Association (SIA), USA, organized a conference on strengthening global semiconductor supply chain in an uncertain era. As the US Congress considers funding domestic semiconductor manufacturing and research, a new joint study by the Semiconductor Industry Association (SIA) and Boston Consulting Group (BCG) analyzed how such investments will help address the vulnerabilities in supply chain, and ensure more of the essential chips USA needs are produced domestically.

The report, titled “Strengthening The Global Semiconductor Supply Chain in an Uncertain Era,” finds that while the current global semiconductor supply chain structure based on geographic specialization has enabled tremendous innovation, productivity, and cost savings over the last 30 years, new supply chain vulnerabilities have emerged that must be addressed by government actions, including funding incentives to boost domestic chip production and research.

The participants were Antonio Varas, Senior Partner and MD at BCG, Raj Varadarajan, Senior Partner and MD at BCG, Ms. Susie Armstrong, Senior VP, Engineering, Qualcomm Inc., Ms. Jackie Sturm, Corporate VP, Global Supply Chain Operations, Intel Corp., and Dr. Chad Bown, Reginald Jones Senior Fellow at the Peterson Institute for International Economics. The session was moderated by Falan Yinug, Director of Industry Statistics and Economy Policy at SIA.

Semicon highest in R&D, capital intensity
Talking about the report, Raj Varadarajan, BCG, said that the semiconductor industry ranks high, simultaneously, in R&D and capital intensity. Pharmaceuticals is perhaps, the closest to the semiconductor industry. Also, the global semiconductor supply chain based on geographic specialization has delivered enormous value for the global industry.

Different parts of the globe have different shares. There was also 35-65 percent reduction enabled in semiconductor prices. He added there are five key vulnerabilities in the semiconductor supply chain. These are high geographic concentration of certain activities, geopolitical frictions. national self-sufficiency policies, talent constraints, and stagnation on funding of basic research.

Antonio Varas, BCG, added there are 50+ points of high geographical concentration across the supply chain. One sensitive area is manufacturing. Most of the global manufacturing capacity is concentrated in East Asia, such as China, Taiwan, Japan, Malaysia, etc. East Asia + China concentrate ~75 percent of the wafer fab capacity, and ~90 percent of advanced logic capacity. And, <10nm is focused in Taiwan. There is need to enhance supply chain resilience through a focused approach. Eg., US minimum viable capacity for advanced logic (<10nm).

Focus on R&D
Ms. Susie Armstrong, Qualcomm, said R&D is critical. If you don’t have R&D, you have really nothing to manufacture. This is an area where USA has led in. We need to ensure R&D continues to drive manufacturing. Mature node chips are also essential. We make Snapdragon in leading-edge technology nodes. We need to have mature components. Supply chain is also really complex. It is very intertwined. We have to look at allies and maintaining strategic access for some chips from different parts of the world. We are also involved in various conversations around semiconductor manufacturing.

Ms. Jackie Sturm, Intel, said that it is developing world-changing technology. Today, supply chains are crucial. The semiconductor industry is extremely integrated. As an IDM, there is state-of-the-art logic and MCUs produced around the world. She agreed that R&D is crucial. Over half of Intel employees are based in the USA. That’s also the center for R&D. We are keen on growing domestic operations. Pat Gelsinger, CEO, re-iterated domestic manufacturing. US and global capabilities are crucial to support the needs of our customers. Teams have accumulated skills over the years. By harnessing the collective capability across the ecosystem, we have been able to deliver chips.

The semiconductor industry also faces many risks. These are geopolitical uncertainty, pandemic, cyber/IP security threats, natural disasters, environmental regulations, disrupted logistics, and additional emerging risks. Demand shot through the roof to support WFH, education, etc. We were able to provide for customers. Business continuity ensured the delivery to Intel’s customers. We are actively engaging to do more, going forward. Intel’s supply chain enables the future. We are preparing for the next 10 years in advance. Its vital the business environment remains stable in the future, for Intel and all the other players.

Reasons for investment
Dr. Chad Brown said the report is diplomatic in nature. It is all about uncertainty. There is also the policy uncertainty created by governments. China is doubling down in promotion of their own domestic demand. A previous report said that about a quarter of US revenues come from Chinese makers. Revenue is what drives R&D. There is also a big shift in US policy. Other countries won’t just subsidize more. We also need to increase manufacturing within the USA. If you also want the manufacturers to do something new, you maybe, have to pay them more. Some manufacturing facilities, such as TSMC, need to have extra costs involved in areas, such as packaging.

Ms. Susie Armstrong said USA has traditionally led in the R&D area. It is an area that puts USA in a relatively good position. There is lot of fundamental technology leadership in the USA. There used to be Bell Labs, Lucent, Nortel, etc. We need to fund and make the world’s electronic devices. Keeping access to the global markets and supply is critical. There may be subsidies for R&D, as well. People need to look at the scale of the various companies. Decoupling from China also gets us worried. Security really starts with the R&D, and it is also linked with manufacturing.

Ms. Jackie Sturm added that for manufacturing, the need to build a fab is a major decision. There needs to be reasons to be considered for doing an investment. As you think about putting a multi-billion investment on the ground, we think about the workforce capability. Do they have enough technical background to work with technical equipment? It also leads to the R&D topic. Does the education policy look at that? Do the tax and trade laws look at power and water? Is there political stability, and perhaps, a strong industrial policy?

Varas said BCG took a long-term perspective. The growth is 5 percent CAGR for the next decade. The industry definitely needs to add more capacity. The industry and downstream needs a more diversified manufacturing scenario. It should be good for the entire industry.

Varadarajan added that the capacity is relative to demand. When you have a large number of players, there can be boom-bust. The industry then becomes consolidated and capex consistent. On the demand side, the industry has more utilization discipline. The industry had also switched to repurposing during the pandemic.

Confluence of AI/ML with EDA and software engineering: ISQED 2021

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The International Symposium on Quality Electronic Design (ISQED) 2021 started today virtually in the USA. It is the premier electronic design conference. . ISQED bridges the gap between electronic/semiconductor ecosystem members, providing electronic design tools, IC technologies, packaging, assembly and test, semiconductor, etc., to achieve total design quality.

ISQED is the leading conference for design for manufacturability (DFM) and quality (DFQ) issues. ISQED emphasizes a holistic approach toward design quality to highlight and accelerate co-operation among the IC design, EDA, wafer foundry and manufacturing communities.

Arun Venkatachar, VP, AI and Central Engineering, Synopsys, presented the keynote on the confluence of AI/ML with EDA and software engineering. He talked about how AI/ML can help in chip design and product development.

Chip design a tough game to play. There are deluge of challenges. There is debug, DFM, DPT, etc. We can leverage AI and Big Data to design silicon faster, and more cost-effectively. There are connected analytics, insights, time-series, patterns, etc. Algorithms generate a ton of data. Data has become the epicenter. Synopsys has three different vectors of innovation: enabling AI chips, AI-enhanced tools, and AI-driven apps. AI/ML looks at the data.

Synopsys has AI-enhanced tools and apps. These improve the performance, QoR, and productivity, beyond what is possible algorithmically. They are also using RL for design space optimization. ML enables new way of thinking about design.

Another example is VC LP, or faster violation debug with ML. There are manufacturing-related opportunities. AI/ML use cases have finally gone into production at customers. Customers are also more savvier, and understand the importance of good data diligence. Deployment of AI solutions are different than current EDA product deployments. However, not all problems can be solved with AI/ML. Confluence of data, algorithm, etc., is need.

AI/ML can also help build better EDA products, leading to better software engineering. Systemic complexity growth has been happening in product development. Products and engineering complexity is also increasing. We need to improve the release quality and predictability, improve R&D productivity, etc.

Quality can be managed by design, such as preventive measures and built-in quality, validation, such as test and failure analysis, and defect management, such as responsiveness and support. Path to actionable insights need data points, Big Data, and intelligence. AI/ML takes the insights and starts to predict. We can also do quality-by-analytics. You need to know the defects, tests, and code. Insights enable shift-left in quality and improves productivity. Shift-left strategy is enabled by quality-by-analytics and information at the disposal of the developer.

Synopsys has ML-infused apps. There is CodeQuarry, Plan Better, Failure Triage, Bug Triage, Intelligent Test Selection, Release Analytics, and Predictive Score. An example is the code hotspot analysis tool. We need to identify the functions that are hot. This will prioritize the R&D work that yields high RoI.

In bug triaging, new bugs are automatically compared to others, and clustered, based on stack similarity. There is also the check-risk analysis. We need to identify who should review the code change, whether dependent code modules need to be considered, related bugs, etc. Today, you can link and search collaterals across the organization, using NLP.

You need to establish a unified data management strategy. Streaming data access on a unified data platform can enable a true ecosystem via data sharing. Connected analytics can yield key insights and open up new avenues. Tap into the convergence! It all starts with good data-diligent approach and process management. Use AI/ML as a new paradigm shift to improve quality, productivity, and efficiency.

DRAM and NAND show building strength

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Memory markets struggled through a mixed 2020, but appear to have emerged, strongly positioned. Can 2021 be the beginning of another memory super-cycle?

Walt Coon, VP of NAND and Memory Research, Yole Développement, Semiconductor, Memory & Computing Division, said NAND was in early stages of recovery exiting 2019. A record year was expected in 2020. Profitability during the downturn was high. DRAM was in downward trajectory. Recovery was expected to commence in 2020. The pandemic led to H1-2020 demand pull-in. It was a weaker H2 for both NAND and DRAM. Work- and learn-from-home transitions led to strong notebook/Chromebook usage. Covid-19 impacted memory profits. Memory markets exited in weaker position during 2020.

Market outlook
Speaking about the market outlook for 2021, Mike Howard, VP of DRAM and Memory Research, Yole Développement, Semiconductor, Memory & Computing Division, said there was significant capex cut off in 2020 for DRAM and NAND. This is expected to grow 20 percent in 2021, and 2022, respectively. Suppliers also cannot pull back on their capex as other suppliers may come into play.

DRAM bit density is expected to grow 13-15 percent. Similar for NAND, growing at 20 percent. DRAM production is forecast to grow 18 percent in 2021, and 19 percent in 2022 based on recent capex, and expected growth in bit density per wafer. Significant adjustments could be made in 2022 production growth, and could reach over 22 percent. NAND production is forecast to grow 32 percent in 2021, and 31 percent in 2022, based on recent capex and growth in bit density per wafer.

On the demand side, server shipments are likely to grow inline with 5-year average in 2021, and slightly below in 2022. DRAM content is expected to grow inline with the recent trends. NAND content growth is expected to decelerate from 2020 growth rates, but remain above the 2019 rate.

Smartphone unit shipments are likely to outgrow recent trends. It will grow 6 percent in 2021 and 3 percent in 2022. Content growth is likely to continue the deceleration of the past few years. PC shipments are likely to remain high in 2021, before falling off steeply in 2022. Content growth is expected to decelerate slowly for both NAND and DRAM.

2021 is expected to see rather high DRAM demand growth and NAND demand growth slightly above the trendline. It will be a good year for memory overall. Demand pull-ins will happen in both markets. Prices will climb through 2021, peaking in Q4-21 for NAND and Q1-22 for DRAM. NAND revenue will peak or plateau in Q4-21. DRAM revenue will peak in mid-2022. The overall memory revenue in 2021 is expected to hit $163 billion and rise to $196 billion in 2022.

RISC-V an opportunity for China to reduce risks

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2nd RISC-V Week commenced today in Grenoble and Paris, France. Ms Lucilla Sioli, Director for Artificial Intelligence and Digital Industry within Directorate-General CONNECT at the European Commission, talked about Open Source Hardware: A European Perspective.

There is a clear and increasing interest for open source hardware and RISC-V solutions in Europe. It is important to have an alternative processor ecosystem due to various reasons like uncertainty about established processor IP providers, geopolitical considerations, creation of healthy competition in processor IP, etc. From a European perspective, there is a need to help further the creation of a European ecosystem around open source hardware addressing all performance ranges and including software and tools. Ms. Sioli provided an overview of the forthcoming European initiatives in processors and semiconductor technologies, and specific information about open source hardware activities.

Ms. Sioli talked about the European Processor Initiative and the significant role of RISC-V. EU expenditure from 2021-2027 is around Euro 1,824.3 billion. There are funding opportunities for open source hardware. Horizon Europe calls for proposals will be launched in the coming months. Specific call related to the open source hardware support action will also happen. Specific call for processor design projects in lower technology readiness levels (TRLs) will follow.

Horizon Europe will re-inforce EU’s technology autonomy is electronic components and systems. It supports the future needs of vertical industries and the economy at large. Digital Europe program ensures that Europe drives the digital transformation of the economy and society. There are testing and experimentation facilities in AI hardware.

RISC-V in China
Pierre Sel, CEA, (CEA, Ambassade de France en Chine), and Didier Guy (Expertise France, Ambassade de France en Chine), talked about RISC-V in China.

Mainland China has become the main market for semiconductors, attracting companies, talents and IP to the country. With the so-called “War on Huawei”, the Chinese government doubled down on independent innovation and mastery of the key technologies. In particular, it is crucial for China to emancipate themselves from the ARM/x86 duopoly and gain autonomy in designing processors and cores.

In that respect, RISC-V represent a unique opportunity for Chinese companies to develop their own cores and IP, and reshuffle the cards in the market. We wrote on extensive study of Chinese RISC-V ecosystem, from associations, universities, research centers as well as companies, in order to better understand who are the players of that ecosystem.

There is dependance on foreign intellectual property for semiconductors. The Huawei case is a scary screenplay for all in China. It is barred from ARM licenses, acquiring design tools, barred from using TSMC and SMIC, purchasing from Mediateak, and Qualcomm for 5G, etc. RISC-V is an opportunity for China to reduce risks regarding ISA. There is significant involvement with the RISC-V International Foundation. There are 7 premier members, on a total of 13. CRVA or Chinese RISC-V Alliance is managed by the Chinese Academy of Sciences. CRVIC is another organization aiming at fostering development and adoption. It is managed by the Municipality of Shanghai.

Patent-wise, China lags behind USA, but has widened the gap with the rest of the world. In IoT/AIoT, there are concrete developments happening. Servers and data centers are expected to take 2-3 years. More time may be needed for desktop PCs, smartphones, etc.

How is RISC-V better than ARM? Many Chinese companies have partnerships with ARM. The China relationship with ARM is very complex. RISC-V can help innovate to design your own chips. There can be some arbitrary US sanctions. Also, if it takes 2-3 years for data centers, etc., the world could have moved on. However, there are significant cash capabilities with Chinese companies. The Internet giants also have the necessary talent.

Digital sovereignty
David Fraboulet and Laurent Crouzet, French Ministry of Education, Research and Innovation, presented the European digital sovereignty and open source hardware: a perspective from French research and innovation.

The industrial digital value chain provides sovereignty. Circuit design is in the middle of the cluster. You definitely need the hardware tools. Interface is done at the function layer. For that, you will need EDA tools, that are not yet easy for Europe.

New innovation requiring design know-how include specific circuits for strategic use (ASICs), security chips, FPGAs, IA dedicated chips, and later, quantum computing and hybrid quantum. RISC-V presents a fantastic opportunity. It is being adopted progressively by the majors. Hyper computing is vital for sovereignty and innovation, and a contribution from RISC-V. Core processor is one of the keys.

Cyber security key condition for Industry 4.0 adoption

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Thomas Schulz, Channel Manager CEE, GE Digital, presented cyber security as the key condition for Industry 4.0 adoption, on the concluding day of SEMI Technology Week.

With the introduction and integration of Industry 4.0 devices, platforms and frameworks to existing systems comes the issue of interoperability. In industrial environments, securing interconnectivity between diverse devices is often challenging. Difficulties in ensuring security in Industry 4.0 result also from lack of technical capabilities of connected industrial devices and systems, especially considering integration with legacy infrastructures.

Cyber security in manufacturing is very essential. Fast progress is key to enable the valid responses to cyber threats in the future manufacturing environment. Here, the dependence on networks and information systems will increase rapidly. Attacks become smarter, and therefore, they need to be protected against. The semiconductor industry and manufacturing industry can be particularly vulnerable to attacks.

There are technical fields of action for cyber security. There are mobile and intelligent systems, platforms with hosted apps, and factory as an app domain. The physical assets need to be protected. Security by design, and security by default must be guaranteed at the outset.

Industrial automation and control systems, such as SCADA, DCS, ICS, BAS, and PLCs need to be secured. The equipment used in semiconductor manufacturing includes OT, that manages and monitors the industrial process assets, and manufacturing or industrial equipment. Cyber security must protect the automation and control systems to your physical assets and equipment.

There are factors influencing the technical fields of action. The German BSI or Federal Office for Information Security, Platform Industrie 4.0, and associations, such as SEMI are well established. There is compliance with ISO/IEC 2700, IEC 62443, VDI/VDE 2182, and SEMI E169 and SNARF 6506.

The IEC 62443 security for industrial automation and control systems was adopted globally. It created a framework and common language for the end users to communicate their requirements. IEC 62443-2-4 established that manufacturers must demonstrate that security measures are incorporated in their development lifecycles across four key areas: organization, system capability, commissioning and acceptance testing, and maintenance and support.

A penetration test, also known as pen test or ethical hacking, is an authorized, simulated cyber attack on a system that is conducted to assess the security of that system, and identify vulnerabilities. The Achilles test platform is a communications robustness test platform to test and monitor network and operational parameters of devices under real-world conditions. The Achilles Communications Certificate (ACC) verifies the network robustness.

Deep packet inspection (DPI) is used extensively to prevent attacks. DPI systems should always be kept up to date. There is an important role of IDS and IPS in network security. There is also the OpShield from GE Digital to inspect, enforce, and control. You can protect OT networks structurally via virtual segmentation. It creates zones that reduce the mobility and damage of a misconfiguration, or an attacker. The time to act is now!

Holistic data and computing platform for advanced semiconductor manufacturing

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Holistic data and computing platform for advanced semiconductor manufacturing, was presented by Tom Hoogenboom, System Engineer IT, ASML, and BG Lee, Director, ASML, on the concluding day of the SEMI Technology Week.

Holistic lithography is data hungry. Chips are ‘made with data’. The position and shape of every pattern element must be set with sub-nm precision. Holistic lithography is built on data. It helps building the digital platform of the future. We also have the digital platform for patterning.

Holistic lithography is our world. It helps compute the best process and actual process windows. There are compute process corrections. The nm level is fine grained. We have now moved from PCs to central computing platform. Today, we operate the digital twin of a fab. If we go to a new node, we analyze everything that has gone on with the previous, old node.

It is important to note that nm performance can be affected by any small variant on process, equipment, etc. We need a platform for running fab-critical software. There is also the integration of software from other vendors. IT should be ready to integrate.

The key requirement is secure communications. You need to move toward a digital lithography ecosystem based on IT technologies and a single platform.

The IT pieces are there for the next node. Integration remains a challenge. Fab automation has some standards. Digital Twin is needed to calibrate the machines. The ASML digital platform provides integration, and is scalable. You also need to process the equipment and connection data.

Moving to integrated and collaborative smart systems

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John Behnke, GM, FPS Product Line, Inficon, kicked off day 3 of the SEMI Technology Week, that was on the future fab. He spoke about the evolution of smart manufacturing — integrated and collaborative smart systems.

The semiconductor industry has been on the forefront of developing advanced technologies used to fuel innovation and accelerate technology development since its inception. Its understanding and access to advanced technologies, coupled with its need to continuously improve manufacturing efficiency and customer satisfaction has pushed the industry to develop and adopt semiconductor-specific Smart Manufacturing/Industry 4.0 methodologies.

These Smart/I4.0 methodologies are heavily integrated solutions, which enhance the existing systems and capabilities. Data from these multiple systems, such as MES, yield, metrology, fault detection, process control, maintenance, and demand, integrate to create a real-time digital representation of the factory.

Smart manufacturing is based on three pillars. These are sensing, connecting, and predicting. Sensing involves the integrated real-time tool, process, and WIP monitoring. Connecting involves uniting the different and unique data sources. Predicting involves the Digital Twin-enable predictive apps.

Inficon offers FPS Smart solutions, such as Digital Twin, Factory Dashboard, Factory Scheduling, NextMove VTS, and Metrology Sampling Optimizer. Digital Twin enables the integrated apps. It is a never-ending journey of increasing the complexity and adding more information. It is the repository of everything about your digital factory.

The window to the Digital Twin real-time factory visualization is needed. Users are aligned to the immediate fab needs. There are integrated analysis tools, so you can set, track and shift the output goals. You can do historical performance charting, maintenance tracking/planning, and line linearity views. Schedulers pick the best lot for the best tool at the best time, and feed this information to lot delivery systems. This ensures factory-wide performance optimization.

Inficon’s NextMove Vision Tracking System (VTS) tracks the smart WIP movement. Dispatched material needs to be moved as per the schedule. There is integration with FabGuard to allow for SECS equipment set up. He showed some dashboard and scheduling-enabled RoI examples.

IoT end-node device built to last: IRPS 2021

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Alessandro Piovaccari, CTO and SVP of Central R&D, Silicon Labs, presented the concluding keynote on IoT End-node Device: Built to Last, on day 4 of the IRPS 2021, at Monterrey, California, USA. He spoke about the SoC near us.

There has been over 50 years of the Moore’s Law, and it is still standing. There has been an evolution toward scientific discoveries, starting from Brahe, Kepler, on to Newton and Einstein. Innovation is a long process involving deep understanding, and simple, elegant solutions.

Cross-discipline collaboration is extremely important. Every important innovation always creates a platform that can enable great possibilities in the other fields. An example is the road from light bulb to electronics, such as HP200 in 1939. This has since led to IoT connected lighting. Light bulb was indeed a rocket science.

We have put an end-node SoC as the wireless superhero. These devices are likely to have lifetime of 15-20 years, with coin cell operation, OTA upgradeability, etc. These devices are always on. The cost should be <$1 ASP. Looking at one of the end-node SoC under the hood, it uses the RF transceivers. The NVM and RAM will also scale up. It is designed at 90-40nm, and 22nm and beyond are around the corner.

There are reliability considerations with the connected lighting system. There are the IoT end-node meters (HCAs, ESLs, meters), connected LED light bulbs, etc. There is electronics reliability and aging also in play. There are software reliability standards, such as Motor Industry Software Reliability Association (MISRA). There also has to be end-node SoC secure lifecycle management.

Talking about low-power apps, there is the energy consumption in 2020 2025, with batteries now having to go off the radar. There will likely be around 20 billion battery-operated IoT nodes for about 50 billion IoT devices. The IT ecosystem electricity requirement will be around 3-4 PWh/year, increasing to ~20 percent in 2025.

The utility meters data collection is done via base stations in direct connection. Some other approaches are static aggregators and mobile aggregators. Another app is the heat cost allocators (HCA) in Europe. There is the wireless configurator and aggregator. Battery cost and lifetime of the LiMnO2 battery, soldered to the PCB, is 12 years. Main challenge is handling the transmission burst. The battery lifetime can be maximized, with LDOs only for the wireless SoC. LCD minumum voltage is 2.4V. Contrast fades during the transmission burst.

Achieving SoC-larity
So, how will we achieve the SoC-larity? We have the next-generation end-node SoC. The main challenges are cost, energy, performance, and lifetime. There is also the hardware and software development time. For energy consumption, the radio (transmission) limits the wireless activity and OTA upgrades.

Innovation is needed for circuits, systems, and network protocols. We also need a smarter Moore’s Law. We need to use multi-core and bring ML to the end node. This includes local data computation and anomaly detection, as well as predictive maintenance and enhanced security detection, network optimization, and adaptive security management.

Revisiting Moore’s Law, there are new areas, like digital, process advancements, digital-centric, circuit cleverness, analog, etc. We can still take good advantage of Moore’s Law. There is the factor of interchangeable parts. This is the fundamental ingredient for scalability, efficiency, and time-to-market. We also need to have verified open source hardware. ETH Zurich is building some of them. There is the Open-Hardware Group, of which Silicon Labs is a part. Another component is ML. There will be ML in the end-node devices.

SAW/BAW filters, and future materials technology for new filters

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Prof. Ms Amelie Hagelauer, University of Bayreuth, presented on surface acoustic wave /bulk acoustic wave (SAW/BAW) filters, and current and future materials technology for new filters, at the ongoing Technology Week, organized by SEMI, USA.

There are material challenges in mobile communications. There are increasing number of frequency bands, filter components, higher frequencies, etc. BAW resonators are using AlN or AlScN with Scandium concentrations </= 10 percent.

There are BAW resonators and filter. We can calculate the electromechanical coupling. Piezoelectric properties dominate the bandwidth. A BAW ladder-filter example, and different resonator types were shown. For SMR-BAW-technology, the silicon substrate is very important.

BAW filter.

AlScN, in comparison to pure AlN allows improved piezoelectricity with increased Scandium content. Deposition is possible using physical vapor deposition (PVD) sputtering. In the first experimental study, the simplified 1.7GHz BAW resonator designs were used. Deposition of thin films with increasing Scandium concentration was done. This led to the crystallographic characterization of the AlScN thin films. There was characterization of coupling and quality.

The initial growth conditions show a key impact on the crystal quality. The more crystallites, the lower is the preferred c-axis orientation. Size of the crystallites is also an important factor. High amount of crystals does lower BAW performance. There can be design improvements in BAW resonators using electrode frame, electrode apodization, optimized surface roughness, and optimized acoustic mirror.

For SAW, we have some basics. Especially, for SAW, temperature compensation is of interest. There are different types of TC SAW structures. Variant 1 will improve the thermal expansion co-efficient (TEC) by bonding the piezoelectric substrate to a low TEC substrate like sapphire or silicon. Variant 2 will deposit an additional material with positive temperature co-efficient of velocity (TCV).

Crystal grain-free AlScN thin films for 20 percent Scandium using PVD sputtering were shown for BAW. The results were also useful for sputtering with higher Sc content. New materials offer new possibilities, such as wide bandwidth filter, advanced LC-BAW hybrid topologies, and tunable approaches.

High frequency filter performance for the n41 band was also demonstrated. Quality factor is still lower than for pure AlN, even without crystal gains. Deposition-based limitations using sputtering might be the reason. The other deposition methods for higher crystal quality and lower loss like metal oxide chemical vapor deposition (MOCVD) or pulsed layer deposition (PLD) have to be considered. PLD is a promising approach that could allow moderate deposition rats and cost per wafer using high-frequency lasers, local stress control, and high BAW performance and crystal quality for Scandium concentration up to 40 percent.

Heterogenous integration key enabler for electronic systems

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Day 2 of the SEMI Technology Week focused on materials. Rolf Aschenbrenner, Fraunhofer IZM, presented on heterogenous integration as the key enabler for electronic systems.

There has been a diversification of semiconductor products. There is no single leading driver. Instead, we have had a fragmented growing market. Diversification has been in terms of IoT infrastructure with connectivity and data processing as the backbone, IoT, AR/VR, AI, automotive, 5G connectivity, and servers/data centers. There is growth of high-performance computing, edge computing, and embedded IoT computing, using smart sensors, localized networks, etc. There is the heterogenous integration platform for doing all of this.

Heterogenous integration refers to the assembly and packaging of multiple separately manufactured components into a higher-level assembly that, in the aggregate, provide enhanced functions and improved operating characteristics. Higher-level assembly includes homogenously integrated SoCs, SiPs, or MCMs. This involves system design, algorithms, and software.

The packaging toolbox provides the characteristics for the different use cases. The toolbox has functions for interconnecting, materials, architecture, etc. For the SiP packaging toolbox, there are the new embedded technology that interconnect via electroplating. Thin active chips are embedded into the di-electric layers. Passive components are also embedded with the chips, as are SMD components.

Challenges include the remaining di-electric thickness has been decreasing, as are the multi-material challenges. Multiple additional functions also emerge for SiP packaging toolbox. Cost is an important issue, as are customer requirements, testing, assembly, co-design, and standardization. It is important to remember that all package materials will continue to change over the next 10 years.

Compact SiP requires material knowhow, along with understanding failure. There are also plating challenges, thermal and mechanical issues, corrosion, electrical, and new semiconductor materials, such as SiC, GaN, and new Ga2O3.

Heterogenous integration drives the interconnect density. We have developed a consortium to understand the challenges of panel-level packaging. These include Amkor, Dupont, AT&S, Hitachi Chemical, Ajinomoto, Evatec, ASM, RENA, etc. Warpage and die-shift control provide process understanding that enables high-precision RDL layers (or, dielectric layers).