Semiconductor Industry Association (SIA), USA, organized a conference on strengthening global semiconductor supply chain in an uncertain era. As the US Congress considers funding domestic semiconductor manufacturing and research, a new joint study by the Semiconductor Industry Association (SIA) and Boston Consulting Group (BCG) analyzed how such investments will help address the vulnerabilities in supply chain, and ensure more of the essential chips USA needs are produced domestically.
The report, titled “Strengthening The Global Semiconductor Supply Chain in an Uncertain Era,” finds that while the current global semiconductor supply chain structure based on geographic specialization has enabled tremendous innovation, productivity, and cost savings over the last 30 years, new supply chain vulnerabilities have emerged that must be addressed by government actions, including funding incentives to boost domestic chip production and research.
The participants were Antonio Varas, Senior Partner and MD at BCG, Raj Varadarajan, Senior Partner and MD at BCG, Ms. Susie Armstrong, Senior VP, Engineering, Qualcomm Inc., Ms. Jackie Sturm, Corporate VP, Global Supply Chain Operations, Intel Corp., and Dr. Chad Bown, Reginald Jones Senior Fellow at the Peterson Institute for International Economics. The session was moderated by Falan Yinug, Director of Industry Statistics and Economy Policy at SIA.
Semicon highest in R&D, capital intensity
Talking about the report, Raj Varadarajan, BCG, said that the semiconductor industry ranks high, simultaneously, in R&D and capital intensity. Pharmaceuticals is perhaps, the closest to the semiconductor industry. Also, the global semiconductor supply chain based on geographic specialization has delivered enormous value for the global industry.
Different parts of the globe have different shares. There was also 35-65 percent reduction enabled in semiconductor prices. He added there are five key vulnerabilities in the semiconductor supply chain. These are high geographic concentration of certain activities, geopolitical frictions. national self-sufficiency policies, talent constraints, and stagnation on funding of basic research.
Antonio Varas, BCG, added there are 50+ points of high geographical concentration across the supply chain. One sensitive area is manufacturing. Most of the global manufacturing capacity is concentrated in East Asia, such as China, Taiwan, Japan, Malaysia, etc. East Asia + China concentrate ~75 percent of the wafer fab capacity, and ~90 percent of advanced logic capacity. And, <10nm is focused in Taiwan. There is need to enhance supply chain resilience through a focused approach. Eg., US minimum viable capacity for advanced logic (<10nm).
Focus on R&D
Ms. Susie Armstrong, Qualcomm, said R&D is critical. If you don’t have R&D, you have really nothing to manufacture. This is an area where USA has led in. We need to ensure R&D continues to drive manufacturing. Mature node chips are also essential. We make Snapdragon in leading-edge technology nodes. We need to have mature components. Supply chain is also really complex. It is very intertwined. We have to look at allies and maintaining strategic access for some chips from different parts of the world. We are also involved in various conversations around semiconductor manufacturing.
Ms. Jackie Sturm, Intel, said that it is developing world-changing technology. Today, supply chains are crucial. The semiconductor industry is extremely integrated. As an IDM, there is state-of-the-art logic and MCUs produced around the world. She agreed that R&D is crucial. Over half of Intel employees are based in the USA. That’s also the center for R&D. We are keen on growing domestic operations. Pat Gelsinger, CEO, re-iterated domestic manufacturing. US and global capabilities are crucial to support the needs of our customers. Teams have accumulated skills over the years. By harnessing the collective capability across the ecosystem, we have been able to deliver chips.
The semiconductor industry also faces many risks. These are geopolitical uncertainty, pandemic, cyber/IP security threats, natural disasters, environmental regulations, disrupted logistics, and additional emerging risks. Demand shot through the roof to support WFH, education, etc. We were able to provide for customers. Business continuity ensured the delivery to Intel’s customers. We are actively engaging to do more, going forward. Intel’s supply chain enables the future. We are preparing for the next 10 years in advance. Its vital the business environment remains stable in the future, for Intel and all the other players.
Reasons for investment
Dr. Chad Brown said the report is diplomatic in nature. It is all about uncertainty. There is also the policy uncertainty created by governments. China is doubling down in promotion of their own domestic demand. A previous report said that about a quarter of US revenues come from Chinese makers. Revenue is what drives R&D. There is also a big shift in US policy. Other countries won’t just subsidize more. We also need to increase manufacturing within the USA. If you also want the manufacturers to do something new, you maybe, have to pay them more. Some manufacturing facilities, such as TSMC, need to have extra costs involved in areas, such as packaging.
Ms. Susie Armstrong said USA has traditionally led in the R&D area. It is an area that puts USA in a relatively good position. There is lot of fundamental technology leadership in the USA. There used to be Bell Labs, Lucent, Nortel, etc. We need to fund and make the world’s electronic devices. Keeping access to the global markets and supply is critical. There may be subsidies for R&D, as well. People need to look at the scale of the various companies. Decoupling from China also gets us worried. Security really starts with the R&D, and it is also linked with manufacturing.
Ms. Jackie Sturm added that for manufacturing, the need to build a fab is a major decision. There needs to be reasons to be considered for doing an investment. As you think about putting a multi-billion investment on the ground, we think about the workforce capability. Do they have enough technical background to work with technical equipment? It also leads to the R&D topic. Does the education policy look at that? Do the tax and trade laws look at power and water? Is there political stability, and perhaps, a strong industrial policy?
Varas said BCG took a long-term perspective. The growth is 5 percent CAGR for the next decade. The industry definitely needs to add more capacity. The industry and downstream needs a more diversified manufacturing scenario. It should be good for the entire industry.
Varadarajan added that the capacity is relative to demand. When you have a large number of players, there can be boom-bust. The industry then becomes consolidated and capex consistent. On the demand side, the industry has more utilization discipline. The industry had also switched to repurposing during the pandemic.
The 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems (VLSID 2021) commenced virtually in India today.
Ravishankar Kuppuswamy, Corporate VP, Intel Data Platforms Group / GM, Custom Logic Engineering (CLE), Intel, presented the keynote on Digital Democratization: Driving Social Change. It is the process by which digital technology becomes more rapidly accessible to the people. The 1980s to 2000s, it was the PC era. India had a slower start in the PC space. From 2000-2010, the mobile everything era happened. By 2020, we had moved to cloud everything. We are now talking about intelligent everything, with 100 billion connected devices.
Intel India is changing rural lives, with examples like Churni in Maharashtra and Sahibganj in Jharkhand. Microsoft partnered with AirJaldi for broadband connectivity. Aakash Alokar presented common services point. The availability of technology has started to change lives. Another example is precision agriculture using AI. An example is Bairavanikunta in Kurnool. Farmers received sowing data, and dates, over the simple mobile phones via an SMS. Some of them saw 30 percent better yields.
Intel XPUs power AI in Microsoft Azure. We are collaborating for the best CPUs and FPGAs. The XPU solutions are driving the data centers of the future. Intel is building something that fits in one chip. India is home to 6 million software developers. Intel is committed to accelerate innovation and research through collaboration. There are the Intel OneAPI, Intel FPGA University and Intel Startup Program.
OneAPI is a unified programming model to simplify development across diverse industries. The FPGA University program in India, and the Startup program are supporting innovative, deep-tech startups. Accessible compute is levelling the playing field. XPUs are powering the zetascale India. We are collaborating in solutions development. There is innovation to drive social change.
Yole Développement and System Plus Consulting provided an understanding of today’s 2.5D/3D packaging market and its evolution. Intel, TSMC, and Samsung have tapped into the advanced packaging market’s growth with finite element (FE) and BE capabilities. They have achieved faster time-to-market than outsourced semiconductor assembly and test (OSATs) players for the high-end performance packaging. This strategy poses a formidable threat to OSATs.
Favier Shoo, Technology and Market Analyst, Package Assembly and Substrate, Yole Développement, said that the semiconductor industry today has only three players left with leading-edge manufacturing capabilities, namely, Intel, Samsung, and TSMC, at 7nm. How many will remain at 5nm/3nm remains to be seen.
There is leading-edge node, with steep investment cost, in the combined roadmap of 3D interconnect density and technology nodes. Front-end scaling remains a work-in-progress in the background. The market drivers of 3D/2.5D packaging market include HPC PU in servers, from TSMC and Intel in 3D SoC. The types of technologies that will evolve by 2025 include hybrid bonding, embedded Si bridge, TSV, micro-bumps, 2.5D interposers, UHD FO, etc.
Mapping the players based on technology, UHD FO has ASE Group, Samsung, TSMC, Amkor, etc. In the 2.5D interposers, there are ASE Group, Amkor, BPIL, GlobalFoundries, Intel, Micron, Samsung, TSMC, etc. For 3D stacked memories such as TSV and micro-bumps, there are Micron, Samsung, SK Hynix, etc. The embedded Si bridge has Intel and TSMC as the leaders. In hybrid bonding or bump-less, there are XPERI, TSMC, Samsung, Intel, UMC, etc.
If we look at the IP landscape in hybrid bonding for 3D SoCs, 60+ patent assignees have filed more than 1,400 patents, and regrouped in more than 400 families, related to hybrid bonding and / or 3D IC technology.
Stéphane Elisabeth, Technology and Cost Analyst, System Plus Consulting, spoke about 2.5D packaging. With identical 2019 form factor and packaging technology, Nvidia increased the performances of its data center GPU over the year.
As preliminary result, size of the interposer showed that x2 pass reticle is needed to achieve large size. The interposer and the GPU have been designed to support six HBM stacks. This could may append in the future version of the Nvidia Ampere A100. If we look at the CoWOS vs. UHD FO solution, using passive interposer or UHB FO can be a question that industrial is asking themselves. The cost relatives are the determinant factor in this choice. The cost estimation is based on several hypothesis, and not on the actual devices.
When we look at the Intel Foveros solution, there is the first application of 2.5D packaging using the interposer in a consumer device. Moreover, the interposer is for the first time active with support of all major interface blocks. The TSVs are designed for efficient power delivery. Each signal TSV is single, and power TSVs are by group up to 12 TSVs per C4 bumps.
Additionally, to power supply function, the interposer features audio codec, USB 2.0, USB 3.2, UFS 3.x, PCIe Gen 3.0, etc. There is the touch hub to support continuous activity (always-on) I3C, SDIO, CSE, SPI/I2C.
Next comes 3D packaging. For state-of-the-art memory die stacking, differences can be noticed in the change of generation that enable higher stacking potential in the high bandwidth memory or HBM2, compared to the HBM1. Change could also come from manufacturing processes from Samsung and SK Hynix.
Hybrid bonding has just started to enter the memory market with YMTC. For a long time, the technology was already used and enhanced in CIS market. The gain is not only on bit transfer rate. Specification of the memory is improved with the X-stacking of the logic. Hybrid bonding is a real game changer in this case.
As for the emerging technologies in 2.5D/3D packaging, the future will see the Co-EMIB or the co-embedded multi-die interconnect bridge solution. Co-EMIB solution is coupled with 2.5D and 3D stacking technology. If we look at the SoIC or system-on-integrated chips solution, TSMC goes beyond Intel’s solution with hybrid bonding.
Favier Shoo next presented the market forecast. The focus is on high-end segment. The high-end segment is defined as the market where an application is less sensitive to the cost, but requires smaller footprint in addition to high performance and reliability. It includes HPC, networking, and gaming. The mid-/low-end segment is defined by a good balance between cost sensitivity and performance. It includes sensing and lighting.
The high-end performance packaging market is expected to reach $4.7 billion by 2025 from $884 million in 2019, with a CAGR of 32 percent. By 2025, mobile and consumer segment will grow 40.8 percent, and telecom and infrastructure will grow by 58.4 percent. Automotive and mobility will grow 0.8 percent, and defense and aerospace will grow by 0.1 percent.
3D/2.5D packaging now essential
In conclusion, 3D/2.5D packaging has now become an essential part of the semiconductor industry, extending Moore’s Law at system-level. The 3D/2.5D integration is accelerating 3D interconnect density (3D ID) into new highs. Such is the value of 3D/2.5D packaging.
A strong adoption of end-system units in cloud computing, networking, HPC, and consumer devices, personal computing and gaming, has been observed. The trend is expected to continue. Future digital trends in end-systems require a far more intelligent and multifaceted devices. This leads to an intensive trend towards of finer pitch and 3D/2.5D integration at package level.
There is a dramatic shift in the fundamentals of semiconductor packaging. Leading companies, such as TSMC, YMTC, Xperi, XMC, Sony, Samsung Electronics and IBM) are starting to place priority on 3D IC and/or hybrid bonding IP strategy. The high-end packaging market size is valued at $0.8 billion in 2019, and projected to reach $4.7 billion by 2025, growing at a CAGR of 33 percent from 2019 to 2025.
David Jourdan, Global Sales and Support Co-ordinator, Yole Développement, was the moderator.
Takayuki Ikushima, Market Development Director, Industrial & Automotive Business Unit, Programmable Solutions Group, Intel, presented a session on Intel FPGAs enabling industrial automation and Industry 4.0, at the Intel FPGA Technology Day 2020.
Industries are going through transformation. There is now an evolution to smart factories. These are enabling downtime reduction, improved product quality and optimized operations. As per a Capgemini study over 70 percent of manufacturers have a smart factory initiative. FPGA flexibility, connectivity, and performance enable smart factory applications.
FPGA in Industry 4.0
Industry 4.0 presents more flexible and connected architecture. This opens the opportunities for implementing intelligence. Evolution to smart factories are happening in multiple phases. You need to connect the unconnected, be smart and connected, and move on to autonomous. Smart and connected devices are making their way to the factories.
Intel CPU is a major player in the industrial IT market. Intel FPGA is a market leader in industrial OT market. Together, they are driving IIoT transformation for Industry 4.0.
There is a role for FPGAs in the Industry 4.0 paradigm. Applications exist for vison-based, robotics, motion control, sensors, etc. Intel FPGA can provided TSN switch implementation. Many industrial apps now connect to the cloud for data logging, analytics, remote management, etc. Over things, edge, and cloud, FPGAs can combine many apps.
The Edge AI acceleration solutions from Intel include Corerain Nebula accelerator and the ATUS, or CVDL-m9A miniPCIe card. Cirerain is a high-performance, low-latency, and high-cost efficient AI acceleration solution. ATUS is a deep learning-based edge vision AI inference accelerator using Cyclone V FPGA.
An MLOps demo was done with AWS and LeapMind. Sample MLOps system was used to prove remotely-managed AI service for embedded IoT apps. LeapMind’s Blueoil and AWS components, such as AWS IoT Greengrass and Amazon SageMaker. It enabled multiple FPGA-based AI devices on the field to be managed and remotely updated by AWS Cloud.
Intel offers the portfolio for all three robotics activities, sense, plan, and act. At the sense stage, there is the depth camera and workload/AI accelerators. At the plan stage, Intel processor family is used. At the act stage, there are embedded FPGAs. There is also a drive-on-a-chip for robotics and drives. The reference design is an integrated drive system of single- and multi-axis field-oriented control (FOC), supporting concurrent control of upto four permanent magnet synchronous motors.
There is the TUV-certified IEC1508 functional safety data package. You can now reduce the time for functional safety certification. This includes devices, docs, IPs, and tools. A success story was the Yaskawa YRC1000 robot controller in Japan.
Among the reasons for selecting Intel FPGA were integration of custom logic, PCIe, and software applications, low-power for fanless system, monitoring position data of the encoders and cross-checking by FPGAs, reduced development time compared with ASIC, with programmability, shorter certification turnaround time, etc.
Intel offers supported protocols and IP partners. There are Intel FPGA-based time-sensitive networking (TSN) solutions, along with off-the-shelf solutions. There is the IIoT edge controller and gateway, as well, such as the eXware 707T. There are system-on-module (SoM) offerings, as well. Intel also offers the FPGA cloud connectivity kit. The base kit is certified for Microsoft Azure and qualified for AWS Greengrass.
There is the TLS 1.3 hardware security IP core from Xiphera in Finland. The cryptographic computations and key management are entirely FPGA-based, enables complete independence from software for security-critical apps.
Another solution is DOME, the IoT secure ownership management solution, from Veridify Security, USA. It offers low-touch onboarding and the end-to-end blockchain ownership management for globally distributed devices at the edge.
Let us all make smart factory for real!
Intel organized the Intel FPGA Technology Day 2020, titled: Accelerating a smart and connected world.
David J. Moore, Corporate VP and GM, Intel Programmable Solutions Group, along with Patrick Dorsey, VP & GM, FPGA and Power Products Group, Programmable Solutions Group, Intel, presented the opening session.
David J. Moore said there has been great change due to the global pandemic. Together, we can re-imagine how people and data can change our world for the better. The potential for data to transform businesses and markets has never been greater. We have seen several examples of how we use data.
Data is projected to reach 175 ZB by 2025. Mobile and cloud have changed the way we live, and the way we create and use data. We are now looking at the next era of disruption. With the exponential amount of connectivity, we are generating an exponential amount of data. There is a huge data opportunity for innovation. We are generating data at a faster rate than our ability to analyze, understand, transmit, secure, and reconstruct in real time.
There are key technology inflections. 5G will enable rich, new data experiences. There will be 5G network transformation. AI is a fundamental driver. It will convert data into an opportunity. Machine learning and range of developments continue to occur. The edge is necessary to become more intelligent. The levels of efficiency will increase with the cloudification of everything.
Intel is also unleashing the full potential of data. Software and system level approaches are also getting optimized. Storage efficiency is also growing in importance. We have a wide range of processing architectures. We have the Intel Ethernet, Intel Silicon Photonics, and Intel Tofino Switch. We are also finding ways to optimize and lower the TCO.
Intel FPGAs provide the flexibility for a rapidly transforming world. We are extending platform capabilities, intercepting evolving requirements, and enabling agile innovation. FPGAs are also ideal for agile innovation. The range of challenges that FPGAs can unlock continues to expand broadly. We are working with a range of partners. FPGAs are also powering the next-gen infrastructure, accelerating the analytics processing, etc.
At the edge, FPGAs find apps in a diverse range, from smart factory and Industry 4.0, to next-gen vision systems, aerospace, etc. Ability to process data at the source is critical to the intelligent edge.
Patrick Dorsey said that the global pandemic has not stopped innovation at Intel. Intel’s product focus is on being developer first, leadership in FPGA and custom logic silicon, and delivering end-to-end heterogenous platform. We are developing compute, connectivity and data access platforms with partners.
The Intel Quartus Prime is the FPGA design software tool. It has a comprehensive developer support, ease of use with Design Assistant, and provides upto 40 percent higher performance or 40 percent lower power with Intel Agilex FPGA designs.
For the software developers, there is the Intel oneAPI Base Toolkit. It has a unified programming model for XPUs, open specifications and standards, and ease of use.
Intel is now announcing the Intel Open FPGA Stack (IOFS), the second generation of FPGA software platform. There is faster time to innovation and accelerated deployments. There will be more details on IOFS in a separate session.
Intel also has the Custom Logic Continuum. It has the fastest time to market and highest flexibility. There is the highest performance, and lowest power and cost. There is flexible, re-usable, and agile optimization across the product lifecycle.
Intel has rapid silicon innovation that allow any compute, any connection, and any developer. There is the FPGA chiplet library. It started with the Intel Stratix. In production now is Intel’s first AI-optimized FPGA for high-bandwidth, low-latency AI acceleration.
The Intel Agilex series FPGAs with 10nm SuperFin technology offer upto 40 percent higher performance, upto 40 percent lower power, PCI Express Gen5, Compute Express Link (CXL), 116Gbps transceiver, and next-gen HBM2e.
Edge-optimized FPGAs are always going to be a focus area for Intel. They have long product lifecycle, continuous software support, and continuing IP and solution development.
Intel is also announcing the industry’s newest structured ASIC. We are introducing the Intel eASIC N5X device family. It is the first structured ASIC with Intel innovations. There is the FPGA-compatible hard processor system. It has upto 50 percent lower core power compared to the FPGAs. There are smaller form factor custom packages. The optimized TCO supports Intel’s custom logic continuum from FPGA to structured ASIC, on to ASIC platforms and solutions.
Intel has also invested in growing their leadership in the SmartNIC market. Intel FPGA-based SmartNIC products include the Intel FPGA SmartNIC C5000X platform architecture, which helps you to supercharge your cloud data center, and the Silicom FPGA SmartNIC N5010 that allows multi-workload acceleration for the network core. These are transforming the network and the cloud.
These are just some of the many innovations Intel has developed this year. We are solving many real-world challenges together. Intel FPGAs are accelerating key transitions. Accelerate the future with Intel.
Intel and IoT Solutions Alliance presented a session titled — Deployed at the edge: Telemetry and video analytics in Industry 4.0, which was powered by Embedded Computing Design.
The speakers were Andy Smith, Partner Alliances Director, Arrow Electronics, Daniel Collins, Senior Director IoT Solutions & Technology, ADLINK, Toby McClean, VP of IoT Technology and Innovation, ADLINK, Avi Kewalramani, Lead Product manager in Azure Live Video Analytics, Microsoft, and Ryan Berry, Cloud Solution Architect, Microsoft.
Machine telemetry and video analytics are two big trends today. Ryan Berry, Cloud Solution Architect, Microsoft, said there is need to understand how they work together.
Avi Kewalramani, Lead Product manager in Azure Live Video Analytics, Microsoft, said that video analytics is a growing industry. Video analytics is applicable in retail. You need to know what customers do inside stores. There is a use case in passenger counting at train stations. Other industries are healthcare, private sector, etc., where they see that the assets are protected. Video analytics has many use cases across industries.
Daniel Collins, Senior Director IoT Solutions & Technology, ADLINK, added that video analytics is being leveraged across all industries. That’s also true for machine telemetry. There are tool changing issues, etc., that come into play. From a video analytics perspective, there is quality of inspection, etc. The industry we are seeing the most impact is in the distribution sector, for video analytics.
Andy Smith, Partner Alliances Director, Arrow Electronics, said the biggest challenge is in Industry 4.0, as IT and OT have co-existed for a long time. With Industry 4.0, companies are seeing the benefits of bringing IT and OT together. The business case should be the driver.
Toby McClean, VP of IoT Technology and Innovation, ADLINK, added that the challenge is the human factor to deliver change. Technology and skills required are changing rapidly. The pace of change is immense.
Ryan Berry said customers look at device connectivity options. What path is the correct one to take? What technology will be around for the long haul?
Avi Kewalramani added that people need a breadth of skills for video analytics. There are different kinds of ingestion protocols, etc. The system designer also needs to understand the IoT. You need to have the right AI model, as well.
How can SIs leverage their domain expertise and IP into these IoT edge apps? Ryan Berry said that the IoT edge can be used. The industrial PC should be able to run services, and provide benefits to the customers.
Avi Kewalramani added that for video analytics, there is a platform for developers to come and build on top. It gives pluggability on the edge. All the security, manageability, etc., of Azure is in the platform. Addition of cameras brings distinct advantages. You can publish things on the edge, instead of going to the cloud.
Toby McClean noted that skill set gaps need to be addressed, as well. Getting the data from the edge can help normalize it, and you don’t adjust for different data models. Data integration is very important. Fusing and making data available is very necessary.
Andy Smith gave an example of how they are focused on monitoring some CNC machines in manufacturing plants. They put together edge monitoring machines in the plant. The data is combined with data from the other machines. You can start to deliver additional insights.
Daniel Collins added there is difficulty in making projects a success. There is lot of trial and error. There should be some experimentation. Unless there is actionable feedback, teams may fail.
Avi Kewalramani noted that there must be partnerships. There is a pluggable platform, where you can build upon. They should give plug-and-play models. AI developers can go and solve problems for the customers.
Ryan Berry added there should be unique capabilities for customers who can extend the capability of the edge appliance, and do more interesting things. They can make it easy for customers to manage the edge devices. Edge capabilities should be really powerful.
Toby McClean said best way to fill the gap is to have an open platform, so that people can interface, eg., different cameras. The open platform can plug in an algorithm. Specific pieces of a project should be used to build. You may choose to integrate. You can build several other components of the system. The innovation around the pluggable platform is really important. Avi Kewalramani agreed with the pluggability of the open platform.
Andy Smith noted that OT system integrators have great expertise. They can embrace new technologies. That requires a breadth of technology skills. Toby McClean said there is need to build domain expertise, and add to the platform.
There are potential business opportunities. Ryan Berry said SIs have the expertise of handling challenges and get data out of them. Microsoft can help accelerate some of those.
Industry use cases
Andy Smith said the business premise is to think big, and start small. You can spend the second half of the time to customize the production solution. People learn all the time that the device or technology they earlier bought, isn’t the right fit. We should also need to see how the actual users interact with the solution.
Ryan Berry added that there should be some opportunities identified. Starting small is really important, and go on later to expand the solution.
Avi Kewalramani noted that there was a traffic monitoring solution deployed. Real-time analytics need to be provided for the parking lot. Every video image has to be analyzed. You build small, and later, scale, for your customers.
Andy Smith said you need to understand the business problems of customers. Industry 4.0 is a specific type of digital transformation. A successful provider can help the customer undertake that journey.
Toby McClean said there should be business value delivered to customers. Eg., can you build a computer vision model fast? There are lots of opportunities.
There was a panel discussion on ‘Bending the climate curve: Enabling sustainable growth of Big Data, AI and cloud computing, at the ongoing Semicon West 2020.
The panelists were, Cliff Young, Google, Nicola Peill-Moelter, VMware, Ellie Yieh, Applied Materials, Moe Tanabian, Microsoft, Samantha Alt, Intel, and Rob Aitken, ARM. Eric Masanet, U.C. Santa Barbara, was the moderator.
Masanet opened the discussion, stating that digitalization can bring energy efficiency challenges. There is 67 percent increase in electricity use. There are dual narratives in play with energy. How much bandwidth remains to improve processor efficiency?
Rob Aitken of ARM said that computer designers think of how to get more power into the processors. They look to co-optimize all the pieces. A big chunk is done via the Moore’s Law. You have to approach a problem differently. We are going to move to more 3D-based solutions. We will see high processing with localized memory. The 3D aspect of Moore’s Law has yet to begin. We will see some serious gain in the performance. You can also stack logic and memory devices.
Ms Ellie Yieh, added that Applied Materials has been focusing on designing and making semiconductor equipment more sustainable. We look at PPAC. We also focus on chip architectures. We follow the 30x30x30 rule. There are many ways to reduce the energy. There can be better energy efficient generators.
From the silicon processing standpoint, we have a suite of integrated solutions and materials. Tungsten is not a new material. You can eliminate 40 percent voltage drop. SRAM and DRAM consume lot of power. We are working on MRAM. It is not an easy technology to integrate. It can save the standby power by 10X. There is the BCMA or voltage-driven MRAM. We will continue to push the curve.
Cliff Young from Google said there are problems and risks with all of the new technologies. We have been breaking previous abstractions. We have changed the math. We need to break abstractions at all levels. Those might be enablers for the next 10X steps. Google is not yet super deep. We need partners that can teach us about materials.
Future energy efficiency
Masanet asked can future energy efficiency can mitigate some of the problems?
Intel’s Ms. Samantha Alt said that we want the data centers to be green and clean. We also need something to consume the energy. DCs are in a position to consume energy. We also have high energy workloads. They are just executing. If we are running clean, we can run faster. We need to look at cooling, liquids, etc. We want to be able to load the backup and operate, and then, put it to sleep.
Ms. Nicola Peill-Moelter of VMware noted there are new IT innovations, such as AI, ML, etc. These are enabling de-carbonization. There should be more lifecycle studies. Virtualization has already reduced lot of e-waste. There is use of energy at the systems level. About <5W is meant for useful computing.
There is software-enabled compute efficiency. VMware has virtual machines running. The cumulative impact of compute virtualization has avoided 130 million servers deployed, etc. There are stranded compute capacities, as well. We need to look at maximizing the productivity, cost and carbon efficiency of IT. Stranded capacities are expensive for organizations.
Cliff Young added that virtualization has been a key app for IT. AI is another app. AI can be very computationally intensive. We have seen breakthroughs in AI over the past few years. There is competition to achieve higher levels of accuracy. There is an open AI. We can train the model to that level of accuracy. You have to find more efficient ways. We should not draw conclusions from the early days of AI.
Moe Tanabian from Microsoft concluded that the edge data centers have implications for energy use. We need to see better energy efficiency. AI is the foundational technology. It can power up the good and the not good. There are lots of AI-driven benefits. There are network costs as well. You need to have a lot more bigger machines. We can bring renewable energy at the edge. It can reduce the energy cost of the data center. You can achieve a better energy consumption level.
There was a plenary session, at the 2020 Symposia on VLSI Technology and Circuits, on the future of compute – how data transformation is reshaping VLSI?
Dr. Michael C. Mayberry, Senior VP, CTO, and GM, Technology Development, Intel Corp., said that the transformation of data into information will drive the next decade of compute. Moore’s Law will continue through traditional scaling, design co-optimization and novel integration. There are many critical VLSI issues to solve now and in the future.
The distant past had focused on shorter channel lengths and better gate oxides. The recent past also focused on materials, architectures and novel compute logic. Scaling has largely been driven by the integration of new architectures and materials, and limited by the precision of equipment and metrology. The future requires continued scaling PLUS heterogeneous integration, co-optimization, software-driven hardware, AI, and more novel compute logic.
What has changed?
There is an increasing amount of unstructured data. Managing unstructured data requires AI everywhere to process high volume inbound data. There is the xPU diversity to address diverse sets of unstructured data. Compute embedded happens throughout the cloud network-edge to manage QoS and security.
Customers value information! There is a need for converting the unstructured data into services, and information creates enormous value. Hardware solutions are necessary, but insufficient for optimal business models. Data volume changes the data center topology.
Data transport costs exceed compute cost. Data centers are proliferating near the edge, closer to data. There are reduced transmission costs, greater privacy, and lower latency. Within a data center, the compute/data are distributed to hardware and software implications. We are now in the distributed compute era, where we are bringing compute to the data.
The distributed network is here and growing. Network volume is doubling every ~3 years. It is growing in all aspects: connections, applications, security attacks, and speed. Proliferation requires distributed intelligence across the network. Distributed compute also drives the domain-specific architectures. Tailored architecture is used for efficiency gains. There is co-design of domain-specific language (DSL) with domain-specific architectures (DSA).
There are certain compute barriers — memory and power management. Data movement exhausts power budget. AI workloads are bottlenecked by memory. Security and system complexity also add to the compute barriers. Speculation attacks continue unabated. The industry is also pursuing automated tuning solutions.
Continuing evolution of Moore’s Law
There is continuing evolution of Moore’s Law, in terms of product and process co-optimization, features and integration, and product and workload co-optimization. We are now seeing FinFETs changing to nanowires/ nanoribbons. There is 2D-material nanosheet transistor research as well. There is better computing through chemistry with directed self-assembly (DSA) patterning. DSA enables LER and spacing variation reduction. DSA is also used for multi-pitch EUV direct print.
There is monolithic 3D transistor stacking: Ge PMOS + Si NMOS. Monolithic memory stacking comes with benefits such as multi-layer, dense, low latency, and high speed. Risks involve yield, PBTI, retention and endurance.
There is the continuing evolution of Moore’s law. Extending 3D solutions leads to system optimization. Massive compute demand leads to highly parallel workloads, high bandwidth memory requirements, large systems – reticle limited die, new system architectures and accelerators, and rapidly changing workloads driving need for agility. Heterogeneous integration improves the performance and power efficiency.
Heterogeneous integration can also be done with advanced packaging and interoperable chiplets. This leads to continued scaling and improved performance, and power efficiency.
Evolution of Moore’s law is seen in design productivity. There is the software-defined hardware (SDH) vision, where, the hardware developers support apps (vs. status quo app developers supporting hardware). There is rapid E2E exploration as well. Traditional waterfall development is replaced with correct-by-construction automation, enabling rapid E2E design exploration.
Future of programming
The future of programming is diverse and interesting. Programmer population growth requires automation to generate high-quality software that is based on the programmer intention. There is need to transform software development to meet the complexity of programming heterogenous hardware. Scaling presents a new paradigm in error detection.
There will also be co-evolution of software and hardware solutions. From graph analytics, we will be moving on to neuromorphic and quantum computing, from 2020-2035. Neuromorphic computing status today is about complex neural network topologies and ~1 billion neurons demonstrated. The challenges are neuroscience model development, algorithm development, and software and simulation tools. The opportunities are in constraint satisfaction, real-time learning, adaptive control, and complex systems modeling.
Quantum computing has qubit implementations. The status is 8 qubit types, ~100ms coherence time for SC, and ~100 major orgs investing. Challenges lie in decoherence and error-correction, low-latency qubit control, and algorithms / compilers. The opportunities exist in the molecular structure, materials science, pharmacology, cryptography, etc. Beyond CMOS, the novel devices are improving. There is improved switching efficiency, and better understanding of logic circuits.
Some really interesting news is coming out from the global semiconductor and telecom industries!
First, TSMC has plans to construct an advanced semiconductor plant in Arizona, USA. TSMC Chairman, Mark Liu has reportedly said the company is actively evaluating the US fab plan.
Ok! It is confirmed!! TSMC has announced its intention to build and operate an advanced semiconductor fab in the United States with the mutual understanding and commitment to support from the U.S. federal government and the State of Arizona.
This facility, which will be built in Arizona, will utilize TSMC’s 5-nanometer technology for semiconductor wafer fabrication, have a 20,000 semiconductor wafer per month capacity, create over 1,600 high-tech professional jobs directly, and thousands of indirect jobs in the semiconductor ecosystem. Construction is planned to start in 2021 with production targeted to begin in 2024. TSMC’s total spending on this project, including capital expenditure, will be approximately US$12 billion from 2021 to 2029.
A statement says: “This U.S. facility not only enables us to better support our customers and partners, it also gives us more opportunities to attract global talents. This project is of critical, strategic importance to a vibrant and competitive U.S. semiconductor ecosystem that enables leading U.S. companies to fabricate their cutting-edge semiconductor products within the United States and benefit from the proximity of a world-class semiconductor foundry and ecosystem.”
TSMC holds a distinct technical advantage in terms of advanced process technology, which has encouraged the U.S. government to give TSMC priority as a potential semiconductor partner, according to TrendForce, Taiwan.
TSMC recently announced net revenues for April 2020. On a consolidated basis, revenues for April 2020 were approximately NT$96 billion, a drop of 15.4 percent from March 2020, and an increase of 28.5 percent from April 2019. Revenues for January through April 2020 were NT$406.60 billion, an increase of 38.6 percent, compared to the same period in 2019.
Next, Applied Materials announced Q2 2020 results where it reported a generated revenue of $3.96 billion. On a GAAP basis, the company recorded gross margin of 44.2 percent, an operating income of $932 million or 23.6 percent of net sales, and earnings per share (EPS) of $0.82.
“As we navigate the challenges created by Covid-19, we have rallied the company around safety, productivity and keeping our customers and the industry moving forward,” said Gary Dickerson, president and CEO. “While the situation remains fluid, based on the visibility we have today, our supply chain is recovering, and underlying demand for our semiconductor equipment and services remains robust.”
Samsung Electronics reported financial results for Q1 ended March 31, 2020. The total revenue was KRW 55.33 trillion, a decrease of 7.6 percent from the previous quarter, mainly due to weak seasonality for Samsung’s display business and Consumer Electronics Division, and partially due to effects of Covid-19. From a year earlier, revenue rose 5.6% due to increasing demand for server and mobile components.
Another major, an unnamed player (see name after May 20) is launching the industry’s first 20nm radiation tolerant FPGA for space applications.
Intel Capital has announced new investments totaling $132 million in 11 technology startups. These companies are in AI, autonomous computing and chip design. The companies are: Anodot, Astera Labs, Axonne, Hypersonix, KFBIO, Lilt, MemVerge, ProPlus Electronics, Retrace, Spectrum Materials and Xsight Labs.
Elsewhere, GlobalData reports that some regulators have recognized the need to move forward with 5G spectrum allocation. In New Zealand, for example, the regulator has decided to direct allocate 5G spectrum in the 3.5GHz band to three operators — Dense Air, Spark and 2degrees, without conducting an auction. Perhaps, India can learn from this!
In the USA, the FCC has allowed major operators, Verizon, AT&T, T-Mobile and US Cellular, to temporarily borrow spectrum from the existing licensees in the 600 MHz and AWS frequency bands (1700 MHz / 2100 MHz) for a 60-day period.
Well, keep watching, folks! There may just may be more good news to share!