VLSI
Bridging digital and physical worlds with efficiency and intelligence!
2024 IEEE Symposium on VLSI Technology & Circuits will be held June 16-20 at the Hilton Hawaii Village, Honolulu, Hawaii. The conference theme is bridging the digital and physical worlds with efficiency and intelligence.
Gosia Jurczak, Lam Research, and Borivoje Nikolić, University of California, Berkeley, are the Symposium Chairs. Takaaki Tsunomura, Tokyo Electron Ltd and Mototsugu Hamada, The University of Tokyo, are the Symposium Co-Chairs.
Vijay Narayanan, IBM T. J. Watson Research Center, and Ron Kapusta, Analog Devices, are the Program Chairs. Kazuhiko Endo, Tohoku University and Sugako Otani, Renesas Electronics Corp., are the Co-Chairs.
The plenary speakers are: Dr. Ahmad Bahai, CTO, Texas Instruments, on making sense at the edge. Dr. Maryam Rofougaran, CEO, Founder, Movandi Corp., on wireless and future hyperconnected world. Hidehiro Tsukano, Senior VP of R&D, NTT Corp., on photonics-electronics convergence devices to accelerate IOWN. Dr. Kazuoki Matsugatani, Senior Director, R&D Center DENSO Corp., on mobility evolution: electrification and automation.
The conference commences June 16 with standing workshop and three parallel workshops. The standing workshop is on advancing SoC design: open-source and ML-driven approaches in the cloud. Three parallel workshops are: novel metals for advanced interconnect, high-performance mixed-signal circuits: recent art balancing the analog vs. digital effort, and biosensory breakthroughs: pioneering the future of health tech.
June 17 has short courses on tech and circuit each, and a demo session. Circuit course is on circuits and systems for heterogeneous integration. Tech course is on advanced VLSI technologies for next-generation computing. Demo session, first introduced in 2017, has 15-20 demos.
June 18 has plenary talks, regular paper sessions, WIC and YP event, and an evening panel discussion. Joint panel for circuits and technology is on: Will AI bite the industry that feeds it? It will be moderated by Tokyo Institute of Technology. There will be seven participants from Qualcomm, KLA, SK Hynix, imec, Nvidia, KAIST, and Stanford University. There will be a game-show like competition between chip heroes (panelists and audience) and gen-AI.
There will also be Women in Circuits & Young Professional Mentoring event, Test of Time award, VLSI Symposia Best Student Paper award (BSPA), with a winner each for circuits technology, and Best Demo Paper award. June 19 has plenary talks and regular paper sessions.
June 20 has regular paper sessions and luncheon talk. Luncheon talk will be on CHIPS Program and you: an R&D update for VLSI symposia. It will be delivered by Greg Yeric, Director of Research, CHIPS National Semiconductor Technology Center Program, CHIPS R&D Office, US Department of Commerce.
There are 17 technology sessions, such as oxide semiconductor applications in BEOL, backside of silicon: from power delivery to signaling, NVM — Hafnia-based ferroelectrics-1, novel channel materials for advanced CMOS, etc.
There are 29 circuits regular sessions, such as wireline circuits, power at high voltage and current, AI/ML accelerators and CiM, biomedical stimulation and imaging, etc.
There are six joint focus sessions, such as RF, mmWave, and THz technologies, processors and compute, thermal management and power delivery in 3D integration, biomedical technologies, image sensors, and memory-centric computing for LLM.
VLSI 2024 will see historical high for paper submissions, totaling 907. 41 percent of the accepted papers are from the industry. The USA and Korea have the highest number of accepted papers, followed by China and Taiwan. Other countries include Japan, Belgium, Singapore, France, Switzerland, etc.
2024 IEEE Symposium on VLSI Technology & Circuits to be held in Hawaii
2024 IEEE Symposium on VLSI Technology & Circuits will be held June 16-20, 2024 at the Hilton Hawaiian Village, Honolulu, Hawaii USA. The conference theme is: Bridging the digital and physical worlds with efficiency and intelligence.
This conference will be a fully in-person conference with Circuits, Technology & Joint sessions. All sessions — workshops, short courses, main conference, evening panel) are in-person. On-demand access of recorded presentations will be made available later. On-demand access goes live June 24, 2024.
The event has a glittering lineup of plenary speakers. They include:
- Dr. Ahmad Bahai. CTO, Texas Instruments, on sensing at the edge.
- Dr. Maryam Rofougaran, CEO, Founder, Movandi Corp., on future of 5G/6G technologies
- Hidehiro Tsukano, Senior VP of R&D, NTT Corp., on photonics-electronics convergence devices to accelerate IOWN.
- Dr. Kazuoki Matsugatani, Senior Director, R&D Center, DENSO Corp., on mobility evolution: electrification and automation.
There are two short courses. These are on:
- SC1 — Advanced VLSI technologies for next-generation computing, featuring transistor scaling, memory technology evolution, backside power delivery, and advanced packaging.
- SC2 — Circuits and systems for heterogeneous integration, featuring die-to-die connectivity, memory co-integration, wafer-scale integration, and heterogenous integration for automotive.
There will be expert speakers from TSMC, Applied Materials, Hitachi, AMD, NVIDIA, Samsung, and others.
The evening features a joint panel discussion for Circuits & Technology, featuring the impact of Generative AI on the semiconductor industry – technology, circuits, EDA.
Workshops will explore forums on topics that are adjacent to the conference. They are a combination of committee-curated topics and submissions from open call. A Standing Workshop, will be on open-source design including EDA, chiplets, etc. Parallel Workshops will be on 3D integration, novel metals for advanced interconnect, recent art in balancing analog vs. digital in mixed-signal circuits, and interfacing chips with biology.
In focus sessions, there is the Technology Focus Session 1, featuring backside of silicon — from power delivery to signaling. Technology Focus Session 2 is on oxide semiconductor’s applications in BEOL. Joint Focus Sessions will be on memory-centric computing for large language models, thermal management and power delivery in 3D integration, processors and compute, and sensors. There are 12 invited speakers in combination with traditionally submitted papers.
Demo session was first introduced in 2017. Joint between Technology and Circuits, there will be typically between 15 and 20 demos. The best demo will be selected by Symposia attendees.
For Diversity and Best Student Paper Award, a Women in Engineering forum is being planned. VLSI Symposia Best Student Paper Award (BSPA) wil be awarded to a student registered full-time at a university. There will be one winner each for Circuits and Technology.
Next spintronics beneficial to LSIs for high performance and ultra-low power
2023 Spintronics Workshop on LSI was a satellite workshop of the 2023 VLSI Symposium on Technology and Circuits, It focused on next spintronics technologies beneficial to LSIs for high performance and ultra-low power.
The workshop was organized by Center for Innovative Integrated Electronic Systems (CIES), Research Institute of Electrical Communication (RIEC), and Center for Science and Innovation in Spintronics (CSIS), as world-leading Research Center for Spintronics at Tohoku University, Japan.
Field-free SOT-MRAM
Chi-Feng Pai, National Taiwan University, presented on field-free SOT-MRAM— recent progress and challenges. Back in 2011, we had the original three-terminal device, made by HGST. A device was also made at Cornell. From 2012 to present day, there is the spin Hall-effect three-terminal device spin-orbit torque magnetic random-access memory or the SOT-MRAM. There is also the field-free issue.
There are possible field-free solutions for type-z. These are lateral symmetry-breaking, in-plane exchange bias, interlayer exchange coupling, and z-polarized spin current. However, some are incompatible with p-MTj, low switching ratio, and limited z-spin efficiency.
Lateral symmetry-breaking revisits a simple PMA structure. We have the origin of field-free switching, such as tilted anisotropy. Another one is interlayer chiral exchange coupling. We also have interlayer Dzyaloshinskii-Moriya interaction (i-DMI). The D vector is orthogonal to symmetry breaking direction. Direction of D is randomly given. We have current-induced field-free switching via i-DMI.
Challenges ahead!
Roles of tilted anisotropy and interlayer chiral exchange interaction, and their correlations with growth protocols have been largely neglected. Robust current-induced field-free magnetization switching can be realized by either mechanism, or both combined.
Growing these hetero-structures uniformly, while maintaining symmetry-breaking properties is key toward wafer-scale integration. Further reduction of field-free switching current density (0.1X) for type-z devices, without sacrificing its thermal stability, is also critical.
MTJ for non-volatile memory
Shunsuke Fukami, Tohoku University, presented on magnetic tunnel junction for non-volatile memory and more. There are opportunities for MTJ, such as STT-MRAM, SOT-MRAM, probabilistic computing, and energy harvesting.
There has been successful development of MTJ devices with tens of nm, especially in Everspin, GlobalFoundries, Intel, TSMC, Samsung, etc. MTJ scaling down to X nm remains one of the major challenges. There are tips for scaling MTJ to X-nm regime, while tailoring the performance for Flash- and SRAM-like apps.
We also have shape-anisotropy MTJ. Shape anisotropy becomes remarkable at smaller scale. T dependence of E scales with T dependence of Ms. We also have multilayered MTJ for faster switching. We can increase the anisotropy field, by increasing the number of interfaces. Hk eff increases with the number of CoFeB/MgO interfaces. Dipolar coupling becomes remarkable at smaller scale.
MTJ with large number of interfaces suppresses switching voltage enhancement with pulse width reduction. Fast switching down to 3.5ns is confirmed for 4.5nm MTJ. For retention-critical (Flash-like) apps, rely on shape anisotropy with less temperature-insensitive retention. For speed-critical (SRAM-like) apps, rely on interfacial anisotropy for less pulse-width-incentive switching.
Energy harvesting
For energy harvesting, he talked about spin-torque oscillator (STO). The STO can convert DC input to RF output. Energy harvesting can be from wireless signal or electromagnetic wave.
Mutual synchronization or phase locking comes in next. It can enhance the output signal. We can harvest energy from ambient Wi-Fi signal using mutually-synchronized STO. Challenges include adjusting the resonance frequency to Wi-Fi band (2.4GHz), and increasing generated voltage by mutual synchronization.
We are looking at synchronization of uniformally-magnetized STOs. STO-array performance is compared in parallel and series. Energy harvesting can be done using STO-arrays. In conclusion, MTJs are moving to Xnm regime. Energy harvesting can be done with wireless signal using MTJ.
There were other presentations, from Hiroaki Sukegawa, NIMS, advancing TMR through epitaxial technology: Reaching 631 percent at room temperature, Matthew W. Daniels, NIST, on magnetic tunnel junction-based crossbars: Improving neural network performance by reducing the impact of non-idealities, and Kerem Camsari, UC Santa Barbara, on probabilistic computing with Spintronic p-bits: Devices to algorithms. Tetsuo Endoh, Tohoku University, was the Program Chair.
MCHI packaging for semiconductor system scaling
2023 Symposium on VLSI Technology and Circuits is currently ongoing at the Rihga Royal Hotel, Kyoto, Japan. It is themed: Rebooting technology and circuits for a sustainable future.
Dr. Surya Bhattacharya, Director, System-in-Package, Institute of Microelectronics, Agency for Science, Technology and Research (A*STAR), Singapore, presented the plenary on multi-chiplet heterogeneous integration packaging for semiconductor system scaling.
There is diversification of semiconductor systems. In the past, singular apps drove semiconductor systems with chip and board integration. Present time has diverse, rapidly-growing markets that demand application specific system power, performance, form factor, cost (PPFC) optimization, leading to system scaling. In future, package integration will be critical to meet diversified system scaling needs.
Driving force for heterogeneous integration in package is PPFC optimization enabled by multi-chip HIP. SoC challenges include performance/functionalitylimitations from SoC reticle and cost of leading nodes. System on board challenges include higher power due to longer PCB traces, and form-factor limitations of PCB.
When we look at evolution of multi-chiplet HIP, mobility, IoT, 5G, sensing, radar markets are driving cost-effective fan-out wafer-level packaging (FOWLP) using multi-layer RDL. Data centre, AI, memory, and HPC markets are driving large-scale system integration 2.5D silicon interposer, and stacking using TSV, and µ bump. Disintegration of large SoC is driving adoption of 3D integrated chiplets using hybrid bonding.
There are multi-chiplet heterogeneous integration (MCHI) platforms available. These include embedded high-density fan-out WLP with target apps such as 5G-Tx/Rx, mmWave antenna, automotive radar, AP+memory, AR/VR, etc. Others are 2.5D interposer with target apps like HPC, AI, data center, and chiplets. Finally, 3D integrated chiplets with target apps such as SoC disintegration and re-integration, 3D memory, etc.
The accurate models and precise design enablement are critical to multi-chiplet packaging. Significantly improved FOWLP warpage prediction using extracted visco-elastic models ensures high yields and reliable packaging.
Tremendous market growth in 5G, AI, HPC, autonomous transportation etc , is driving the semiconductor system scaling to meet diverse PPFC requirements. MCHI packaging is must-have tool box to meet semiconductor system scaling demands. Continuous innovation in the ecosystem is ensuring broad, deep and sophisticated capabilities of MCHI packaging. These include embedded high-density FOWLP, 2.5D interposer, and 3D integrated chiplets.
Round-up 2022: War, chips, and back to overseas travels!
Year 2022 has been quite eventful! With the Russia-Ukraine war, alongside Covid-19, things have gone downward for the global semiconductor industry. Next year, we all hope that the industry bounces back much more stronger.
Semicon dip in 2023?
World Semiconductor Trade Statistics (WSTS) released its semiconductor market forecast generated in Nov. 2022. Following a strong growth of 26.2 percent in 2021, WSTS revised its forecast down to a single-digit growth for the worldwide semiconductor market in 2022 with a total size of $580 billion, up 4.4 percent, for 2022.
For 2023, the global semiconductor market is projected to decline by -4.1 percent to $557 billion, driven by the memory segment, according to WSTS. Will that happen? Let’s see!
Some categories are still expected to see double-digit year-over-year growth in 2022, led by analog with 20.8 percent, sensors with 16.3 percent, and logic with 14.5 percent growth. Memory is expected to turn negative in the forecast, and decline 12.6 percent year-over-year. In 2022, all geographical regions are seen to show double-digit growth except Asia Pacific. Asia Pacific is likely to decline 2 percent. Americas is expected to show growth of 17 percent, Europe 12.6 percent, and Japan 10 percent, respectively.
TrendForce, Taiwan, has said that YoY growth of NAND Flash demand bits will stay under 30 percent from 2022 to 2025 as demand slows for PC client SSDs. Recent headwinds in the global economy have caused a demand freeze in the wider consumer electronics market. Enterprise SSDs will succeed as major driver of demand bit growth in future. TSMC has also made moves in the USA, and now, is targeting Europe. More of that later!
Review 2022
In Jan. 2022, Future Horizons said that the global semiconductor industry grew 26 percent in 2021, and was likely to grow 10 percent in 2022. This was later revised down to 4 percent growth for 2022.
CEA-Leti organized a photonics workshop in Feb. 2022, where they talked about silicon photonics for AI, and integration of electronics and photonics. Dr. Nicky Lu, CEO and Founder, Etron, and Managing Board Director, Taiwan Semiconductor Industry Association (TSIA), spoke about start of tera-scale-integration era with optimized heterogeneous and monolithic integration at the fifth annual heterogeneous integration symposium, in Feb. 2021. Heterogenous integration impacts Silicon 3.0. Monolithic and heterogenous integration (MHI) has led to the Si4.0 era that is now ongoing.
March 2022 had HAXPES-Lab and what it can do for the electronics industry. There were key developments and implications of MWC 2022. DIGITALEUROPE, EU, had a webinar on how the Ukrainian IT industry was still standing against all odds, in March 2022.
ISQED 2022 was in April 2022, with Dr. Chi-foon Chan, Co-CEO, Synopsys discussing how to thrive in our changing environment. Digital Ts — threads, twins, technologies, and transformation, from Digital Twin Consortium (DTC), was another event.
May 2022 had MegaChips entering the US market for edge AI chips market. Display Week 2022 saw Ross Young discuss the smartphone and smartphone display market outlook. AR/VR market trends and technology outlook was presented by Guillaume Chansin, Director of Display Research, DSCC, at Display Week. It was in May that Future Horizons revised the semiconductor outlook for 2022 to 6 percent. Later, SEMI Arizona and Texas Chapters, USA, had a seminar on workforce shortage—meeting challenges for the semiconductor industry.
Semiconductor innovations
Global Semiconductor Alliance (GSA) had a conference on how diversity increases profitability. It looked at what managements can do to accelerate diversity. Honolulu, Hawaii, was the place for 2022 VLSI Symposium that looked at technology and circuits as critical infrastructure of future. Dr. Y. J. Mii, Senior VP of R&D, Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC), presented on semiconductor innovations, from device to system.
Intel 4 CMOS with advanced FinFET transistors optimized for high-density and HPC came to the fore, and there was a workshop on cryogenic electronics for quantum computing. CHIPKIT emerged as an agile, re-usable open-source framework for test chip development. We had the OpenROAD project — open source platform for IC design innovation at VLSI Symposium 2022. Chips in Europe looked at advancing innovation in semiconductor industry, by SEMI Europe.
BloombergNEF summit in New Delhi talked about 2-4x investment that was needed to meet the net-zero targets by 2050. Semiconductor Industry Association-Semiconductor Research Corp., (SIA-SRC), USA discussed the future of semiconductor hardware. At Automatica 2022, Siemens’ showcased NX industrial electrical design to boost engineering productivity.
In July 2022, I wrote about why more women are definitely needed in semiconductors! Boreas Technology advised how piezo haptics will create their own market by introducing novel haptic apps. At Semicon West 2022, Ms. Laurie E. Locascio, Under Secretary of Commerce for Standards and Technology Director, National Institute of Standards and Technology (NIST), talked about how all parts of the US Chips Act need to be closely co-ordinated.
Andrea Lati, Director, Market Analysis, TechInsights, mentioned the semiconductor capital spending and equipment outlook for 2022. Christian Gregor Dieseldorff, Senior Principal Analyst, SEMI, discussed the trends and forecast for fab equipment spending, capacities, and new fabs.
NASA invites me!
Dr. Michael McCreary, Chief Innovation Officer, E Ink Corp., at Flex 2022, Semicon West 2022 stated how electrophoretic display was changing the look of autos, transportation, and beyond. Dr. Dawson Cagle, Program Manager, IARPA, talked about how IARPA’s smart e-pants were weaving electronics into textiles. In July, I was invited to attend NASA’s SpaceX CRS-25 launch to International Space Station. That was really something spectacular to behold!
Dr. Ms. Kate Darling, leading expert in Robot Ethics and MIT Media Lab Research Specialist, MIT Media Lab, talked about the future of human-robot interaction at Sensors Converge 2022. SIA discussed investing in innovation: blueprint for enduring American semiconductor leadership. Silicon-based quantum computing as a disruptive paradigm, was presented by Dr. Maud Vinet, Quantum Hardware Program Manager, CEA Leti, at Scaling and Lithography Tech Talks, Semicon West 2022.
Aug. 2022 saw how the EU Chips Act was necessary for accelerated digital transformation. I clarified whether people think I am very good in semiconductors? Dr. Henning Schröder, Group Leader, Fraunhofer Institute for Reliability and Micro-integration IZM, presented on glass-based quantum photonic packaging.
Agri-PV harvesting the opportunities of solar + farming started off Sept. 2022. Quantum dot imagers bridging SWIR accessibility gap was presented at SEMI MEMS & Sensors Summit 2022. Malcolm Penn, Future Horizons, revised global semiconductor growth forecast to +4 percent for 2022; with downturn likely ahead in 2023! Let’s see!
New materials required
SEMICON Taiwan 2022 Power & Opto Semiconductor Forum addressed how new materials are required to solve technology challenges, and support growth of electronics. SEMI, USA, looked into the future of computing in 2040. Center for the Study of the Presidency and Congress (CSPC), USA organized a conference on the US Chips Act and implementation. Xecs, Europe, maintained its focus on electronic components and systems.
Oct. 2022 had a session on time-sensitive networking (TSN) and future of connectivity by the Industry IoT Consortium (IIC). Satellite quantum key distribution moving to industrialization phase was discussed by the European Photonics Industry Consortium (EPIC). I also made my first overseas trip to Dubai, post the pandemic, to attend an event.
In Nov. 2022, SEMI, Northwest Chapter, USA, organized a conference on ‘The Future of More Than Moore—Chiplets, Advanced Packaging, and More’. Ms. Amy Leong, SVP, CMO, GM Emerging Growth/M&A, FormFactor Inc., presented on strategy for wafer probe in a chiplet world. Luc Van den hove, President and CEO, imec, discussed how future of scaling needs system-level thinking and STCO at IMT 2022. Japan intimated how it was gearing up to re-transform computing power and semiconductors.
Las Vegas and KA
Las Vegas, USA, welcomed me back, again, after 15 years, for an industry event. May I also mention KA, a spectacular show from Cirque de Soleil, that I witnessed. Featuring 80 artists from around the world, KÀ is a gravity-defying production featuring powerfully emotive soundtrack that enhances the innovative blend of acrobatic feats, Capoeira, puppetry, projections, and martial arts. Great experience! I also bumped into an angel or Pari, mid-air, en route to New York. 🙂
Next, there was Semicon Europa 2022 in Munich, Germany, which included ITF Beyond 5G. Among the topics discussed were compound semiconductor epitaxy core of next-gen connectivity. Chips are now the new oil, was proclaimed by Laith Altimime, President, SEMI Europe! I cannot express how happy I am to hear this! More of it later!! There were talks about building scalable and ultra-coherent quantum computers with carbon nanotubes, metaverse, future of air travel, among topics at Semicon Europa 2022. Later, there was IEEE Standards Association (SA) workshop on 5G and beyond in New Delhi.
Dec. 2022 began with an SIA seminar that looked at the growing challenge of semiconductor design leadership. Design costs are rising with every new technology node. Moore’s Law scaling has not been keeping pace. New improvements are required in design and packaging.
There are challenges to global semiconductor manufacturing. Geopolitical tensions are creating risks of disruption and shortages. Semiconductor industry is suffering from a lack of attractiveness and qualified talent. Besides, we have global warming threat and need for sustainability programs. Countries also need to create enough incentives for manufacturing investments.
Still in Dec. 2022, the 68th International Electron Devices Meeting (IEDM) 2022 was held in San Francisco, USA. IEDM celebrated its 75th birthday this year. There were five focus sessions on advanced heterogeneous integration: chiplets and system-in-packaging, quantum information and sensing, special topics in non-von Neumann computing, DNA digital data storage transistor-based DNA sequencing, and bio-computing, and implantable-device technology.
Fusion ignition achieved
US Department of Energy (DOE) and DOE’s National Nuclear Security Administration (NNSA) announced the achievement of fusion ignition at Lawrence Livermore National Laboratory (LLNL)—a major scientific breakthrough decades in the making that will pave the way for advancements in national defense and the future of clean power. On December 5, a team at LLNL’s National Ignition Facility (NIF) conducted the first controlled fusion experiment in history to reach this milestone, also known as scientific energy breakeven, meaning it produced more energy from fusion than the laser energy used to drive it.
For the first time, researchers produced more energy from fusion, than used to drive it. This promises further discovery in clean power and nuclear weapons stewardship. This historic, first-of-its kind achievement will provide unprecedented capability to support NNSA’s Stockpile Stewardship Program, and will provide invaluable insights into the prospects of clean fusion energy. It would be a game-changer for efforts to achieve President Joe Biden’s goal of a net-zero carbon economy.
TSMC leads
On December 6, TSMC announced that besides TSMC Arizona’s first fab, which is scheduled to begin production of N4 process technology in 2024, it has started construction of a second fab, scheduled to begin production of 3nm process technology in 2026. When complete, TSMC Arizona’s two fabs will manufacture over 600,000 wafers per year, with estimated end-product value of more than US$40 billion.
TSMC is also reportedly in advanced talks for setting up its first potential European plant in Dresden, Germany. The plant could begin construction by 2024. This will be probably signed sometime in 2023.
National Institute of Standards and Technology (NIST) organized a session on US CHIPS and Science Act. Ms. Gina Raimoldo, Secretary of Commerce, USA, said teams are working to ensure implementation and future impact of US Chips Act. USA is also nudging TSMC to do more in the USA.
Dec. 16, TrendForce reported that YMTC may abandon the market for 3D NAND Flash by 2024 following the US Government’s decision to place it on entity list. Well, that may be bad news for China and flash memory market.
That reminds me! I came across a post on LinkedIn, where technologies were being discussed for semiconductors by lots of big names. Ok, my name was not included! 🙂 That’s fine. Here is a list that may be looked up: nanosheets, vertical-transport nanosheet field-effect transistors (VTFETs), compound semiconductor epitaxy, quantum communications, biosensors, glass-based quantum photonic packaging, 3D hybrid electronics, piezo haptics, system-on-multichip (SoMC) architectures, tera-scale-integration, KOOL DRAM, etc. Oh, it was my BDSM moment, surely! 😉
And, that’s it, folks! 🙂 One sincerely wishes that the global semiconductor industry, and semiconductor market, are back to the top again, in 2023. Warm wishes to everyone for a very successful and vibrant 2023.
PS: Edson Arantes do Nascimento, or Pele, Brazil, and football world’s superstar, is no more. Rest in peace, ‘O Rei’, the greatest!
OpenROAD project: Open source platform for IC design innovation
Andrew B. Kahng, CSE and ECE Departments, UC San Diego, presented the OpenROAD project: Open source platform for IC design innovation, at the 2022 IEEE Symposium on VLSI Technology and Circuits in Hawaii, Circuits Workshop 2.
There is the crisis of hardware design. ASIC design is in advanced nodes, and there are barriers of cost, expertise, and even risk. Innovators also cannot evaluate SWaP, PPA of their design ideas. OpenROAD proposes the ease of use and runtime. It directly attacks the crises of design and innovation. RTL-to-GDS can be available in 24 hours, and there are no human-in-the-loop, with tape-out GDS, and open source that runs in 24 hours.
With OpenROAD, you can unleash system and design innovation. There can be tool customization to system and app needs. Foundation for hardware innovation can be found in the DoD/DIB. It also provides foundation for research and education, and workforce development.
Open ROAD and chip design are progressing together. There is SKY 130, with 260+ tape-outs on Google-SkyWater, e-fabless chip-ignite shuttle and commercial offering. Also, there is GF12, a mixed-signal SoC, and Intel 22/16, an Army Research Labs project in flight. OpenROAD is supporting GF12, Intel 22/16, TSMC65, GF55, SKY90, SKY130, and more. Army Research Labs is also working with University of Michigan. University of Washington is working on BlackParrot dual-core in GF12LP.
OpenROAD is now part of VLSI system design, with over 2,500 enrollments in the OpenLane/OpenROAD courses and workshops across 85 countries and 26 languages. There are novices to experts, working on trust, and 3DIC, AI/ML.
What’s next?
So, what’s next? OpenROAD is looking at 12nm tapeout-capable, with integrated architecture, database, and timer. It is looking at improved performance, power efficiency and area, ML and auto-tuning. It is on the road to EDA 2.0 with intelligence and cloud. There is COPILOT, or cloud optimized physical implementation leveraging OpenROAD technology. Some of the engaged contributors include IBM, Google, DoD, etc.
OpenROAD is a front-runner in open-source semiconductor design automation tools and know-how. The project reduces barriers of access and tool costs to democratize system and product innovation in silicon.
At VLSI-SoC 2020, there was talk about open-source EDA. If we build it, who will come? There are inherent contradictions or tensions to grapple with. Academic research meets tapeout-clean RTL-to-GDS in foundry nodes. There are factors such as research success vs. open-source EDA success. There is no human-in-the-loop tool vs. flexibility for the new, such as 2.5D, secure IC areanas, etc.
We are looking at how open source can meet business viability. The system needs will be better served in future. We can also edit the source code. We are growing the technology. We are also using ML for intelligence and self-adaptation. Cloud deployment can scale up quality and efficiency. We are always keeping in mind the critical mass and critical quality.
CHIPKIT: Agile, re-usable open-source framework for rapid test chip development
Gu-Yeon Wei, Harvard University, presented on the emerging ecosystem of open-source chip design. He talked about CHIPKIT, an agile, re-usable open-source framework for rapid test chip development, at the 2022 IEEE Symposium on VLSI Technology and Circuits in Hawaii.
Today, we are finding that CMOS physical scaling is plateauing. Dennard scaling ran out a while ago. Two obvious paths forward are parallelization and specialization. If we look at 10+ years of hardware specialization, the number of specialized IP blocks has steadily risen across many generations of Apple SoCs. There have also been 5+ years of accelerator test chips at Harvard.
Currently, there is huge activity around open hardware. There are open-source IP from universities, and commercial IP available to academia, example, ARM. There has never been a better time to get into research test chips. CHIPKIT embodies 5+ years of SoC tapeout experience at Harvard, and tutorial with code to help build test chips. CHIPKIT is an agile, re-usable open-source framework for rapid test chip development. There are different complexities of test chips.
CHIPKIT offers opportunities for agile and re-usable chip design. There is SoC scaffold, such as SoC bus fabrics, M-class and A-class SoC architecture examples, on-chip memories, etc., and the CHIPKIT tutorial is also available. He showed an example of a 28nm DNN engine accelerator. CHIPKIT provides basic scaffolding for research test chips.
CHIPKIT is intended for those looking to do their first tape outs, and develop more sophisticated test chips. They can reduce the time to develop and maintain their SoCs and custom IPs. The goals of CHIPKIT and the tutorial are source of open and basic material for research tape outs, provide high-level overview of front-end design and validation, overview of physical design flow, bring up, and testing.
Holistic patterning to advance semiconductor manufacturing
Martin van den Brink, President and CTO, ASML, presented a keynote on the holistic patterning to advance semiconductor manufacturing for the 2020s and beyond, at the ongoing 2022 IEEE Symposium on VLSI Technology and Circuits in Hawaii.
There are litho shrink, holistic lithography, apps, DUV, EUV, and EUV high-NA. Different lithography technologies address numerous market segments. There are mature segments, above 40nm and advanced segments less than 28nm. Over 35 years, two orders of magnitude resolution reduction continuing. We are working on wavelength, NA and k1. How will we move forward?
Moore’s Law will continue to evolve over the next two decades. System energy efficient performance growth will be 3x per 2 years, continuing on to 2040. There will be equivalent scaling, and new transistor structure materials. Moore’s Law will evolve from cost per transistor through density, to cost of time and energy through systems. Moore’s Law evolution today is on system energy efficient performance through more transistors and silicon area. Litho density scaling continues in this decade. Overlay and optical proximity correction errors are continuing to shrink.
Holistic litho portfolio
A holistic litho portfolio is required to meet litho requirements. We need lithography scanner with advanced control capability. Today, we are integrating litho, metrology, and computational litho in one platform — the virtual computing platform (VCP). There are scanner metrology, YieldStar, HMI metrology and inspection to optimize sampling for scanner control and as yield proxy for faster time-to-yield. We start from apps, to DUV, onto EUV.
Deep learning is transforming optical proximity correction models. There are resist and etch models, OPC+, SRAF or sub-resolution assist features, and final freeform mask. We have OPC improvement through deep learning-based etch model, with 35 percent on-product improvement in OPC accuracy. An example of Freeform OPC+ enhancing DUV litho performance for logic was shown. Also, for Yieldstar, ASML is looking for speed and robustness increases. ASML has also extended its offering to wafer inspection with multibeam architecture. As per ASML, edge placement error monitoring and optimization can be enabled by fast metrology. ASML is also driving improvements in EPE.
DUV and EUV
Productivity improvements are very important for DUV. ASML has a product roadmap to support all market segments. All wavelengths, ArFi, ArF, KrF, and i-Line, are supported. There is a DUV immersion scanner roadmap. Overlay and productivity upgrade paths are supporting the installed base.
There are robust alignment measures for improved on-product overlay. Sub-wafer scale errors dominate the overlay budget to future nodes. The scanner intra-field and die correctability is combined with fast and dense sampling to meet this. New DUV distortion manipulator can cut by factor of 2. DUV Pellocle deflection correction reduces its contribution by 2X.
EUV single expose leads to process simplification. Process simplification is leading to better defect density. There is shorter production cycle and steeper ramp to higher yield, as well as lower patterning costs. In a full fab, EUV enables higher output.
EUV adoption has been enabled by high-volume, production-capable EUV platform. It is providing system maturity, needed for high-volume manufacturing. For EUV product roadmap, EUV 0.55 has been added to support high-volume manufacturing in 2025-26. Also, scalability of EUV source power beyond 500W has proven to be feasible.
ASML is also supporting the EUV pellicle power compatibility and transmission roadmap. It is supporting the productivity roadmap. Finally, metal oxide resist is driving ASML in the sub-10nm regime.
Despite growing chip complexity, energy and mask usage has stabilized. Without EUV insertion, process energy and mask steps will continue to increase. ASML is announcing the High-NA program. Patterning simplification can be done by High-NA. EUV High-NA requires an anamorphic lens. High-NA and fast stages enable 220 Wph. There can be mix-and-match between half field (High-NA) and full-field (DUV and EUV 0.33) that can be optimized through layer optimization. Die bigger than half field will need stitching.
ASML is also integrating for pre-qualified modules worldwide. It is building a High-NA lab that enables early process development for customers, starting 2023. The lab facilities are now ready, and the first equipment has been installed.
Conclusion
The value generation of semiconductor innovation is not slowing down, and Moore’s Law will not stop. Litho density decrease will slow down, but carry on. New and improved litho solutions will be required in future. Holistic approach through various wavelengths of litho, optical, and e-beam metrology, inspection, and computational techniques is required. All technologies will be used for production in the new advanced nodes.
EUV has become the high-volume production for advanced nodes, leading to higher yields and less energy use. EUV High-NA will extend this simplification for 1future nodes from 2025 and beyond.
Cryogenic electronics for quantum computing
At the 2022 IEEE VLSI Technology and Circuits conference in Hawaii, there was a joint workshop on cryogenic electronics for quantum computing.
Kevin Tien, Research Staff Member, IBM Quantum, presented on cryo-electronics and system design approaches for superconducting qubit control at the ongoing 2022 IEEE Symposium on VLSI Technology and Circuits in Hawaii. Today, we have cryo-electronic ASICs exceeding 2,000 qubits. There are Transmon qubits that behave like the artificial atoms.
The cryogenic operation allows us to isolate transition between two lowest levels 0 and 1, whose separation defines qubit frequency. The qubit state is controllable with application of capacitively coupled electric field, such as coherent resonant drive with correct envelope can shift state from 0 to 1.
There are apps of quantum computing across chemistry, materials, ML, optimization, etc. The quantum possible is factoring and simulating quantum mechanics.
Error correction is key to realizing fault-tolerant quantum computing. Example, physical data qubits interconnected with supporting ancilla and flag qubits to realize heavy hexagon code — 1 logical qubit! This requires potentially >70 percent of the 57 physical qubits to be active at any one time. That control can cover qubit frequency spread. Multiplexing is not straightforward!
Cryogenic state controller is designed with single-channel-per-qubit system in mind to meet requirements of error correction. It is realized in 14 nm FinFET technology. It achieves 23 mW per qubit under active control, with error rates and measurement results comparable to those achieved with baseline room temperature control systems.
Emulation is the key to speeding up the development cycle by allowing early software development. Xilinx Zynq UltraScale+ RFSoC FPGA was chosen as the anchor for the emulation system. ASIC and FPGA design specs intersect to allow consistent frequency plans. This enables direct system emulation.
Cryo-CMOS measured output spectrum was upconverted baseband sine wave of 141 MHz IF and 5.6 GHz LO. Lower sideband signal was 5.459 GHz. SFDR within 500 MHz of signal is >50 dB.
Qubit measurements are done by Rabi cycle. Rabi experiment: determines the relationship between the amplitude of coherent, qubit-resonant microwave pulse and angle swept by Bloch vector. It allows for determination of π pulse (0->1 transition) amplitude, key part of system calibration. Qubit measurements lead to randomized benchmarking.
Low-power qubit state controller was implemented and demonstrated in single-qubit control application. The emulation platform based on the Xilinx Zynq UltraScale+ RFSoC FPGA was used to perform early validation of high-level specifications for the ISA of the controller processor and for the baseband DAC core, and to set the stage for multi-qubit control with cryogenic quantum state controllers.
Next steps involve the demonstration of more complex multi-qubit control using both the ASIC platform and the emulation platform. There will be continued cryo-CMOS development towards decreasing power consumption and increasing integration scale.
Intel 4 CMOS with advanced FinFET transistors optimized for high-density and HPC
There was a presentation of Intel 4 CMOS technology featuring advanced FinFET transistors optimized for high-density and HPC at the ongoing 2022 IEEE Symposium on VLSI Technology and Circuits in Hawaii.
Intel has introduced Intel 4 logic process technology featuring >20 percent iso-power performance gain vs. Intel 7 (Alder Lake), 8VT offers additional 5 percent performance at high voltage, 2x high-performance logic library area scaling vs. Intel 7, extensive use of EUV lithography for process simplification, etc. Intel4 is compatible with advanced packaging technologies EMIB and Foveros. The lead Intel 4 product, Meteor Lake, is up and running.
EUV lithography enables significant process flow simplification while supporting scaling. Extensive use of EUV lithography has enabled total mask and total step count reduction in Intel 4. Also, Intel 4 is optimized for HPC apps to support low (<0.65V) and high-voltage (>1.3V) operations. Both, NMOS and PMOS devices exhibit excellent sub-threshold characteristics. There is healthy and robust Weibull behavior across a wide range of normalized lifetimes.
For interconnects, EUV has been used extensively across multiple layers. There are 5 enhanced Cu and 13 Cu interconnect layers. The interconnect stack is optimized for RC, while providing healthy EM reliability. There is gridded interconnect design rules benefit process predictability design optimization.
MIM capacitor is used for power delivery. Intel 4 offers ~2x increase in MIM cap density over Intel 7. Meteor Lake with Intel 4 and 3D Foveros packaging technology is up and running.
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