IRPS 2021

IoT end-node device built to last: IRPS 2021

Posted on

Alessandro Piovaccari, CTO and SVP of Central R&D, Silicon Labs, presented the concluding keynote on IoT End-node Device: Built to Last, on day 4 of the IRPS 2021, at Monterrey, California, USA. He spoke about the SoC near us.

There has been over 50 years of the Moore’s Law, and it is still standing. There has been an evolution toward scientific discoveries, starting from Brahe, Kepler, on to Newton and Einstein. Innovation is a long process involving deep understanding, and simple, elegant solutions.

Cross-discipline collaboration is extremely important. Every important innovation always creates a platform that can enable great possibilities in the other fields. An example is the road from light bulb to electronics, such as HP200 in 1939. This has since led to IoT connected lighting. Light bulb was indeed a rocket science.

We have put an end-node SoC as the wireless superhero. These devices are likely to have lifetime of 15-20 years, with coin cell operation, OTA upgradeability, etc. These devices are always on. The cost should be <$1 ASP. Looking at one of the end-node SoC under the hood, it uses the RF transceivers. The NVM and RAM will also scale up. It is designed at 90-40nm, and 22nm and beyond are around the corner.

There are reliability considerations with the connected lighting system. There are the IoT end-node meters (HCAs, ESLs, meters), connected LED light bulbs, etc. There is electronics reliability and aging also in play. There are software reliability standards, such as Motor Industry Software Reliability Association (MISRA). There also has to be end-node SoC secure lifecycle management.

Talking about low-power apps, there is the energy consumption in 2020 2025, with batteries now having to go off the radar. There will likely be around 20 billion battery-operated IoT nodes for about 50 billion IoT devices. The IT ecosystem electricity requirement will be around 3-4 PWh/year, increasing to ~20 percent in 2025.

The utility meters data collection is done via base stations in direct connection. Some other approaches are static aggregators and mobile aggregators. Another app is the heat cost allocators (HCA) in Europe. There is the wireless configurator and aggregator. Battery cost and lifetime of the LiMnO2 battery, soldered to the PCB, is 12 years. Main challenge is handling the transmission burst. The battery lifetime can be maximized, with LDOs only for the wireless SoC. LCD minumum voltage is 2.4V. Contrast fades during the transmission burst.

Achieving SoC-larity
So, how will we achieve the SoC-larity? We have the next-generation end-node SoC. The main challenges are cost, energy, performance, and lifetime. There is also the hardware and software development time. For energy consumption, the radio (transmission) limits the wireless activity and OTA upgrades.

Innovation is needed for circuits, systems, and network protocols. We also need a smarter Moore’s Law. We need to use multi-core and bring ML to the end node. This includes local data computation and anomaly detection, as well as predictive maintenance and enhanced security detection, network optimization, and adaptive security management.

Revisiting Moore’s Law, there are new areas, like digital, process advancements, digital-centric, circuit cleverness, analog, etc. We can still take good advantage of Moore’s Law. There is the factor of interchangeable parts. This is the fundamental ingredient for scalability, efficiency, and time-to-market. We also need to have verified open source hardware. ETH Zurich is building some of them. There is the Open-Hardware Group, of which Silicon Labs is a part. Another component is ML. There will be ML in the end-node devices.

Laying groundwork for 6G communications: IRPS 2021

Posted on

Peter Gammel, CTO MWI, GlobalFoundries, presented a keynote on day 3 of the ongoing IRPS 2021, on laying the groundwork for 6G communications. He talked about silicon solutions for today’s 5G reality and foundation for 6G.

Three megatrends are driving the industry. These are frictionless networking, virtualization, and hierarchical AI. Frictionless networking arises from the need to be immersed in a sea of data. Your devices are always connected, without worrying about log on/off, network type, etc. The move to frictionless networking is going to be huge. Next, when can we go to a true holographic virtualization. This would require at least 3GB per person at about 10ms latency.

Frictionless networking will be enabled by low latency, bronto bytes of data, proliferation of connected devices, and secure agents and transactions. The number of connected devices will just explode.

5G is critical to the evolution of the network. There will be 10X decrease in latency, rise in 10X connection density, 10X experienced throughput, 3X spectrum efficiency, 100X traffic capacity, and 100X network capacity. There will also be growing data demands, leading to everyday machine communications, and critical machine communications. In terms of the future regulatory and standardization, we should have reached Rel-17 by 2021. We will aim for Rel-18 in 2022, going up to Rel-22 by 2027.

We are also looking at wireless last hop. This will lead to higher frequency, denser network, lower power, and multi-standard. The frequencies continue to increase, cell size continues to decrease, and Wi-Fi growth continues. Higher frequencies favor SiGe, FDX (FD-SOI), etc. Higher density and multi-protocol drives software volume and roadmap. Smaller cells favor SiGe, FDX, and lower power, especially, IoT, drives FDX SoC.

At sub-6GHz and 5G handset RF FEM (front-end module) there are technology challenges. More bands/handset leads to more components within the same form factor. Higher frequency bands leads to higher insertion loss, transmission efficiency, and transmission/reception isolation, etc. A DL 4×4 MIMO device has four antennas for four simultaneous data streams. That means more antenna, more components, and transceiver area/power.

There are key technology metrics for mmWave radio. These include back end parasitics, transistor stacking, and flicker noise. Low-power logic and analog are the key metrics for RF SoC. The mmWave 5G will need phased arrays. Multiple phased array antenna modules within a handset avoid blockage of mmWave signal. Also, mmWave radio will co-exist with sub-6GHz in a handset. GlobalFoundries’ mmWave technology enables next-generation networks. These include 22FDX solutions, 45RFSOI solutions, and SiGe 8HP/XP solutions.

Expanding requirements for 6G
Now, 6G will expand all of our work. 6G will lead to extreme high data rate and capacity, and extreme coverage. Peak data rate will be above 100Gbps and exploiting new spectrum bands. There will also be new coverage areas.

It will also lead to extreme low energy and cost. There will also be extreme low latency, extreme high reliability, etc. There will be extreme massive connectivity, with massive connected devices, sensing capabilities, and high-precision positioning. 6G will also enable new combinations of requirements for new use cases.

Looking at 6G and sub-THz, there are huge amounts of spectrum available at 100-300GHz. It is an enabler for sensing and communications, with large bandwidth and smaller wavelength. W- and D-bands are the leading contenders.

There are next-generation solutions from GlobalFoundries to address the 6G requirements. These include extreme high data rate/capacity, with transmission at higher frequencies (up to THz), extreme low energy and cost leading to alternative front-end modules/power amplifier (FEM/PA) architectures, extreme massive connectivity, with low-power devices, IoT, etc.

There are other technology challenges for beyond 5G, such as PCB routing loss. One way would be to move antenna from PCB to package. We are going on to a much more complicated packaging structure. With the antenna on package, there would be die flip chip under mounted to laminate, and antenna elements are on the package.

Next, satellite-based broadband Internet and mobile communications will boom. It will be connecting the next 4 billion people. There will be thousands of satellites in LEO.

Open RAN will also challenge the traditional network deployment. The shift to 5G networks is creating innovation in RAN component virtualization and interface standardization. Upto 10 percent of all cellular infrastructure deployments could be Open RAN by 2025. Key drivers for this transformation are multi-faceted. There will be flexibility in selecting multiple vendors, fast hardware deployments, and reduction in capex (by 40 percent) and opex (by 35 percent).

Future communication networks will be driven by intelligent edge nodes based on high-speed, always-on devices. Technology innovations are needed to leverage a vast, untapped spectrum (100GHz-1THz). Innovative RF-SOI, FinFET, SOI/SiGe-based photonics are the platforms for the future.

Reliability of SiC MOSFETS: IRPS 2021

Posted on

International Reliability Physics Symposium (IRPS) 2021 commenced in Monterrey, California, USA. Dr. John Palmour, CTO Cree/Wolfspeed, presented a keynote on SiC MOSFET Reliability: An overnight success 30 years in making. Robert Kaplar, Sandia, General Chair, IRPS 2021, introduced Dr. Palmour.

Wolfspeed offers vertically-integrated SiC and GaN devices. SiC power MOSFETs are being rapidly adopted for EVs. SiCs are well established in OBCs, and gaining traction in off-board chargers. They offer improved range and/or cost for BEVs vs. the current Si IGBT solution.

There has been adoption of Wolfspeed SiC across various apps. Eg., PV inverters, battery chargers for EVs, server power supply, and traction, etc. SiC impact on key apps is in electric vehicles. These are used in drivetrain inverters, auxiliary inverters, fuel-cell DC-DC, onboard charging, solid-state circuit breakers, etc.

SiC MOSFET improve the cost of ownership. The inverter-level loss comparison is significant. The overall cost of EV can come down by $15,000-$100,000. You can shed cost by SiC battery savings, and also for weight and cooling savings. There is 2.5x increase in power density, and 10 percent reduction in capacitors.

The shift from silicon to silicon carbide delivers cost savings for OEMs. There is ~10 percent battery savings, space and weight savings, cooling replacement savings, etc. The e-powertrain can be re-purposed for further e-markets. For e-mobility, they can be used for e-tank, etc. Off board charging DC-DC efficiency and power density are also improved. There is 33 percent more power, and 25 percent smaller size.

SiC MOSFETs history
There was the usage of first real MOSFETSs in SiC in 1987. We had to move to 3C-SiC MOSFET on 6H-SiC Lely platelet at 650C. The first 6H-SiC inversion-mode MOSFET came in 1989. The first trench (UMOS) 6H-SiC MOSFETs came in 1992. The mobility was much better. However, 6H-SiC had severe electron mobility anisotropy. In 1995, we delivered the first 4H-SiC MOSFETs (UMOS).

The SiC evolution and R&D milestones have been rapid at Wolfspeed. In 2008, we got to the SiC 1200 V DMOSFET on-state performance. The industry’s first SiC MOSFET was made available in 2011 from Cree. In fact, Barack Obama, then president, USA, asked a question about oxide reliability due to lower conduction band offsets. Wolfspeed SiC MOSFETs are now a decade in the market. Tesla was the first automotive company to jump into SiC. Cree has also partnered with Delphi Technologies for SiC into EV powertrains.

Why is SiC reliable?
There is decreasing failure rate for SiCs. Minimal parametric shift has been witnessed post stress. In qualification testing, there was parametric shift post 1,000 hours of high-temperature blocking (HTGB) stress. Si IGBTs show sharper failure onset, but higher max failure rate.

Looking at time-dependant di-electric breakdown (TDDB), there is TDDB data for three different gate voltages and three different temperatures, using at least 40 counts of Cree Gen 3 devices at each stress condition.

There is the accelerated life test high temperature reverse bias (ALT-HTRB). Physical failure analysis on Wolfspeed MOSFETs shows that failures are gate oxide related. ALT-HTRB fits with Weibull statistics and linear-V model. The mean time to failure (MTTF) is shown. It predicts high lifetimes at typical use voltages. Automotive quality depends on fundamental SiC reliability. Capacity required for automotive is a quantum leap for SiC wafer and fab capacity.

SiC power MOSFETs have been in development for 34 years. Three different types of polytypes were explored. settling on 4H-SIC. There were seven wafer diameter increases. The current capability increased by 100,000, and voltage capability by 3,000. Oxides have proven to be reliable.

The BEV market for SiC has been seeing rapid expansion due to the benefits that SiC brings. They are smaller, lighter, with more efficient chargers. There are faster, and more economical charging times. SiC oxides are now looking on part with SiO2 on Si. Sensitivity to terrestrial neutrons is on par with the insulated-gate bipolar transistor (IGBTs), and much lower at higher bias. Gen 3 planar MOSFETs are ‘hard to kill’ in reverse bias.

IRPS 2021 is here, virtually!

Posted on Updated on

The 2021 IEEE International Reliability Physics Symposium (IRPS), will be held virtually between March 21 and March 24, 2021.

Seok-Hee Lee

There are going to be some outstanding keynote speakers. Among those confirmed include Seok-Hee Lee, President and CEO of SK Hynix, who will talk about memory’s journey towards the future ICT world. John Palmour, CTO Cree /Wolfspeed, will talk about SiC MOSFET reliability: An overnight success 30 years in the making.

Peter Gammel, CTO MWI at GlobalFoundries, will talk about laying the groundwork for 6G communications. And, Alessandro Piovaccari, CTO, Silicon Labs, will talk about IoT end-node device built to last.

There are 22 tutorials on a range of reliability topics, the year in review, 11 workshops, and the technical program. The IRPS 2021 technical program sub-committees have a selected a number of highlighted papers. Some of them are highlighted below, as prepared by the Publicity Chair, Ben Kaczer, IMEC.

  • Study on the difference between ID(VG) and C(VG) pBTI shifts in GaN-on-Si E-mode MOSc-HEMT.
  • Elucidating 1S1R operation to reduce the read voltage margin variability by stack and programming conditions optimization.
  • Characterization of slow traps in SiGe MOS interfaces by TiN/Y2O3 gate stacks.
  • TDDB or time-dependent dielectric breakdown reliability in gate-all-around nanosheet.
  • Time dependent variability in advanced FinFET technology for end-of-lifetime reliability prediction.
  • Reliability of a DME Ru semidamascene scheme with 16 nm wide airgaps.
  • Characterization and mitigation of relaxation effects on multi-level RRAM based in-memory computing.
  • Reliability of wafer-level ultra-thinning down to 3 μm using 20 nm-node DRAMs.
  • Reliability and variability-aware DTCO flow: Demonstration of projections to N3 FinFET and nanosheet technologies.
  • Compact model of ESD diode suitable for sub-nanosecond switching transients.
  • Robust brain-inspired computing: On the reliability of spiking neural network using emerging non-volatile synapses.
  • Scaling trends in the soft error rate of SRAMs from planar to 5nm FinFET.
  • Machine learning on transistor aging data: Test time reduction and modeling for novel devices.
  • RF reliability of SOI-based power amplifier FETs for mmWave 5G applications.

We look forward to a great conference!