Thomas Schulz, Channel Manager CEE, GE Digital, presented cyber security as the key condition for Industry 4.0 adoption, on the concluding day of SEMI Technology Week.
With the introduction and integration of Industry 4.0 devices, platforms and frameworks to existing systems comes the issue of interoperability. In industrial environments, securing interconnectivity between diverse devices is often challenging. Difficulties in ensuring security in Industry 4.0 result also from lack of technical capabilities of connected industrial devices and systems, especially considering integration with legacy infrastructures.
Cyber security in manufacturing is very essential. Fast progress is key to enable the valid responses to cyber threats in the future manufacturing environment. Here, the dependence on networks and information systems will increase rapidly. Attacks become smarter, and therefore, they need to be protected against. The semiconductor industry and manufacturing industry can be particularly vulnerable to attacks.
There are technical fields of action for cyber security. There are mobile and intelligent systems, platforms with hosted apps, and factory as an app domain. The physical assets need to be protected. Security by design, and security by default must be guaranteed at the outset.
Industrial automation and control systems, such as SCADA, DCS, ICS, BAS, and PLCs need to be secured. The equipment used in semiconductor manufacturing includes OT, that manages and monitors the industrial process assets, and manufacturing or industrial equipment. Cyber security must protect the automation and control systems to your physical assets and equipment.
There are factors influencing the technical fields of action. The German BSI or Federal Office for Information Security, Platform Industrie 4.0, and associations, such as SEMI are well established. There is compliance with ISO/IEC 2700, IEC 62443, VDI/VDE 2182, and SEMI E169 and SNARF 6506.
The IEC 62443 security for industrial automation and control systems was adopted globally. It created a framework and common language for the end users to communicate their requirements. IEC 62443-2-4 established that manufacturers must demonstrate that security measures are incorporated in their development lifecycles across four key areas: organization, system capability, commissioning and acceptance testing, and maintenance and support.
A penetration test, also known as pen test or ethical hacking, is an authorized, simulated cyber attack on a system that is conducted to assess the security of that system, and identify vulnerabilities. The Achilles test platform is a communications robustness test platform to test and monitor network and operational parameters of devices under real-world conditions. The Achilles Communications Certificate (ACC) verifies the network robustness.
Deep packet inspection (DPI) is used extensively to prevent attacks. DPI systems should always be kept up to date. There is an important role of IDS and IPS in network security. There is also the OpShield from GE Digital to inspect, enforce, and control. You can protect OT networks structurally via virtual segmentation. It creates zones that reduce the mobility and damage of a misconfiguration, or an attacker. The time to act is now!
Holistic data and computing platform for advanced semiconductor manufacturing, was presented by Tom Hoogenboom, System Engineer IT, ASML, and BG Lee, Director, ASML, on the concluding day of the SEMI Technology Week.
Holistic lithography is data hungry. Chips are ‘made with data’. The position and shape of every pattern element must be set with sub-nm precision. Holistic lithography is built on data. It helps building the digital platform of the future. We also have the digital platform for patterning.
Holistic lithography is our world. It helps compute the best process and actual process windows. There are compute process corrections. The nm level is fine grained. We have now moved from PCs to central computing platform. Today, we operate the digital twin of a fab. If we go to a new node, we analyze everything that has gone on with the previous, old node.
It is important to note that nm performance can be affected by any small variant on process, equipment, etc. We need a platform for running fab-critical software. There is also the integration of software from other vendors. IT should be ready to integrate.
The key requirement is secure communications. You need to move toward a digital lithography ecosystem based on IT technologies and a single platform.
The IT pieces are there for the next node. Integration remains a challenge. Fab automation has some standards. Digital Twin is needed to calibrate the machines. The ASML digital platform provides integration, and is scalable. You also need to process the equipment and connection data.
John Behnke, GM, FPS Product Line, Inficon, kicked off day 3 of the SEMI Technology Week, that was on the future fab. He spoke about the evolution of smart manufacturing — integrated and collaborative smart systems.
The semiconductor industry has been on the forefront of developing advanced technologies used to fuel innovation and accelerate technology development since its inception. Its understanding and access to advanced technologies, coupled with its need to continuously improve manufacturing efficiency and customer satisfaction has pushed the industry to develop and adopt semiconductor-specific Smart Manufacturing/Industry 4.0 methodologies.
These Smart/I4.0 methodologies are heavily integrated solutions, which enhance the existing systems and capabilities. Data from these multiple systems, such as MES, yield, metrology, fault detection, process control, maintenance, and demand, integrate to create a real-time digital representation of the factory.
Smart manufacturing is based on three pillars. These are sensing, connecting, and predicting. Sensing involves the integrated real-time tool, process, and WIP monitoring. Connecting involves uniting the different and unique data sources. Predicting involves the Digital Twin-enable predictive apps.
Inficon offers FPS Smart solutions, such as Digital Twin, Factory Dashboard, Factory Scheduling, NextMove VTS, and Metrology Sampling Optimizer. Digital Twin enables the integrated apps. It is a never-ending journey of increasing the complexity and adding more information. It is the repository of everything about your digital factory.
The window to the Digital Twin real-time factory visualization is needed. Users are aligned to the immediate fab needs. There are integrated analysis tools, so you can set, track and shift the output goals. You can do historical performance charting, maintenance tracking/planning, and line linearity views. Schedulers pick the best lot for the best tool at the best time, and feed this information to lot delivery systems. This ensures factory-wide performance optimization.
Inficon’s NextMove Vision Tracking System (VTS) tracks the smart WIP movement. Dispatched material needs to be moved as per the schedule. There is integration with FabGuard to allow for SECS equipment set up. He showed some dashboard and scheduling-enabled RoI examples.
Prof. Ms Amelie Hagelauer, University of Bayreuth, presented on surface acoustic wave /bulk acoustic wave (SAW/BAW) filters, and current and future materials technology for new filters, at the ongoing Technology Week, organized by SEMI, USA.
There are material challenges in mobile communications. There are increasing number of frequency bands, filter components, higher frequencies, etc. BAW resonators are using AlN or AlScN with Scandium concentrations </= 10 percent.
There are BAW resonators and filter. We can calculate the electromechanical coupling. Piezoelectric properties dominate the bandwidth. A BAW ladder-filter example, and different resonator types were shown. For SMR-BAW-technology, the silicon substrate is very important.
AlScN, in comparison to pure AlN allows improved piezoelectricity with increased Scandium content. Deposition is possible using physical vapor deposition (PVD) sputtering. In the first experimental study, the simplified 1.7GHz BAW resonator designs were used. Deposition of thin films with increasing Scandium concentration was done. This led to the crystallographic characterization of the AlScN thin films. There was characterization of coupling and quality.
The initial growth conditions show a key impact on the crystal quality. The more crystallites, the lower is the preferred c-axis orientation. Size of the crystallites is also an important factor. High amount of crystals does lower BAW performance. There can be design improvements in BAW resonators using electrode frame, electrode apodization, optimized surface roughness, and optimized acoustic mirror.
For SAW, we have some basics. Especially, for SAW, temperature compensation is of interest. There are different types of TC SAW structures. Variant 1 will improve the thermal expansion co-efficient (TEC) by bonding the piezoelectric substrate to a low TEC substrate like sapphire or silicon. Variant 2 will deposit an additional material with positive temperature co-efficient of velocity (TCV).
Crystal grain-free AlScN thin films for 20 percent Scandium using PVD sputtering were shown for BAW. The results were also useful for sputtering with higher Sc content. New materials offer new possibilities, such as wide bandwidth filter, advanced LC-BAW hybrid topologies, and tunable approaches.
High frequency filter performance for the n41 band was also demonstrated. Quality factor is still lower than for pure AlN, even without crystal gains. Deposition-based limitations using sputtering might be the reason. The other deposition methods for higher crystal quality and lower loss like metal oxide chemical vapor deposition (MOCVD) or pulsed layer deposition (PLD) have to be considered. PLD is a promising approach that could allow moderate deposition rats and cost per wafer using high-frequency lasers, local stress control, and high BAW performance and crystal quality for Scandium concentration up to 40 percent.
Day 2 of the SEMI Technology Week focused on materials. Rolf Aschenbrenner, Fraunhofer IZM, presented on heterogenous integration as the key enabler for electronic systems.
There has been a diversification of semiconductor products. There is no single leading driver. Instead, we have had a fragmented growing market. Diversification has been in terms of IoT infrastructure with connectivity and data processing as the backbone, IoT, AR/VR, AI, automotive, 5G connectivity, and servers/data centers. There is growth of high-performance computing, edge computing, and embedded IoT computing, using smart sensors, localized networks, etc. There is the heterogenous integration platform for doing all of this.
Heterogenous integration refers to the assembly and packaging of multiple separately manufactured components into a higher-level assembly that, in the aggregate, provide enhanced functions and improved operating characteristics. Higher-level assembly includes homogenously integrated SoCs, SiPs, or MCMs. This involves system design, algorithms, and software.
The packaging toolbox provides the characteristics for the different use cases. The toolbox has functions for interconnecting, materials, architecture, etc. For the SiP packaging toolbox, there are the new embedded technology that interconnect via electroplating. Thin active chips are embedded into the di-electric layers. Passive components are also embedded with the chips, as are SMD components.
Challenges include the remaining di-electric thickness has been decreasing, as are the multi-material challenges. Multiple additional functions also emerge for SiP packaging toolbox. Cost is an important issue, as are customer requirements, testing, assembly, co-design, and standardization. It is important to remember that all package materials will continue to change over the next 10 years.
Compact SiP requires material knowhow, along with understanding failure. There are also plating challenges, thermal and mechanical issues, corrosion, electrical, and new semiconductor materials, such as SiC, GaN, and new Ga2O3.
Heterogenous integration drives the interconnect density. We have developed a consortium to understand the challenges of panel-level packaging. These include Amkor, Dupont, AT&S, Hitachi Chemical, Ajinomoto, Evatec, ASM, RENA, etc. Warpage and die-shift control provide process understanding that enables high-precision RDL layers (or, dielectric layers).
SEMI, USA, organized the Technology Week seminar. Day 1 focused on power electronics and devices. Ms. Veronique Sousa, CEA Leti, presented on the technological challenges for MOS HEMT (metal-oxide-semiconductor high-electron mobility transistor) GaN power devices.
There are wide band gap semiconductors. WBG and UWBG semiconductors are used for low-frequency unipolar vertical power switches. WBG apps range features SiC and GaN. SiC is quite mature. Looking at the long-term GaN power market evolution, GaN devices dominated the consumer market segment in 2018. By 2024, it will be introduced in the automotive market, and later, the industrial segment, by 2030. By this time, the industrial market will take off, and consumer and automotive markets will co-exist.
There are the N-ON GaN technologies. Examples are the P-GaN HEMT, hybrid drain GIT, and MOS HEMT GaN. P-GaN is in production at TSMC, and in R&D at IMEC. Hybrid drain GIT is in production at Panasonic and Infineon. MOS HEMT GaN is in R&D at ST/HRL, Toshiba, and Leti. Looking at the description of the main building blocks, there is epitaxy GaN on Si and passivation, recessed gate structure, and drain/source ohmic contact.
The pGaN FET architecture of devices is now available on the market for several “end-users” applications. CEA/LETI has develop another approach to meet the requirements of power electronics with an isolated MIS GATE HEMT GaN solution. This option is on its way to reach an industrial level of maturity.
A GaN-on-Si epitaxy has been developed. There are no holes for 10mm2 devices. As for DC device characteristics, there is positive Vth of 1.85V, but 500mV hysteresis is likely, due to the gate dielectric charge trapping.
There are technological challenges such as carbon contamimation. Yet another is gate trench etch. ALE process reduces the damage by conventional etching. There is the investigation of the etch impact on the trench profile after conventional etching and atomic layer etching. A new differential method allows to evaluate the contribution of the gate edge regions in the total MIS-HEMT device conductance. Another challenge is the wet clean before the high K deposition. There is the effect of the wet treatments prior to ALD of Al2O3.
We have shown the MOS-Gate stack. Ohmic contact on ALGaN/GaN is required. There is low resistive CMOS-compatible ohmic contact (Ti/Ai) on AlGaN/GaN. MOS gate HEMT GaN power devices have shown promising perspectives. Isolated gate provides its intrinsic benefits in terms of leakage and di-electric lifetimes. The ageing of gate stack should be pursued before starting reliability evaluation of the device.
Here is part two of the SEMI Silicon Valley Chapter and SEMI Northeast Chapter conference on semiconductor outlook for 2021.
Dan Hutcheson, CEO, VLSI Research, presented on how the pandemic has turbocharged digitization. There are macro factors driving the semiconductor industry. Covid-19 closed one door and opened another. We have since gone from rainy situation to a sunny situation. The semiconductor industry had prepared the world for Covid-19. This year has started really strong. IC market growth has been slowing because of Covid-19.
This year, VLSI Research’s forecast for semiconductor equipment industry is about 20 percent. Zooming in on critical IC market segments, semiconductor sales growth should be +13 percent.
Focusing on IC market growth this week, the 13-week MA shows 2021 has kicked off on a strong growth path. Unlike the last 2 years, DRAM, NAND, auto, analog logic, and power are in a tight growth pattern – most recently ranging from +14 percent to +19 percent. In 2019, DRAM and NAND sung the blues after a hot 2018. 2020 was the year for auto ICs to be blue. With all the news of an auto IC shortage, this market is clearly hot. The auto IC sales are forecast to grow 21 percent. Seeds of auto IC shortage in 2020 were sown in poor supply chain management.
DRAM is very data-driven and forecast to grow 21 percent. NAND IC sales is forecast to grow 15 percent, as well. Analog IC and power discrete sales is forecast to grow 12 percent. Logic IC sales is forecast to grow 10 percent.
IC supply/demand trends
Looking at the IC supply/demand trends, IC wafer fab production levels continued to rise last week at ~20 percent above 2020 levels, with production levels above 2M 300mm equivalents per week. Supply/demand status held tight for the week. DRAM jumped, NAND and IDM tightened, while foundry, OSAT, and analog and power loosened. The 1Q nowcast is tight
In semiconductor utilization, all sectors are high. These include wafer fab, test, and packaging. Electronics’ prices are also declining. These include TVs, PCs, notebooks, tablets smartphones, cell phones, digital cameras, appliances, etc.
Looking at semiconductor inventory, the inventory-to-billings ratio is in an expansionary range, and ~0.25 below critical levels. Total IC inventories are in decline, suggesting high fear levels at the start of 2021.
Semiconductor/semiconductor capital equipment 2021 outlook
Harlan Sur, Executive Director, JP Morgan, presented semiconductor/semiconductor capital equipment 2021 outlook and long-term trends. Semiconductors/semicap stocks have outperformed the market over the last 1, 3, 5, 10 years.
Drivers of the strong stock performance include the realization that semiconductors are the foundational building block for all innovation in the technology sector — applications/devices/appliances are getting more intelligent and requiring higher levels of semiconductor $ content. There is lower cyclicality in the industry driven by end-market diversification and disciplined supply growth. Lower cyclicality drives more focus on profitability and free cash flow expansion, leading to strong capital return to shareholders.
Industry consolidation (M&A) is expected to drive diversification, R&D scale, and enhanced profitability and capital returns. Near-term, there is positive Y/Y inflection in semiconductor company revenues in 2H20, and expectations of industry growth through 2021. We expect long-term positive fundamental trends to continue going forward. Semiconductors have been in more stable growth phase. There is focus on market leadership, strong product cycles, margin/free cash flow expansion, and capital allocation.
End-market diversification and lower industry cyclicality drives more focus on profitability and cash flow. As operating margins and free cash flow margins have expanded, companies put in place strong capital return programs, driving higher valuation multiples. Industry consolidation has driven valuation multiples higher over time.
Semiconductors/semicaps growth and cyclical trends remain positive entering 2021 and beyond. We believe the semiconductor industry has entered a more stable and less cyclical growth phase characterized by low- to mid-single-digit annual revenue growth and high-single-digit unit growth. With the industry generally driving high-single-digit Y/Y unit growth, the entire value chain is able to better predict silicon consumption requirements, better respond to perturbations in supply/demand, and more efficiently plan manufacturing output. As a result, volatility in semiconductor supply/demand and semiconductor equipment spending has muted significantly.
Compare this to 15-20 years ago, when unit growth rates were +15 percent Y/Y – small perturbations in supply/demand would drive significant swings in inventory, shipments, capacity planning, and equipment spending. Bottom line: The current environment is likely more stable and less cyclical for semiconductor and semiconductor capital equipment suppliers. In a maturing industry, we believe the market will focus on market leadership/scale, operating margin and free cash flow margin expansion, and increasing payout ratios.
We see the semiconductor industry revenue up 10-12 percent Y/Y (bias upward) in 2021, following a 7 percent Y/Y growth in 2020. If you recall, the 2H20 demand picked up significantly and growth turned positive after 1H20’s weak demand environment and supply chain disruptions (Covid-19). In semiconductor equipment, we see spending up ~16 percent Y/Y in 2021 led by DRAM and foundry strength.
As for supply constraints across all end markets, we see multiple quarters of strength for the semiconductor suppliers. Channel/customer inventories are at/near historic lows, and lead times are continuing to get stretched out. Given the strong demand environment combined with supply tightness, we anticipate strong demand trends through 2021.
We expect continued industry consolidation (M&A). There is focus on scale, diversification, and margin and FCF expansion. There is promising outlook for foundry/memory in 2021, with demand and capex spending driving strong semiconductor equipment fundamentals. Potential investment in US domestic manufacturing capability is a positive, with innovation and assurance of the supply base.
Industry consolidation should also support valuations. We can expect more M&As to happen. Semiconductors are consolidating focus on building scale and driving profitability improvements, End-market diversification, etc. Consolidation should drive more stable revenue growth and improve margins. Less competition leads to less pricing pressure. There will be more market leadership and diversity. In 2015-2018 have seen $100 billion+ per year in M&A deal activity vs. the $20-30 billion run-rate prior to this time period.
M&As are characterized by big getting bigger. Going forward, we expect to start seeing a lot more M&A activity with the smaller/medium-sized companies, as there is pressure to drive scale to compete with much bigger competitors.
Data center fundamentals strong
Strong data center fundamentals, led by cloud service provider (CSP) spending are driving strong demand for compute, networking, and memory/storage semiconductors.
Look for companies levered to data center trends to outperform in 2021 across compute, networking, and storage/memory after digestion cycle in 2H20. CSP spending (top 4) grew by 10 percent in 2020 and was up 6 percent in 2019. We expect cloud spending to reaccelerate in 1H21 and grow 25percent+ in 2021, and at 10-15 percent CAGR over the next few years.
Cloud services revenues continue growing >40 percent + Y/Y. Over the next 5 years, CIOs should grow spending on public cloud by 4x. Early ramp of new processors by Intel, AMD, Nvidia, and ARM will see adopters. Silicon switch ports (>25Gbps) should grow 23 percent CAGR. DRAM memory content in a cloud server is 50 percent higher than traditional enterprise server – OW MU. Data center compute acceleration is growing >25 percent CAGR, driven by higher complexity workloads (AI/Deep Learning, analytics, etc.).
Resurgent custom chips
Custom chip (ASIC) market is experiencing a resurgence in activity as large OEMS, cloud, and hyperscalers look to differentiate at the silicon level — $10-$12 billion silicon market opportunity. Demand is rising for custom ASICs as many large OEMs/CSPs/hyperscalers are looking for more differentiation, better performance, lower power consumption and overall lower cost of ownership versus off-the-shelf chip solutions (or ASSPs).
These same customers do not have the capabilities to do large complex SoC) designs, nor do they have the broad IP portfolio of on-chip design blocks, like high-speed SERDES capabilities or high-speed memory interface technology. They need to engage with semiconductor companies (ASIC companies) that have the IP and chip design expertise (Broadcom, Marvell, Intel, MediaTek as examples).
The digital custom ASIC chip market is a ~$10-$12 billion per year market opportunity. These include cloud/hyperscale ASICS (AI processors, smartNICs, security/video processors, networking/storage acceleration). Telco/service provider equipment OEMs also see growth, for 5G base station modems, 5G digital front ends, 5G MIMO/beamforming DSPs, and coherent DSPs for long haul/metro.
There are 5G opportunities too. These benefit wireless infrastructure and wireless RF smartphone market leaders. 5G base station deployments are growing by more than 22 percent CAGR (2020-2023E). 5G base station estimates are growing from 2020’s ~800k to 2023’s ~1400k. We expect North America activity to pick up in second half of the year followed by Europe in 2022.
Digital semiconductors are growing from ~$3 billion in 2020 to ~$4 billion in 2023. Analog semiconductors will grow from $0.8 billion in 2020 to $1.1-$1.2 billion in 2023. This is a positive for players like Broadcom, Marvell, Intel, Analog Devices, Xilinx, Qorvo, NXP, etc. Massive MIMO/Beamforming are key enablers of 5G sub-6 GHz and mmWave to increase network capacity, data rates with better energy efficiency and TCO. GaN opportunity scales with number of antenna elements. GaN market will grow from ~$350 million in 2020E to ~$550 million in 2023E (15-20 percent CAGR).
5G smartphone complexity benefits the RF market leaders such as Qorvo, Skyworks, Broadcom, etc. The market is growing at 10-12 percent CAGR (2019-2022E). 5G smartphone estimates are growing from 2020’s 225 million to 2022’s 725 million. Ramp of 5G to meaningfully increase RF market opportunity primarily on new sub-6 GHz content, millimeter wave, are also additive over the next few years. There will be ~$5-$7 of incremental 5G sub-6 GHz content. This is positive for Qorvo, Skyworks, Broadcom, etc. Core base component expertise will grow, across PAs, switches, premium filters, etc. It is difficult to insource with lack of foundry model/merchant filter vendors.
Demand growth has been accelerating in memory. Pricing should improve meaningfully in DRAM in early 2021, while price declines in NAND are still moderate. Bit demand in DRAM and NAND should accelerate in 2021. DRAM bit demand should increase to >20 percent with strong demand for server and mobile DRAM. The NAND bit demand should increase to ~40 percent led by SSDs and mobile devices.
There is supply tightness in DRAM, as a result of lower DRAM capex in past two years. It should lead to improved pricing and ASP increases in 2021. NAND market is still in oversupply. ASP declines are set to decelerate later in 2021.
Capital intensity has been increasing across the device types. This is a positive for semiconductor equipment. Increasing capex should drive bit growth for DRAM and NAND. NAND capital intensity for 12X layer should be >50 percent higher than 4X layer NAND. This will require increasing the capex to drive bit growth for DRAM and NAND. Capital intensity is also increasing for foundry/logic, even as EUV has begun ramping. There is 5nm capital intensity that is >50 percent higher than 14nm/16nm. Increasing capital intensity is positive for semiconductor equipment companies, as spending on equipment will likely have a higher floor and be less cyclical over the next several years.
Looking at the wafer fab equipment (WFE) forecast and key programs for semiconductor manufacturers in 2021, we estimate WFE spending is on track to increase by ~16 percent in 2021 to nearly $70 billion.
We expect memory to recover in 2021 led by DRAM on improving supply/demand fundamentals with foundry/logic spending sustainable. Key drivers include following muted memory WFE in 2020 that was held back on supply discipline, we expect memory spending to accelerate to double-digit percent in 2021 led by DRAM. We expect continued foundry/logic spending strength in 2021. This will be broad-based across leading and lagging edge technologies. China spending should remain strong in 2021 as local manufacturers come up the learning curve.
SEMI Silicon Valley Chapter and SEMI Northeast Chapter organized a conference today on Semiconductor Outlook — Navigating Through Turbulent Times – Is the End Near?
David Anderson, President, SEMI Americas, said that the pandemic saw our homes become offices. We had to adapt quickly and our industry kept on going. He added that the Semicon West 2021 has been rescheduled to Dec. 7-9, 2021, in San Francisco, USA.
Memory and storage in data economy
Indradeep Ghosh, Senior Director, Market Intelligence, Micron Technology, talked about memory and storage in the data economy. Electronics today has become a necessity of life. We have seen an acceleration in digital transformation. Memory and storage consumption has been accelerating. DRAM and NAND consumption has been growing per capita. DRAM and NAND revenue has been growing faster than the semiconductor industry.
Technology innovation has unlocked the data economy. Two major trends are AI and 5G. The data-centric cloud is moving to the intelligent edge, on to devices. They are accelerating innovation. New wave of innovation will transform the multiple industries over the next decade. These include mobility, healthcare, media and entertainment, agriculture, and industrial.
A few examples are connected smart vehicles and fully autonomous driving, remote health monitoring and early progonosis, remote operations and IoT in hospitals, immersive media, AR/VR and ubiquitous live streaming, AI-enabled user generated content, robotics, drones, satellite and soil sensors, end-to-end traceability for food safety and spoilage, and cloud control of machines, AR, video analytics, etc.
Data center DRAM is critical for compute-intensive apps. There will by ~13X AI server adoption by 2025. AI servers have ~6X the DRAM content of industry-standard servers. AI will become more pervasive. AI core use cases will be in business apps, content and collaborative, data management, gaming, media streaming, and web and app servers. AI use cases will also be in recommender systems, conversational technologies, image and video analytics, autonomous driving, cyber security, smart manufacturing, etc.
Data center NAND will be critical for data-hungry apps. NAND content on servers will more than double from 2020-2024. There will be 32 percent CAGR data center storage bit shipment growth. Few high-growth apps include structured data analytics, content apps, collaborative apps, app development and testing, etc. Performance will be across unstructured data analytics, media streaming, security, virtual desktop infrastructure (VDI), and engineering/technical apps.
Automotive will be the fastest growing memory and storage market. Content today is mostly infotainment driven. The ADAS adoption will be huge, with L1/L2 ~50 percent in 2020, and L3 <10 percent in 2025. Growing capabilities will be in large screen digital cockpit, ADAS L1/L2 and L3, event data recorder/driver monitoting, and telematic gateway.
In mobile, 5G will drive the smartphone content growth. There are growing 5G use cases. In photography and social, there are use cases such as 100+MP snapshots, 4K/8K video capture, triple picture/video capture, AI-enhanced real-time editing, 4K video livestream, LiDAR and advanced sensors. In entertainment and gaming, there are 4K display/immersive media, AR/VR shopping and gaming navigation, eSports/desktop-level gaming, etc. For healthcare and fitness, there are advanced sensors, AI-based health monitoring, etc.
For PCs, there will be new use cases driving a resurgence in demand. PCs saw double-digit growth in 2020. They are an essential device for WFH and remote learning. There are expanding use cases, such as video conferencing, apps to create, collaborate and productivity, entertainment, gaming and social.
The long-term DRAM bit demand CAGR will be of mid-high teens. The long-term NAND bit demand will be CAGR of approximately 30 percent.
State of EDA
Next, Jay Vleeschhouwer, MD, Griffin Securities, presented the state of EDA. The combined enterprise values of Cadence Design and Synopsys are ≈$80 billion, or more than 12x 2020 combined revenues, and almost 12x estimated 2021 revenues.
Five years ago, the combined enterprise values of Cadence, Synopsys and Mentor was ≈$16.1 billion. The material increase in value has been sustained by a combination of bookings growth, increasing backlog, increasing operating income (up 115 percent over the past half-decade), and increasing operating cash flow (up more than 115 percent over the past half-decade).
We estimate that EDA industry revenue increased by 11-12 percent in 2020 to more than $9.2 billion. The industry has continued to consolidate. Cadence and Synopsys – the Big 2 – accounted for ≈66 percent of industry revenues, as compared with ≈64 percent in 2015 and ≈53 percent in 2010. Mentor has also sustained its prior, pre-acquisition average share (19-20 percent), since it was acquired by Siemens in 2017. Mentor has shown good momentum in physical
verification (Calibre) and PCB. Synopsys-Cadence-Mentor-Ansys have nearly 90 percent of the industry revenues.
For 2021, we are estimating that Cadence’s revenues will increase 7 percent to $2.56 billion, and Synopsys’ EDA revenues will increase 7 percent to nearly $3.7 billion. Similarly, we are estimating that Ansys’ EDA business will increase by 7 percent to more than $360 million.
The earlier dip in EDA revenue was due to the recession. Japan has lost share, while Europe has gone sideways. Mentor has retained its revenue share. while Cadence and Synopsys have also increased their revenue.
The combined Big 2 EDA bookings were $5.89 billion in 2020, up ≈15 percent. We are estimating $5.93 billion for 2021 and more than $6.5 billion by 2023 – consistent with an expectation of better than mid-single-digit bookings growth and continued increases in backlog. The combined Big 2 backlog was $8.5 billion as of the end of 2020, up from $8 billion as of the end of 2019. We are estimating as much as $9 billion by the end of 2021. The combined EDA Big 2 operating income in 2020 was $2.075 billion, or 31.9 percent of revenues, vs. $1.574 billion in 2014, or 27.6 percent of revenues, and $967 million in 2015, or 24.4 percent of revenues.
For 2021, we are estimating combined income of $2.26 billion, or 32.5 percent of the estimated revenues, and $2.75 billion by 2023, or more than 35 percent of the estimated revenues.
Growth has been diverse, across many categories. This diverse base is expected to continue and be a driver. According to industry data, IC implementation, PCB, synthesis, analog/mixed-signal simulation, analysis, custom layout, and hardware-based verification have each had multiple consecutive periods of growth on a trailing-twelve-month (TTM) basis, plus improving trends for physical verification and RTL simulation.
The regular, co-inciding demand across multiple product categories by both the semiconductor and systems customers has been fundamentally conducive to EDA revenue growth – and, this phenomenon is very likely to continue. Each one of the EDA Big 4 – Synopsys, Cadence, Mentor and Ansys – participates in at least two of the growing categories. In physical verification, Mentor has dominated.
One of the most important product mix changes over the past 5-10 years has been growth of hardware-based verification (emulation and prototyping). The combined Cadence-Synopsys hardware revenues were more than $470 million in 2020, nearly doubling from 2015. Combined EDA IP revenues for Cadence and Synopsys were ≈$1.39 billion in 2020, (over 20 percent of combined revenue), vs. ≈ $1.1 billion in 2019, and more than ≈$620 million in 2015. The 2015-2020 CAGR for Big 2 core EDA software revenues (ex hardware and IP) was about ≈6 percent.
Two arms races
There are two arms races underway in technology: software development and silicon development. The investments in silicon development – by semiconductor companies, still the majority of EDA revenues, and the always important class of systems companies, e.g., Apple, Microsoft et al – are dependent upon EDA’s role as a source of essential technologies and services, and as such are sustaining the EDA industry’s revenue, income, and cash flow momentum.
The EDA industry growth has been sustained by growing demand among multiple EDA tool categories – as compared with earlier periods of more narrowly based growth. This has been, and is likely to remain, an important phenomenon, supported by the growth of semiconductor R&D budgets and systems customer product engineering budgets. These customer investments are in turn sustaining, and enabled by, EDA investments in R&D.
In 2020, the combined Cadence-Synopsys R&D was more than $2.35 billion (≈37 percent of revenues), vs. $2.116 billion in 2019, $1.429 billion in 2015 and $845 million in 2010. Cumulative combined R&D over the past decade (2010-2020) was more than $15.7 billion. We are estimating almost $2.5 billion for 2021 and more than $2.72 billion by 2023.
In semiconductor R&D, a composite of more than 25 semiconductor companies showed total R&D of $45.1 billion in 2019, up 2 percent. Intel accounted for ≈30 In semiconductor R&D, of this total. For the TTM ended 3Q20, total R&D was more than $46.8 billion, up almost 4 percent. The total R&D spending, excluding Intel, was up almost 4 percent in 2019 and ≈6 percent for the TTM ended 3Q20.
Among the semiconductor companies that have reported 2020 results, AMD’s R&D increased by 28 percent, Infineon’s by 29 percent, Intel’s by 1.5 percent, NXP’s by 5 percent, Nvidia’s by 39 percent (including Mellanox), Renesas’ by 2 percent, and ST’s by 3 percent. We have calculated that Intel’s commercial EDA spending accounts for as much as a high-single-digit percent of EDA industry revenues (more than $625 million in 2020). About three-fourths of its spending is with Synopsys, plus Cadence, Mentor and Ansys. There has been good bookings for the big 3 players over an 8-year period.
Part 2 continues later.
There was a panel discussion around sustainability and power at the ongoing SEMI Flex 2021. The participants were Prof. Pradeep Lall, Director, Auburn University, Joseph C. Bush, VP Business Development, Battery Resources, Zachary A. Combs, Innovation Manager, Materials, Birla Carbon, Brian Berland, CTO, ITN Energy Systems, Andrew Manning, President and CEO, Lithium Battery Engineering, and Brian Zahnstecher, Principal, PowerRox LLC.
Pradeep Lall said that from a thin flexible battery standpoint, it is more of a new architecture. If we use these for asset monitoring, they might be dynamic. Less is known about these dynamic loads and how do we test for them. Inter-relationship between the variables are not yet understood properly.
Brian Berland said that some batteries need high power, etc. When you go to the highest energy density batteries, and start to integrate, it involves inductors, capacitors, etc. That can take away some of the advantage.
Andrew Manning noted that design factors go into the making of a battery. One challenge is the economic challenge. It costs money for a manufacturing line. Unless you standardize on a format, the cost of a battery can get expensive. The average cost of smart card battery is about 80 cents. We have to think more about developing something that is manufacturable.
Joseph C. Bush added that talking about tiny batteries make ones wonder about consumer behavior. We need to see the product is economical and functional in its life. We need to design with the end in mind. At least 50 percent of consumer electronics is now recycled. What’s going to happen to the batteries, though?
Zachary A. Combs said they are supplying raw materials in the market so those can use existing and re-useable manufacturing processes. We have a significant supply chain. North America is building a superior supply chain.
Brian Zahnstecher added that there are sources and loads are tied together. We also have to look at how they impact, up to the source, particularly, wireless. Base stations are one of the worst offenders. The key is to take a disaggregation model, as in the data centers. There are distributed energy resources. Economics of renewable sources, especially PV, have also become reasonable. The universe of currency is energy. The energy impact on policy making can also be made. The goal of our group is to educate about energy optimization.
When do we run out with resources? There are EV companies, as well. Pradeep Lall said some of the elements may be less prolifically available. That seems to be a moving target. The industry is moving the target more for recycling. We are trying to get similar performance from the recycled batteries. The targets are also moving away, as well. People are also looking at supercapacitors.
Joseph Bush said they recycle over 95 percent of the batteries. Over 28 percent of them can go straight to battery manufacturing. We are going to see incredible performance changes. There is the Tesla EV model that works great. Can they be LFP (lithium ferrophosphate) batteries? We are going to see diversification of chemistries.
Zachary A. Combs said the Li-ion batteries have a hockey stick approach. LFP batteries may come in. There is certainly going to be a raw materials strain, maybe, later. Brian Berland said there are mm-sized batteries that can last for some time. The cost of materials is important. Andrew Manning added that we do have raw materials problem, which will work itself out. We need to see where are we going to get the energy to charge all of these batteries.
Brian Zahnstecher said that we should focus on energy harvesting. Reality occurs in many business domains. When it comes to BOM cost, why should one replace a 10 cent battery material? There is self-powered battery. We can do preventive maintenance for expensive equipment. Joseph Bush added that it is a problem recycling lithium-ion batteries. The economic model needs to be looked at. Who is footing the bill for electrification?
Standards and technologies are required for final acquisition decisions. Brian Zahnstecher said there is a systems framework that needs to be standardized. We are proposing a framework. Pradeep Lall added that new batteries have to conform to established standards for the rigid batteries. We can expect to see standards developed.
Ms. Christine Ho, CEO and Co-founder, Imprint Energy, presented the keynote on green batteries for blending electronics in our daily lives on day 4 of the ongoing SEMI Flex 2021.
There is an urgency to deploy over 100 billion IoT devices to eliminate over 15 percent of our GHG emissions by 2030. IoT devices can be designed to have over 10x sustainability. There is also a call to reduce the global emissions by half by 2030. The transformation proposed is necessary and achievable.
The digital sector has the potential to directly reduce fossil fuel emissions by 15 percent by 2030, and indirectly support further reduction of 35 percent across other sectors through the influence of consumers and business decisions, and system transformations. A connected IoT network will provide data for our daily decisions. IoT will be the digital skin that protects the earth. We are on track to deploy 125 billion Internet-connected devices by 2030.
As an example, Covid-19 vaccines are very temperature sensitive. We have to find a way to reduce wastage and damaged goods. Smart tags are made possible by technology innovations. They exist today as electronics can be flexible and robust. Tags are composed of wireless chip, battery and an antenna. The battery is the single-largest carbon footprint indicator. Imprint Energy has thousands of roll-to-roll screen printed batteries. So, how do we build sustainable power sources for the next trillion IoT devices?
By reducing the carbon footprint, one can maximize resources. There is a unique opportunity for companies to lead. We have the responsibility to provide greener batteries to achieve our sustainable goals. We can start by choosing lower carbon footprint raw material. We can choose sustainability-focused suppliers. We can also reduce manufacturing factory size and distribution of carbon footprints. We can extend the usage and find pathways to re-use and recycle batteries. Battery companies can also work with designers to improve battery lifetime. Imprint Energy has designed a sustainable and high performance battery to blend electronics into our lives.