CHIPS R&D workshop addresses digital twin data interoperability standards

Posted on April 4, 2024

Digital twins in manufacturing enable proactive decision-making, predictive maintenance, scenario testing, and collaboration among stakeholders, etc. This workshop will focus on standards needs for a specific use case, application of a digital twin for manufacturing in the chiplet-packaging module.

CHIPS R&D, USA, organized a conference today. Participants discussed the potential for digital twin technologies to drive progress in the semiconductor and microelectronics industry. They looked at the role of data interoperability standards for digital twins in semiconductor manufacturing ecosystem.

Factors to be considered in identifying standards priorities include potential for broad impact, feasibility for accelerated development, and suitability for various standards development channels, including through alliances, incubators and accelerators, and standards setting organizations.

CHIPS Manufacturing USA
Eric Forsythe, CHIPS R&D, provided an introduction to CHIPS Manufacturing USA. We have a funding opportunity and context. CHIPS Manufacturing USA falls under the CHIPS Act. We will try and solve problems, specifically for the digital twin. We have a workforce initiative going on, as well. We are focused on workforce development. Within the R&D portfolio, we have Natcast, NAPMP, CHIPS Manufacturing USA, with 17 institutes across the network, and CHIPS metrology program.

Manufacturing USA purpose is to accelerate the discovery to US production. We are creating an effective collaboration for applied industry research to bridge the gap from discovery to production. The process has basic research, proof of concept, production in lab, capacity to produce the prototypes, capacity in the production environment, and the demonstration of production rates.

We have minimum NIST commitment of ~$200 million over a five-year period. We are analyzing RFI responses, industry feedback etc., for digital twins. The objectives include reduce time and cost for chips development and manufacturing. Accelerate adoption of the semiconductor manufacturing innovations. We are also increasing the access to semiconductor manufacturing training, etc. We have established the shared resources capabilities, competitively fund industry-led technical and workplace development projects. We have digital framework for interoperable data, shared and validating data, etc. We are also creating a shared marketplace of digital twins model.

Digital twins in semiconductor manufacturing standardization
There was a panel discussion on defining the landscape, scope, and focus of digital twins in semiconductor manufacturing standardization efforts.

Kemaljeet Ghotra, Enterprise Data Strategist, PDF Solutions, said digital twin is a virtual representation of the physical world that is capable of producing intelligent feedback with simulation, emulation, data analytics, and modelling.

We are now developing virtual process, tools and devices, and virtual fab. Data is the horizontal across all. We have grand challenges such as generating data, create models, share, and use data, with security around it. Digital twin framework requirements include DT re-usability, interoperability, validity and verification, maintainability, capability, extensibility, accuracy, security, provenance, hierarchical relations, historian model life cycle, etc.

We need to have an operationally focused digital twin for the extended semiconductor supply chain. We need to bring in the end-to-end traceability for products. Operational DT allows for centralized management of globally distributed supply chain to be built on PDF’s Extensio platform capabilities. We need to allow sharing of data in much more secured environment.

PDF has AI models for automation and real-time insights for DT. We have added fault detection and classification, predictive maintenance, virtual metrology and sensing, and fab predictive model in the PDF solution. The operational DT leverages and expand PDF’s existing solutions and market presence. Focus is to get off different proprietary data types to be able to talk to each other.

James Moyne, Research Scientist, University of Michigan, stated that the scope of DT is across the manufacturing ecosystem. We have existing DT solutions. New ones are emerging from improved ecosystem integration, and solution integration. We also have improved reuse of solutions.

Enabling collaborative DT environment across the industry requires agreement on specs for DT and DT framework. DT is a purpose-driven digital replica of physical asset, process, system, or product. It quantifes prediction and prediction accuracy. The DT framework involves aggregation and generalization examples.

We need to understand requirements driving DT and DT framework definition. We have already done lof of work to identify requirements. We have a path forward for getting results into industry practise, such as International Roadmap for Devices and Systems (IRDS), SEMI, and other standard organizations.

Ben Davaji, Asst. Prof., Northeastern University, stated that development of targeted domain-specific DTs could be more efficient. DT for semiconductor manufacturing includes manufacturing process — such as drifts, aging, tool PM, diagnostics, etc. We can accelerate process development and characterization for manufacturing equipment. We can develop new process equipment and reduce evaluation times.

We can enable fast adoption of novel and emerging materials and substrates. We can do innovation in process design to enable novel device architectures. We can enable accelerated PDK development, etc.

DT for nanofabrication involves DUV lithography process and plasma etch process as examples. He talked about DNN-enhanced virtual metrology. We can have minimum viable DT with data standards, quantitative and multimodal data, TCAD and EDA to generate large data sets and calibrate using experimental data.

We can have DT black box from tool manufacturer and material suppliers. We can develop process and test datasets. We can have computational infrastructure to support secure computing and federated learning. We can also have an open environment for the integration of DTs, enabling interconnections.

Serge Leef, Head of Secure Microelectronics, Microsoft, we have been witnessing the convergence of electronics and physical worlds. DT was limited to chip-level modeling and simulation. We are seeing computing continuum up to 2030.

Modern systems are domain specific, highly heterogenous, distributed over networks, highly interactive with physical world, etc., and everything really has to work together. Physical prototyping for complex systems is a huge task. Typically, one or two prototypes can get built. We also need to have DT simulation, with heterogeneity challenge.

We now need to execute meaningful scenarios at near-real-time speed at near-zero modelling cost to gain actionable insights. Microsoft has developed vision for automotive and aerospace DTs. There are some walls between disciplines that need to be broken down.

Cloud-based architecture is leveraging speculative parallelism. We need to use ML to train reduced order models on real-world data. We have standards opportunities for simulation backplanes, modeling interfaces, and testing frameworks.

Gurtej Sandhu, Principal Fellow and CVP, Micron Technology, noted we have an end-to-end Si virtual model. DT of chip fab is virtual model of the entire process flow to accelerate technology development and ramp to inline and packaging yield.

Cost of developing chips is increasing exponentially. Tools are needed to make more informed decisions and build faster process flows. Successful collaborations require multi-disciplinary collaboration across the entire framework of chip building discipline, structure and materials, etc. Achieving this requires breakthroughs in multi-scale modelling. We also need partnerships among chip makers, tool providers, etc.

We have the fab technology co-optimization (FTCO) framework. We can have DT models on the top. It can be followed by metrology, process, tools, efficiency, and partners. A module-level co-optimization requires over 20 process steps/modules. A typical fab co-optimization requires over 1,000 steps. The DT platform is a virtual test bed. Members can develop tools/models, access data for testing/validation, and deliver DT solutions.

Victor Zhirnov, Chief Scientist, Semiconductor Research Corp. (SRC), talked about DT for microelectronics. SRC is creating CHIPS Manufacturing USA Institute. SEMI is partnering with SRC. DT should have plug-and-play capabilities. It is a tool for rapid innovation enablement. The MAPT plan is call for DT infrastructure.

We need to look at data standards that can be applicable for electronics manufacturing, We are quite familiar with design automation, modelling and simulation, and industrial automation.

Standards must be set to enable interchange of materials and 3D data between various entities involved in SIP design and manufacturing, Key drivers include multiple physics field nature of design. DT interoperability is currently a problem. We need universal standard to cover use cases.