CHIPS metrology research that accelerates innovation

NIST, USA, organized a seminar on the CHIPS metrology: Research that accelerates innovation. CHIPS for America Programs include $39 billion for manufacturing, and $11 billion for R&D.

The CHIPS and Science Act strategy is informed by extensive engagement with semiconductor industry leaders and stakeholders across all fields. NIST was selected as the bureau within DOC to house these new units. 2030 goals include: US technology leadership, accelerate ideas to market, and a robust semiconductor workforce.

Marla Dowell, director of the CHIPS Metrology Program, discussed how CHIPS for America advances metrology research essential for next-generation microelectronics. To address gaps in the semiconductor ecosystem, CHIPS for America is investing in four overlapping entities, all of which include some aspect of workforce training. These programs will share infrastructure, participants, and projects. They will operate in coordination with each other, with the CHIPS for America manufacturing incentives program, and with microelectronics R&D programs supported by other US federal agencies.

The entities are: National Semiconductor Technology Center (NTSC), National Advanced Packaging Manufacturing Program (NAPMP), Manufacturing USA institues (up to three), and Metrology Program.

Metrology is foundational and fundamental for all CHIPS R&D. Metrology solutions are delivered to the industry stakeholders. High-impact research areas are sourced from industry. Metrology technologies should reach commercial scale.

Opportunities are being created for industry, government partners, and academia to participate in CHIPS for America and the CHIPS Metrology Program. You can collaborate with the Metrology community. CHIPS Metrology will help foster collaboration among the semiconductor community with focused groups based around each Grand Challenge. Members of the semiconductor space will have the chance to join webinars, in-person poster sessions, networking sessions, community chat, etc. This is an opportunity to share knowledge with other stakeholders and learn about what other projects are working on.

What is METIS?
METIS, or the Metrology Exchange to Innovate in Semiconductors, is a data exchange ecosystem developed by NIST that will give stakeholders access to CHIPS Metrology research results and serve to catalyze innovative breakthroughs in US semiconductor manufacturing.

METIS will make research and data available in a manner that guards intellectual property, protects US security interests, is aligned with the approach used by NIST for access to research results, and is self-sustaining to meet future needs.

Grand challenges
There are Metrology Program grand challenges. GC1 is materials purity, properties, and provenance. GC2 is advanced metrology for future manufacturing. GC3 is enabling metrology for integrating components in advanced packaging. GC4 is modeling and simulating semiconductor materials, devices, and components. GC5 is modeling and simulating semiconductor manufacturing processes. GC6 is standardizing new materials, processes, and equipment. GC7 is security and provenance of microelectronic components and products.

There was an update on Grand Challenge funded research projects. Over $109 million in funding has been provided to 29 approved research projects over three Grand Challenges. These are in GC2, where, 10 projects were funded, in GC3, where, 6 projects were funded, and GC4, where, 13 projects were funded.

Current projects are helping to develop new measurement instruments, measurement methods, and measurement-informed models and simulations for advanced microelectronics design and manufacturing. Additional projects will be selected by the end of the year. As for industry and academia collaboration, research teams have proposed several distinct industry collaborators to provide materials and software and/or conduct joint research with researchers. Several collaborations with US universities, nonprofit consortiums, research institutes, and associations related to the microelectronics industries have also been proposed.

Ongoing research projects
Funded research projects in GC2 are: Accurate Measurements of Thermal Properties at the Nanoscale, Advanced Analytical Electron Tomography for Materials Development and Failure Analysis in Semiconductor Devices, Advanced Metrology to Enable Next Generation EUV Photoresists, Atom Probe Topography: Nanostructured Semiconductor Materials, Interfaces, and Devices, Critical Dimension Small Angle X-Ray Scattering (CDSAXS) for Next Generation in-line Metrology, Electron-Solid Interactions, EUV Scatterometry Metrology, Non-Destructive Semiconductor Structure Function and Process Optimization for future Microelectronics Manufacturing at the NIST NSLS-II Beamline for XAFS and Diffraction, Overcoming Barriers: Nanoscale Interface Metrology and Electrical Characterization for Advanced Electronics, and Strain Measurement for Semiconductor Devices and Packages.

GC3 Funded Research Projects are: Accurate Cure Kinetics, Stress, Mechanical Properties and Warpage Measurements for Next-Generation Microelectronics Packaging under Device Relevant Conditions, Characterization of nano-to-microscale process-induced thermo-mechanical changes in heterogeneously integrated microelectronics, Metrology of Materials, Surfaces, and Processes for Hybrid Advanced Packaging, Metrology forIntegration of New Magnetic Materials, Nanoscale, Element-Specific X-ray Imaging for Integrated Circuit Metrology, and Standardizing New Materials, Processes, and Equipment for Microelectronics — CalNet.

GC4 Funded Research Projects are: Advancing Power Electronics with Defect Metrology, Causal Green’s function simulations of phonons for multiscale/multiphysics modeling of thermal transport in gate-all-around transistors, Electro-acoustic metrology of piezoelectric materials for wireless communications, High Speed Metrology for Magnetoelectronic Devices and Models, Metrology of Nanoscopic Thermal Transport, Molecular Dynamics Simulation of Heat Transport in Gate-All-Around Transistors, Multiscale Modeling and Validation of Semiconductor Materials and Devices, Nanocalorimetry for Semiconductors and Semiconductor Process Metrology, Quantitative Assessment of Defects and Related Modeling Parameters in GaN Semiconductor Devices, RF Channel Propagation Measurements and Models for Communications Circuits, RF Metrology for Models of High-Frequency Transistors, Thermoreflectance Thermal Property Measurements for Heterogeneously Integrated Materials and Power Electronics, and Time-resolved emission microscopy for circuit evaluation and failure analysis.

Select research teams and their groundbreaking work.was also showcased. These are:

• Ann Chiaramonti Debay: Atom Probe Tomography: Nanostructured Semiconductor Materials, Interfaces, and Devices.
• Joshua Martin — Thermoreflectance Thermal Property Measurements for Heterogeneously Integrated Materials and Power Electronics.
• Jeff Shainline — Time-resolved Emission Microscopy for Circuit Evaluation and Failure.
  Analysis.
• Ran Tao – Accurate Cure Kinetics, Stress and Warpage Measurements for Next-Generation Microelectronics Packaging with High Thermo-Mechanical Reliability.