Advanced packaging heart of innovation: Yole

Posted on June 12, 2019 Updated on June 12, 2019

Advanced packaging is said to be at the heart of innovation. Favier Shoo, Technology and Market Analyst in the Semiconductor & Software division at Yole Développement, member of Yole Group of Companies, France, and currently based in Singapore, elaborated: “In the mega-trend driven era of the new digital age, there are key market demands, such as increased I/O and package size overlaps. Low-power consumption also requires packaging innovation and is demanded by many end-applications — from IoT to datacenters.

“In order to enable these new performance and functionality requirements, the industry needs a high level of innovation for disruptive technological breakthrough.”

Savior of semicon development
How has advanced packaging emerged as the savior of future semiconductor development? According to Shoo, the main driver in the semiconductor market is changing from mobile to more scattered applications in the future – IoT, automotive, 5G, AR/VR, AI.

Advanced nodes no longer bring the desired cost-benefit, so R&D investment in new lithography solutions and devices below 10nm nodes is rising substantially.

Advanced packaging, therefore, represents an opportunity to increase product value (higher performance at lower cost) offering advantages down both the scaling and functional roadmaps.

New developments in FO landscape
Now, let’s focus on significant new developments in the Fan-Out (FO) landscape. In the core Fan Out (FO) market, the existing players are expected to go compete on cost — between wafer-level vs. panel-level solutions. PTI has commenced Fan Out panel-level packaging (FOPLP) production in 2018, and has made huge investment for this (> 1 billion US$).

Within OSATs, the player who can first satisfy new application demands for mobile and automotive will lead the way, set new standards, and capture the market. In the HD FO market, high-end (mobile APEs) and high-performance (HPCs/networking) is still led by the only significant player, TSMC.

SEMCO has started high-volume manufacturing (HVM) by FOPLP for its Samsung Galaxy smartwatch. Inevitably, the HD FO battle stage is set up for TSMC and SEMCO/Samsung Electronics.

Fan-Out packaging: As the die size scales, reducing ball pitch to have more connections within the die surface may not be the ideal roadmap for chip performance. Hence, the adoption of Fan-Out level packaging.

Fan-Out can integrate dies flexibly at reduced thickness because it eliminates IC Substrate process while also cutting the cost. In short, Fan-Out packaging provides benefits in form-factor, electrical performance and SiP integration capability.

3D TSV/hybrid bonding: TSV, hybrid bonding, or a combination of the two, are the mainstream packaging technologies that are able to provide high-end performance at the integration level reached by the actual stacking technologies.

Huge demand for HBM2 memory: HBM2 has become standard for high bandwidth memory. With 2 main current players in market, Samsung Electronics and SK Hynix, Micron is set to enter HBM business in 2020. Development for the 3rd generation is still ongoing and we can expect much improved performance from this device.

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