Extending Moore’s Law via high-end packaging and advanced IC substrates

Yole Group organized seminar around extending Moore’s Law through high-end packaging and advanced IC substrates enabling a pathway AI generation, in France.

By 2029, high-end packaging is poised to hit $16.7 billion, fueling GenAI expansion through chiplet and heterogeneous integration. Advanced packaging market is set up to grow at a healthy pace, strongly driven by the mega-trends of HPC, generative AI, high-end laptops and workstations, and autonomous driving.

Considering all packaging platforms, 2.5D/3D interconnect is growing at the fastest rate. High-end performance packaging market is propelled by massive growth of data center AI chips, need for more computing power, bandwidth, speed, and high-end memory, and lower power consumption.

As Moore’s Law is decelerating and die cost is growing exponentially, heterogeneous integration (HI) and chiplet adoption are gaining interest to support functionality, faster time-to-market, and compensate for exponentially increasing front-end costs. 2.5D interposers and 3D stacking solutions are the key enabling packaging technologies for GenAI, GPUs, CPUs, MCUs, high-end ASICS, and accelerators.

Wafer-to-wafer and die-to-wafer hybrid bonding approaches are hot topics regarding technology breakthroughs as they allow a 10μm to 1µm fine pitch and possibly less. This enables denser 3D IC stacking of logic or memory dies, an interconnection of partitioned SoC dies, and heterogeneously integrated packages.

Advanced IC substrates are necessary to ensure the package connection to the system PCB, and they represent the silent workhorse in the generative AI hardware supply chain. The advanced IC substrate industry is focused on satisfying the increasing requirements of high-end applications, such as thermal management, form factor, power delivery, and signal routing.

Industry drivers
Gabriela Pereira, Technology & Market Analyst, Semiconductor Packaging, Yole Group, said industry giants, including TSMC, Intel, and Samsung, and top OSATs like ASE, Amkor, and JCET, are strongly investing in high-end advanced packaging capacity with a strong focus on AI-related technologies to answer the increasing industry demand.

So, what is driving advanced packaging adoption? Industry mega-trends are moving the semiconductor market and pushing for more demanding system requirements. These include 5G, AD/ADAS, AIML, AR/VR/MR, data center, mobile and wearables, vehicle electrification, HPC, cloud and edge computing, IoT/IIoT, voice processing, Blockchain, etc.

Advanced packaging market is expected to grow from $37.8 billion in 2023 to $69.5 billion by 2029, at 10.7 percent CAGR. 2.5D/3D segment accounts for $10.2 billion in 2023 to $27.6 billion in 2029, at 18 percent CAGR. Other segments are: FCBGA, FCCSP, SiP, WLCSP, FO, and ED, respectively. In fact, 2.5D/3D high-end packaging revenue is taking a growing market share of the total advanced packaging market.

Market drivers for high-end packaging include data center servers and HPC. The number of datacenter AI accelerators reached 7 billion units in 2023, and is expected to reach 17.7 billion units in 2029, growing at a 17 percent CAGR.

Requirements for AI accelerators are high computing power, memory bandwidth, high data flow, large storage capacity, and optimal power consumption. We need high-end advanced packaging for more die integration, more high-bandwidth memory, larger packages, more interconnection density, higher interconnection bandwidth, etc.

High-end performance packaging
Stefan Chitoraga, Technology & Market Analyst, Semiconductor Packaging, Yole Group, said high-end performance packaging market is expected to surpass $18.7 billion by 2029, up from $2.7 billion in 2023, at 38 percent CAGR . Telecom and infrastructure, and mobile and consumer are the biggest markets for high-end performance packaging, with 64 percent and 36 percent, respectively, of market share in 2023. The latter is expected to remain no. 1.

High-end performance packaging encompasses multiple packaging technologies. These are: 3D stack memories – CBA DRAM, HBM, 3DS and 3D NAND are the biggest contributors, representing more than 70 percent of combined market share by 2029. The top four fastest-growing platforms are 3D SoC, active Si interposer, embedded Si bridge, and 3D NAND stack.

3D stack memory is the top volume contributor for high-end performance packaging. CBA DRAM, 3D SoC, active Si interposer, embedded Si bridge, and 3D NAND stack are the top fastest-growing platforms. CBA DRAM, 3D NAND, HBM, and 3DS have the largest wafer production volume. and fastest growth rates for high-end packaging. These are 3D stacked memories. 3D SoC will start having more significant contributions in 2026.

2.5D packaging overview
Vishal Saroha, Technology & Market Analyst, Semiconductor Equipment, Yole Group, noted that 2.5D integration with through-silicon-cia (TSV) is for the high-end segment, with heterogeneous integration on Si interposer. TSV is used as an interconnection between the two Si facets in the Si interposer. Si interposer is a thinned silicon wafer with TSVs that enables heterogeneous device integration on top of it, in what is described as 2.5D integration.

2.5D Si interposer is used in many applications that require higher performance and lower power consumption due to shorter connections. 2.5D Si interposer enables heterogeneous device integration, and allows interconnection to an IC substrate.

There are various types of interposers. Si interposer is introduced in 2.5D packages to interconnect the chips and substrate. Main obstacles to more adoption of Si interposers are reticle size limitations and warpage issues limiting the yield. Significant cost is added to that. Cheaper packaging options are needed. However, Si Interposers will continue to be used in high-performance products as the interposer CTO is the same as the die’s, reducing the complexity of thermal challenges. In addition, the technology is mature and is qualified.

The advantage of an RDL interposer is that it’s cheaper than a silicon interposer. Other advantages are a thinner layer, better power, signal integrity, lower resistance, lower capacitance, and fewer parasitics. However, some players do not consider this as a kind of interposer as it is thin film RDL. Many players prefer to name this a 2.3 package, but Yole groups it as a 2.5D package.

Using Si bridge for localized interconnects between chips is a cheaper option: either an embedded Si bridge or molded Si bridge depending on the IP provider. Mold interposer is formed using mold compound to house Si bridges. It has an RDL on its sides (usually on top) to ensure interconnections with multiple dies. Through-mold vias (TMV) are an important component providing vertical interconnection and heat dissipation.

A glass interposer is another cheaper option, representing an alternative to Si interposer for RF applications. Its electrical, mechanical, and reliability performance is better than a Si interposer. Due to limitations with electrical I/Os, a move towards optical I/Os will define the industry roadmap in the future. Hence, a photonic interposer with integrated Si photonics would be needed.

3D packaging overview – hybrid bonding
3D packaging has interconnect trend. HBM 4+ memory is likely to use hybrid bonding. Collective die-to-wafer approach will be used for DRAM and logic die stacking, but D2D and D2W can be used. Hybrid bonding provides highest I/O density with minimum I/O pitch. Hybrid bonding has bump-less entry at 10μm.

Hybrid bonding has advantages like advanced 3D equipment stacking, maximum I/O, sub-10μm bonding pitch, eliminates need for bumps, expanded bandwidth, and higher memory density. Challenges include surface planarization and cleanliness, interconnect alignment, high annealing temperature, limited throughput and yield, pre- and post-bond electrical testing, and long lead time for equipment.

Chiplet and HI
Chiplet is chip design philosophy, and HI is packaging method. In disaggregation, an SoC monolithic die is first partitioned into smaller chips with different functions, and then interconnected in the same package. In duplication, two or more SoC monolithic dies are interconnected in the same package, forming a bigger SoC.

Chiplets have challenges, such as innovations in scaling, with litho, material science, etc., and scaling becoming more costly. Chiplets are addressing higher silicon yields with smaller dies, multiple product configurations are possible through combinations of fewer die designs, and number of tape-outs are less than number of product configurations. Some examples of chiplet-based products are from Intel, AMD, Apple, Amazon, Tesla, Nvidia, etc.

Si photonics/CPO
CPO or co-packaged optics are beyond pluggable optics. There are cross-sections of co-packaging approaches. CPO is adopting 2.5D/3D technologies by introducing an active interposer. This allows ASIC and optical engine to be closer to each other on the same interposer.

CPO supply chain and industry includes Broadcom, Intel, Cisco, Ranovus, Ayar Labs, Marvell, Nvidia, OpenLight, GlobalFoundries, TSMC, Tower Semiconductors, HPE, Juniper, ASE Holdings, Ragile, Ruijie Networks, etc.

TSMC and Intel are actively developing CPO for HPC and AI apps. Intel has photonic IC and electronic IC, together called optical I/O tile on xPU package with a pluggable connector approach called pluggable optics. It is developed in collaboration with Ayar Labs. TSMC unveiled in 2024, a new packaging platform leveraging Si photonics for high-performance computing and AI chips. TSMC’s HI technology for silicon photonics is called compact universal photonic engine (COUPE ), which integrates optical engine and diverse computing ASICs on the substrate or interposer leveraging the 3DFabric packaging technology from TSMC.

Rayane Mazari, Technology & Cost Analyst, Semiconductor Packaging, Yole SystemPlus, presented the latest products.

Advanced IC substrates
Bilal Hachemi, Technology & Market Analyst, Semiconductor Packaging, Yole Group, said advanced IC substrates are the foundation for AI accelerators. Advanced IC substrate represents the silent workhorse in GenAI hardware’s supply chain. A shortage in advanced IC substrate would be akin to a foundation crumbling, causing constraints on the entire supply chain.

Advanced IC substrate industry is challenging itself to satisfy the increasingly complex requirements coming from high-end applications in terms of thermal management, form factor, power delivery, and signal routing, by increasing the layer count, proposing bigger form factors, and even new core materials, such as glass.

Specifications for AI accelerators include signal routing, thermal management, power delivery, form factor, electrical properties, cost, etc. AI accelerator requirements for advanced IC substrates include larger form factor, higher layer count, and new materials for core and build-up.

For organic core substrates, they maintain cost-effectiveness and versatility across various applications, but require additional requirements such as form factor, higher layer count, improved signal routing, and good thermal management. The industry of organic substrates is expected to keep pace with the requirements for form factor and layer count, especially from ASP and yield perspectives. One approach might take the advanced substrates to the next level is about adopting glass as a new core material.

Glass core substrates can offer smaller L/S, fewer layer count, and superior thermal conductivity, making them a promising candidate to resolve thermal management issues, expected in next-gen high-performance computing, data centers, and AI products. The supply chain is currently limited and under consolidation with major challenges in terms of high yield, glass handling and processing. Glass core substrates are better long-term option for data centers.

Intel, Samsung, and TSMC are leaders in high-end performance packaging market space and key innovators in the field. With unique 2.5D and 3D technologies, they are offering products and services in the market for high-end performance applications. Eg., TSMC’S COWOS is enabling AI through high-end packaging.

High-end packaging supply chain
Vishal Saroha, Yole Group, said TSMC, Samsung, and Intel, are main players in higher-end technologies, where they strongly compete. OSATs/IDM are complementary to foundry businesses in 2.5D Si interposer packaging. In low- to mid-end advanced packaging, OSATs are the main players involved.

Intel, Samsung, and TSMC are leaders in high-end performance packaging market space and key innovators in the field. With unique 2.5D and 3D technologies, they are offering products and services in the market for high-end performance applications. Eg., TSMC’S COWOS is enabling AI through high-end packaging.