Wafer fab equipment
According to Malcolm Penn, CEO, Future Horizons, UK, the global semiconductor industry will see 21.1 percent growth and is likely to reach $499.973 billion in 2018! “Year 2018 will see a continuation of the growth with our official forecast at 21 percent,” said Penn. There will be further double digit growth, barring economic collapse. This recovery has nowhere near yet run its course.
In 2017, the global semiconductor industry grew 22 percent hitting $413 billion ($415 billion upside).
The 2018 capex drivers include node migration from 16nm/14nm To 10nm/7nm logic nodes, 3D NAND, where Samsung alone will spend a staggering $14 billion, following $26 billion total In 2017, including 3D NAND, DRAM ($7 billion) and foundry ($5 billion).
China remains a hotbed of activity in fab equipment spending, with multinational and domestic chipmakers building new fabs. EUV lithography is moving closer to production. Traditional lithography with multiple patterning will dominate front-end equipment makers demand. 200mm fab capacity will remain tight in 2018, prompting the need for 200mm equipment, but 200mm tools will be hard to find.
Entering 2018, a global financial crisis is unlikely. However, China debt and new borrowing is worryingly high. Any slowdown in China growth likely to impact elsewhere.
There is also a potential risk of 2007-09 Eurozone crisis. Big economy with slow growth/high public debt loses market confidence and/or needs bail out too big for Germany to stomach. Middle East conflicts could easily cause oil prices to soar, leading to recession in developed economies.
Further, central banks could trigger downturn. There can also be UK/EU/Global Brexit peripheral economic damage and fallout. No deal is better than a bad deal political brinkmanship. Forecast rests on assumption that major policy mishaps are avoided, and there are positive ongoing economic relationship between UK/EU. There is no significant increase/change in global economic barriers.
As for technology trends, Moore’s Law is still shrinking, and the hype’s exploding. There is still more hype than substance even in technical conferences. In logic devices, silicon area is ceasing to be the prime cost setter. Advances in design (using variance tools) and production (using metrology) mean that yields now so good that it can be worth using a larger die to remove a few process steps.
The ‘X nm’ or ‘node Y’ designations are becoming increasingly irrelevant. Many IC designs are so interconnect limited that smallest transistors are only needed in critical areas of speed or power. Intel pulled away a little due to better metallisation process. Samsung and TSMC are fast followers, but definitely need some divergence in processes again – so they are no longer clones of each other.
The exception is GlobalFoundries. As the smallest company, they need to focus on a single process. Others, including China, don’t spend enough on process R&D. Intel’s 10nm node is the first logic process to exceed the 100 million transistors per sq mm mark. There is still a 12-layer metallisation process, plus Fin and contacted gate. The industry seems to have stalled at 12-layers of metal. Is it impossible to reach layers higher than this, without actually reducing density?
Intel used cobalt for the first two layers of metallisation where all the short inter-gate connections are made. Cobalt provides a more reliable and repeatable conductivity in short interconnects where resistance of the contact dominates, not interconnect length. Another cobalt advantage is that it reduces electromigration. Instead of FEOL (front end of line), BEOL (back end of line) expertise will be the future semiconductor company key differentiator.
EUV (extreme ultraviolet lithography) is now cost effective. There will be new techniques with immersion being used at 10/12nm and beyond. Most layers will stay with 193nm immersion lithography, wherever possible.
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What’s the status of the global semiconductor industry in 2016? What are the forecasts for 2017? Malcolm Penn, chairman and CEO, Future Horizons, UK, presented his findings in London, UK, on Sept. 20, 2016.
The IC ASPs are said to be the least understood statistic. The underlying ASP trend is 4-8 year cycle (2-4 Moore’s Law nodes). The crash is steep, and recovery has been punctuated by 1-2-year disruptions.
ASP recovery from 2005 cyclical bust has been derailed by Lehmann, Euro Crisis, China, Brexit, much more. Penn recommended to beware the extrapolations and received ‘wisdom’,
especially on ASPs.
As for the current 2017 market outlook. there is an ongoing weak PC and smartphone market. The economy remains the industry’s biggest ever wildcard. Lack of industry confidence will bite everyone hard. The poor market growth is said to be the main driver for consolidation (M&A). The chip industry definitely needs a strong economy for growth.
Market forecast 2017
As for the semiconductor market forecast for 2017, the wheels fell off three times in March, Q3 and Dec. 2015. First, demand collapsed in March. This was followed by an ASP collapse and Jun-Sep hit Q3 sales value. The disastrous December made 2015 tip negative (-0.2 percent).
The wheels fell off again this time in Q1! Q3 has been holding up (despite Brexit uncertainty). The disastrous Q1 blew recovery hopes. It has been five years in a row that the market’s failed to recover. The overall economic confidence is clearly to blame.
The current 2017 market outlook is pegged at -1 percent, Lack of industry confidence will bite everyone hard. “Business as usual” means another bad year. As said earliet, the chip industry needs a strong economy for growth.
Well, Moore’s Law is still breathing, but Samsung and TSMC definitely made great efforts to catch up with Intel. Neither spends anywhere near enough on process R&D to research all of the possible next node options, thereby, relying on Intel and Imec Yield ramps are proving to be ‘challenging’, and ‘probably’ always will!
More on the Moore’s Law’, there is shrinking, that’s getting tough. E.g. TSMC FinFET transition has been step by step. Again, in 12nm FinFET, the first designs are now in tape out. However, all are still using the 20nm planar back end of line (BEOL) process. In contrast, Intel is now in early production of its full blown 12nm process and still has one generation lead.
There is a need to bring back a real International Technology Roadmap for Semiconductors (ITRS) roadmap, with classic gate channel width reduction no longer a realistic measure of IC process scaling. There needs to be separate scaling trends for the front (transistor), and BEOL (interconnect) has further muddied the waters. The industry desperately needs a new way to measure real scaling and properly compare different processes and process modes.
Now, N14/16 and N12/10 were easy, bur N7 gets hard! For N7 CMOS on production schedule for 2019, Intel and Imec have prototypes of most structure and material options. The N7 node will require III-V materials as well.
N5 CMOS node is harder still. It is the first node where quantum tunnelling effects are dominant. The prototype CMOS devices are already made by Intel and Imec. Vertical GAA (gate all around) structure is likely with FinET on SOI.
The less said, the better for the N3 node. Both heterojunction TFET and GNR (graphene nanoribbon) TFET offer complementary devices allowing continued use of CMOS design techniques. Intel definitely selected the heterojunction TFET. Either could be introduced at N5 if CMOS alternatives underperform or for very low power applications.
Beyond CMOS processes, there areSpintronics options. These include SpinFET, all spin logic, domain wall logic, Spintronic majority, nano magnet logic and Spin wave.
Looking at the “beyond CMOS” era of N2.25, N1.8 & N1.3 (maybe smaller), numerous device structures are in early research. Orbitronics may offer a simpler option than Spintronics with the BiSFET (bilayer pseudo-spin field effect transistor). A simple graphene-based device not dependent on the need for a band-gap could even come to market before Spintronics logic devices.
As for 3D Flash process challenge, Samsung’s ‘getting there’ Plus Intel’s the ‘dark horse’.
In FD-SOI, is the third process lucky? The original 28nm process was developed by STMicroelectronics and second-sourced to first GlobalFoundries, and then Samsung. The second generation shrink development has been aborted by STM. The second generation 22nm FDX process was launched by GlobalFoundries Dresden, and is an improved 28nm ‘squeeze’.
The third generation 12nm FDX process was launched (10nm FinFET performance and lower power/cost of 16nm FinFET). However, the first customer tape outs won’t be until H1-2019. Little is currently known how the process works and is made. There is unlikely to be a pure FD-SOI process/transistor as the classic FD-SOI transistor would not scale this far.
Let us also have an update on 450mm fabs. Europe’s now turned off all 450mm ‘life support’. Intel’s still “interested”, but remains low key for now. The 300mm process technology has moved on dramatically. 3D Flash needs might still ‘make 450’s day”.
As for an update on EUV, the 12 latest generation machines are now installed (plus six older ones). And, 24 more are due to be installed next year. New techniques with immersion are being used at 10nm. For 7nm, there will probably be used for Fin Cut stage. Most layers will stay with 193 immersion, wherever possible. Read the rest of this entry »
It has been a long and splendid journey. I wish that my parents — Bina and Pramode Ranjan Chakraborty — were still alive! This is dedicated to both of you.
Special mention needs to be made of my wife, Shima Chakraborty, who has been my constant companion and source of strength, since my mother passed away.
What memories I have! Nani Narayanan of Motorola lent me his mobile phone so I could make my first call to my wife, Shima, in 1995, at a trade show. Of course, I was well into Apple, Telstra, Cisco, and some other global companies at the time.
Association of Radio Industries and Businesses (ARIB) was there, from Japan, to promote the use of PHS (personal handyphone system) in India in 1995. The Israel delegation was there in India, again in 1995, to sell security products. Anil Prakash and his PTC India chapter, visit to AT&T and Advantech with Pravin Rikhy.
I first heard of TSMC and other semiconductor majors in 1996, when I arrived in Hong Kong. I became friends with Intel, Texas Instruments, STMicroelectronics, and later, Mentor Graphics, Cadence and Synopsys. In Oct. 2006, at Global Sources, I selected the New Products Gallery at the China Sourcing Fair. My visit to Ericsson’s fab in Kista, Sweden, in 2000, Infineon’s fab in Dresden, Germany, 2002, Intel’s in 2008, Samsung in 2014! I happened to break the news of TD-SCDMA in 2000, and later, visited Siemens in 2002 to have a first look at the handset. Well, there are so many memories to share. I can go on! 🙂
I have to thank all of my classmates and members of my BHS cricket team, my guru, Keshtoda (Shankar Ghosh), Dabbu (Pushpendra), Raju (Rajkumar), Lippi (Rajiv) and recently, Kitty, Len, Raj, Geri, Geetanjali, Usha, Varsha, Sanjana, and so many others. At Global Sources, I have Claudius Chan, Daniel Tam, and so many others to thank.
A special thanks to Rob Gunayan and everyone at EEWeb!
I am ever grateful to Dr. Robert N. Castellano, president of The Information Network., USA, for sharing his article titled “Korea’s Capex Holds The Key To Strong Semiconductor Equipment Sales, But Brexit May Weigh On Business,” which is featured on Seeking Alpha.
- A joint study conducted by Applied Materials and Gartner points to semiconductor equipment sales in Korea of $10 billion per year.
- Although US semiconductor equipment companies stand to benefit, numerous Korean equipment companies compete in several sectors with US companies.
- Revenue and growth could be negatively impacted by the strong US dollar and a possible global slowdown from Brexit.
Wafer fabrication equipment (WFE), he says, presents a lucrative market for Korea. In the short term, the strong dollar, as a result of Brexit, will impact sales of WFE equipment to the European semiconductor manufacturers. Traditionally, Europe represents about 5 percent of WFE sales. Hence, Korea could represent an even a greater percentage of WFE sales in 2016.
On the other hand, the turmoil in global financial markets, as a result of Brexit, could have an overall dampening effect on the Korean economy so that revenues generated from Korean semiconductor companies could be impacted. This will result in lower WFE sales as the NAND and smartphone markets slow, particularly in Europe.
He concludes that the US Dollar and Japanese Yen, could strengthen throughout 2016 and impact revenue growth for US and Japanese equipment companies selling in Korea.
It would be interesting to see how H2-2016 pans out!