CHIPS R&D semiconductor supply chain trust gets essential!
CHIPS R&D Semiconductor Supply Chain Trust & Assurance Data Standards Workshop started today in Rockville, Maryland, USA.
As semiconductor products are manufactured, key transactions are captured as data in different digital twin ecosystem modules (e.g., raw materials acquisition, design, layout, tape-out, mask making, chip fabrication, testing, packaging, and assembly). Digital twin modules must be linked together to allow backward traceability across these ecosystems, and to enable access to accumulated supply chain data for traceability, authentication, and provenance tracking.
Yaw Obeng, CHIPS R&D, welcomed the audience. He also introduced the Workshop Planning Committee.
Addressing supply chain issues
Carl McCants, Special Assistant to DARPA Director, presented the opening keynote on DARPA’s history in the semiconductor supply chain trust and assurance standards. It has been focused on addressing supply chain issues. We had a grand challenge in 2005, where we wanted autonomous cars. We had failed back then.
DARPA has been creating breakthrough, paradigm-shifting solutions. We are accepting and managing risks as well. Concern with globalized microelectronics ecosystem has also been addressed within DoD since 2000. DARPA TRUST and IRIS programs developed the techniques for validating design and process integration before distribution.
He also talked about EDA and testing, and whether the tools were doing what they were expected to do. For IRIS, we focused on what’s happening to the manufacturing process. DARPA SHIELD will develop the facility to provide 100 percent assurance against certain known threat modes quickly, and at any step of the supply chain.
Semiconductor manufacturing supply chain needs to address trust and assurance challenges. We need to maintain the confidentiality of the technology delivered, protect the IP, and have continuous and sustained access to technology needed. We have challenges such as data and definitions, so that a semiconductor product can be delivered without compromise to the product’s integrity, trustworthiness, and authenticity.
For IP protection, we need to incorporate, verify, and validate an IP into design. We need to protect the logic design and simulation of the chip. We also need to be able to transmit and store the functional test programs to the wafer fab facility, and the assembly, packaging, and testing facility. We also have to do aggregation of package-level test data in the APT facility, and take that to the customer.
Model and simulate semiconductor supply chain
Eric Forsythe, Technical Director, CHIPS R&D, introduced the CHIPS Manufacturing USA. The grand challenge is to seamlessly model and simulate the entire semiconductor supply chain. We need to create an effective collaboration environment for applied industry research to bridge the gap from discovery to production.
CHIPS Manufacturing USA Institute is meeting the digital twin institute objectives. These are: reduce time and cost for chip development and manufacturing, accelerate adoption of semiconductor manufacturing initiatives, etc.
Data — reliable, secure and accessible, workforce development, and model development and validation, were the top three areas to look at. These are the big challenges for developing digital twin technologies for semiconductor manufacturing.
Electronics supply chain digital security standardization
There was a panel discussion on landscape, scope, and focus of electronics supply chain digital security standardization efforts. The participants were Gretchen Greene, NIST, Chris Ritter, Idaho National Lab, and Christophe Bégué, PDF Solutions.
Gretchen Greene, Group Leader, Data Science Group, NIST, said we are currently building trusted chip environments (TCE). We are modernizing the ecosystem and leveraging digital technology. Security and interoperability remain the main issues.
In the CHIPS supply value chain, there are design, fabrication, package, assembly, and test, and commercial sectors. These are addressed by players in muti-physics and modelling, IP, Open Source, manufacturing process and tooling, materials and resources, photonics, microelectronics, etc.
Granularity of the semiconductor supply chain is at the heart of the standards challenge. The interoperability at scale supporting coarse grain digital assets has been inconsistent, and even non-existent. We have the opportunity to impact the industry. We are opening several windows of commercial opportunity for marketplace innovation.
We are also standardizing protocols, such as information sharing, smart connections, etc. We are making protocol specs, payload types, synchronization or process flows, status, managing authorities, verification/validation and resolver services, and registry/curation for monitoring, nodes/hubs, etc.
We are also developing a knowledge network via CHIPS exchange. Semiconductor knowledge can be shared across digital assets, such as taxonomy, machine, actionable, analytics, visualization, etc.
We have goals such as federate across supply chain through use of digital architecture connecting generations, standards, TREs and stakeholders. Strengthen exchange, reuse, and interoperability. Enable discovery and access, etc.
Digital engineering mission
Chris Ritter, Idaho National Lab, said that we have the digital engineering mission. Digital engineering transforms the way we design and operate energy assets. Digital engineering is an innovator and key success driver across all initiatives. It is a key enabler for net-zero program.
With DE, we can design — it links facility information. Operations enable the digital twin. He talked about Deep Lynx, its virtual, and physical platforms. Deep Lynx open source model is a centralized digital twin data warehouse and live event system. Ontological and time series storage of digital twin data streams is there. Event system can push and pull data in real-time around a digital twin. It is proven in operation of MAGNET digital twin.
Idaho National Lab has open ontology for thread and twins. General entity model (GEM) is an extensible, upper-level ontology. It has an advanced manufacturing app. It has digital twin demonstrations across lifecycle stages.
Supply chain traceability
Christophe Bégué, PDF Solutions, said the semiconductor market is currently looking at reliability, RMA or failures in the field, security, and regulation.
Supply chain traceability can provide fast and precise analysis of a reliability or security issue. We can enable short- and long-term containment plans to reduce cost and preserve brand. We can have assurance and preferred supply through provenance and traceability.
We need standards for single device traceability. We have SEMI E142 standard that defines a data model for devices within a wafer or complex assembly. Devices have a virtual identifier (VID) based on this model. E142 forms basis for single device tracking.
We need standards for supply chain traceability. SEMI is developing Specification for Supply Chain Traceability using Distributed Ledger Technology standard proposal to record chain of custody and provenance. We also have SEMI Supply Chain Traceability using distributed ledger technology or DLT. Standard currently defines the data and transaction model, asset lifecycle, and services.
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