Collaboration critical for success of advanced packaging, APPF: NAPMP, CHIPS for America

Posted on November 27, 2023 Updated on November 29, 2023

CHIPS National Advanced Packaging Manufacturing Program (NAPMP) organized a conference today.

Approximately $3 billion in funding for the National Advanced Packaging Manufacturing Program (NAPMP) will be used to drive US leadership in advanced packaging. An initial funding opportunity for this program is expected to be announced in early 2024. Supporting innovation and keeping the US at the forefront of new research is a critical part of the president’s Investing in America agenda.

Gina Raimondo, Secretary of Commerce, stated: “Making substantial investments in domestic packaging capabilities and R&D is critical to creating a thriving semiconductor ecosystem in America. We need to make sure new leading-edge chip architectures can be invented in our research labs, designed for every end-use application, manufactured at scale and packaged with the most advanced technologies. This new vision for advanced packaging will enable us to implement President Biden’s Investing in America agenda and make our country a leader in leading-edge semiconductor manufacturing.”

Laurie E. Locascio, NIST Director, added: “Within a decade, we envision that America will both manufacture and package the world’s most sophisticated chips. This means both on-shoring a high-volume advanced packaging industry that is self-sustaining, profitable and environmentally sound, and conducting the research to accelerate new packaging approaches to market.”

Current challenges
Subramanian Iyer, director of NAPMP, Chips.gov, USA, discussed the current challenges in advanced packaging, and the NAPMP’s vision for investments in R&D. There are several opportunities in advanced packaging. Even though transistors have scaled dramatically, die sizes have grown larger. Monolithic dies still outperform multi-chip packaged assemblies.

Packaging is now evolving. It is evolving to emphasize system integration, rather than single-chip packaging with the increasing adoption of silicon processing techniques. Heterogeneous integration (HI) is also evolving, and is not new. The difference now is in the scale. There are simple I/Os, and more useful chip areas. We can end up with lower power, lower latency, and higher bandwidths.

Advanced packaging is now having more bump and pillar pitches. There is finer trace pitch, shorter inter-die distance, etc. We are also increasing the amount of silicon.

Advanced packaging blurs the line between monolithic chip and packaged assembly of heterogeneous chips. Scaling out the package involves accommodating larger number of closely packed heterogeneous dies. We can address power delivery, thermal dissipation, etc. Advanced packaging allows us to change how we put complex systems together. Bare dielets are stacked (3D) or integratedside by side at fine pitch on aninterconnect fabric (substrate). Dielets are heterogeneous, and a simpler and flatter hierarchy is possible.

Chiplets are IP designs, and need to be connected to complementary chiplets to function. Dielets are hardware instantiated chiplets. Bare dielets are stacked or integrated. Today, packages are incredibly complex and costly. We need to simplify packaging, and make it cost-effective to manufacture in the USA.

Critcal resource for advanced packaging
George Orji, Project leader, Microsystems and Nanotechnology Division, NIST, said that the NAPMP implementation planning should serve as critical resource to developed advanced packaging and related R&D. It is now a matter of national security.

NAPMP must be competent inheterogeneous integration, chiplets, photonics, and codesign. NAPMP should have easily accessible and flexible user facilities or hubs that focus on low-volume, cost-effective prototyping, including material characterization, metrology, modeling and simulation, and standards. It is also important to build a skilled workforce to support this industry. Within a decade, NAPMP-funded activities, coupled with CHIPS manufacturing incentives, will establish a vibrant, self-sustaining, profitable, high-volume, domestic, advanced packaging industry where advanced-node chips manufactured in the US, are packaged in the US. We expect the technology developed to be leveraged in new applications and market sectors and at scale.

The CHIPS IAC has also recommended to create programs. Within a decade, NAPMP-funded activities, coupled with CHIPS manufacturing incentives, will establish a vibrant advanced packaging industry in the USA. The Secretary of Commerce shall establish the NAPMP program, in coordination with the national semiconductor technology center established under subsection (c), to strengthen the semiconductor advanced test, assembly, and packaging capability in the domestic ecosystem, and which shall coordinate with a Manufacturing USA institute established under subsection (f), if applicable. The Director may make financial assistance awards, including construction awards, in support of the National Advanced Packaging Manufacturing Program.

Subramanian Iyer stated that we now need to establish advanced packaging in the USA. There are packaging roadmaps, such as Manufacturing Roadmap for Heterogeneous Integration and Electronics Packaging (MRHIEP), Materials and Electrical Test Technology Roadmap (MAESTRO) from International Electronics Manufacturing Initiative (iNEMI), Microelectronic and Advanced Packaging Technology (MAPT), and other roadmaps such as Heterogeneous Integration Roadmap (HIR) and International Roadmap for Devices and Systems (IRDS). All aspects of technologies are required to develop leading-edge on-shore advanced packaging manufacturing capability.

Priority areas
First, there should be an Advanced Packaging Piloting Facility (APPF). It is the key to facilitating high-volume manufacturing, piloting, and prototyping functions. Another important area includes chiplets and design ecosystem, and design and build in the USA, and later, sold worldwide.

The NAPMP priority research investment areas include substrates and materials as the platform for heterogeneous integration of dielets. Equipment, processes, and tools are also needed. There must be thermal management and efficient power delivery, more photonics and connectors, and also the chiplet ecosystem crucial for advanced packaging. APPF will provide the test bed for the integration of different investment areas, and functions as piloting and prototyping facility.

Materials and substrates are the platform on which advanced packaging is built. These substrates or interconnect fabrics (IF) may be based on silicon, glass, or organic materials and can include fan-out wafer-level processes. They must be compatible with advanced and legacy nodes, and different semiconductor material systems.

For equipment, tools, and processes, we need advances in these areas, where substrates are patterned and chipletsare reliably assembled on these substrates. This is to achieve goals in reducing patterned feature sizes on large areas, including through substrate vias, as well as strategies to reliably assemble chipletsonto these finer substrates and passivate them. We expect CMOS equipment and processes will be adapted to handle dies, wafers, and panels. We also expect the APPF to benefit from developments in equipment, tools, and processes.

For power delivery and thermal management, we need new thermal materials and novel circuit topologies to employ advanced substrates and HI. Advanced packaging makes severe demands on power density and can restrict heat spreading. HI will require multiple voltage domains and high granularity. Power delivery will likely require wide bandgap materials integrated into the substrate. Modelling and optimization to achieve high efficiency is a must.

In photonics and connectors, the focus will be on reliable and manufacturable integrated connectors that include computational capability, data pre-processing, security, and ease of installation to the packaged assembly. Packaged assemblies should interact with other assemblies and the outside world. Connectors can also be wired, RF, and optical.

As for the chiplet ecosystem, chiplet discovery methodologies will be developed to ensure a high level of reusability, design, and warehousing of these chiplets. They need to be small and work better when connection pitches and distances are small. We need to develop chiplet dicing and ESD-free transport. Chiplet ecosystem also requires standards and warehousing infrastructure where bare dies are stocked. NAPMP will focus on chiplet discovery methodologies, high-value chiplet designs, and integration methodologies. We will also need common protocols, and protocol translator chiplets.

Finally, there is co-design. Holistic package co-design “will be adapted for advanced packaging with consideration for built-in test and repair, security, interoperability, and reliability, with a detailed understanding of the substrate and processes used for assembly.” Co-design platform should comprehend chiplet architecture and communication options. We need to design for test, repair, security, and reliability. There can be thermal and thermo-mechanical constraints. We also need substrate and assembly technology. We need the extension of chip design methodologies to advanced packaging. NAPMP will support the co-design efforts.

We are also looking at packaging workforce development. It requires multi-disciplinary teams. NAPMP intends to fund projects that incorporate strong workforce development plans. It should be part of other educational advancement activities within each investment area, and APPF.

Collaboration critical!
APPF is the point where everything comes together! The APPF is where successful development efforts will be transitioned and validated for scaled transition to US manufacturing. It is a key facility for technology transfer to high-volume manufacturing.

APPF could include integrated process flows that can reach commercial scale, validating new technology specifications, compatibility with other processes, yield, and reliability, and assessing technologies for scaled transition to US manufacturing. The APPF may consider prototyping innovative design ideas from the community.

Collaboration is now critical for success! We will need the EDA vendors, materials and substrate suppliers, equipment and tool vendors, chiplet designers, chiplet fabricators, system houses and end users, OSATs and IDMs, thermal and connector solutions, educational institutions, etc., to come together.

Iyer noted that the NAPMP expects to release the first funding opportunity in early 2024. Materials and substrates will be the topic of the first funding opportunity. Advanced packaging is all about scale down and scale out. We need minimal hierarchy and reusable chiplets, and innovative architectures and products. We also need small NREs and short times to market. It offers a different way of building complex chips and systems which leverages our strengths in design and system architecture.

Our focus is on R&D that leads to products designed and manufactured in the US, with US software and equipment. We need to build US manufacturing and R&D workforce, and provide a self-sustaining innovation pipeline that fuels US packaging leadership.

The approximately $3 billion NAPMP program will be dedicated to activities that include an advanced packaging piloting facility for validating and transitioning new technologies to the US manufacturers, workforce training programs to ensure that new processes and tools are capably staffed, and funding for projects focusing on: materials and substrates, power delivery and thermal management, equipment, tools and processes, photonics and connectors, chiplet ecosystem, and co-design for test, repair, security, interoperability and reliability. Lora Weiss, Director of CHIPS R&D Office, added that we will leap ahead and do more advanced packaging in the future.