CHIPS R&D Standardization Readiness Level workshop conducted

CHIPS R&D Standardization Readiness Level workshop was held recently in Boulder, Colorado, USA.

On the opening day, Jason Kahn, CHIPS R&D, welcomed the audience. The CHIPS R&D roadmap is for a semiconductor and microelectronics ecosystem that is smarter, faster, and more inclusive and agile in enabling innovation. The impacts should be economic and national security, and future innovation.

From the standards summit, we identified priorities, such as chiplets, metrology and testing, digital twins, etc. We are promoting a diverse, standards-capable workforce, and linking standards and research. There will be collaboration between industry and academia, along with certification and credentialing programs. We need multi-disciplinary and inter-disciplinary education and training.

We are now identifying standards priorities. Standardization readiness level (StRL) is a metric that informs the maturity and suitability of a technology or process for integration into formal standards. Framework elements or dimensions of the StRL include market, technology, and community. They combine to inform an overall standardization strategy. Concept for scale include readiness to standardize, development of standard, and readiness of standard. We need to create a standardization readiness level scale that provides common language for tracking a standard — from concept to adoption.

Marla Dowell, CHIPS R&D Metrology Program Director, presented the CHIPS for America R&D program. Workforce is an over-arching goal of the CHIPS for America program. Workforce initiatives include CHIPS Metrology program, Natcast, NAPMP, and CHIPS Manufacturing USA program.

CHIPS Metrology program has goals to expand measurement solutions for semiconductor ecosystem. Increase the number of solvers harnessing diversity of people, inside and outside of NIST, etc. There are seven grand challenges for metrology.

NSTC is operated by Natcast. NSTC focus areas include workforce development, lower design costs, and advancing research. NAPMP, and CHIPS manufacturing incentives, will establish a vibrant, self-sustaining advance packaging industry in the USA. We have packaging roadmaps, technology investment areas, APPF, chiplet and design ecosystem, and design and build in the USA.

CHIPS Manufacturing USA program will enable the world’s first shared semiconductor DT. It will reduce time for chip development and manufacturing. It will accelerate the adoption of semiconductor manufacturing initiatives.

Barbara Goldstein, Associate Director, Physical Measurement Laboratory, NIST, presented a keynote on how the standards fuel technology innovation and overview of StRL framework. Standards take time to grow, starting from invention. Industrial revolutions do require standards. We need to step into lifecycle stages, such as inventing, de-risking, product development, rethinking/recycling, etc.

We need tools in the toolbox to de-politicize the process, and help ensure that standards are science-based, and industry-driven. Assessing readiness is a complicated process. We need to develop a standardization strategy. We also require a scale for guidance and communicate readiness.

Clare M. Allocca, Associate Director, NIST, presented a keynote on standardization readiness and its application. Standardization should provide considerations for all requirements to develop a standard. It structures framework for evaluation. ISO/IEC has developed a global criteria for standards.

StRL has three elements — technology, market, and community, and capacity. Capacity involves commitment, players, and balance. There also needs to be some windows of opportunity. We need to look at what impact would the development of standard (or other deliverables) have on future of technology development. We need to look at sufficient business cases. Finally, we also look at the capacity, and experts, who can develop the standard further.

Possible responses may include system performance, device design, performance characterization and benchmarking, architecture, systems, components, or interfaces, etc. How extensive are the requirements? How mature and stable is the technology? What level of user assurance is needed?

There was a panel discussion around technology considerations for informing a standardization strategy. The participants were: James Moyne, University of Michigan, Matt Fuller, Entegris, and Albert Fuchigami, PEER Group. Alan Weber, Cimetrix by PDF Solutions, was the moderator.