Strategy for wafer probe in a chiplet world

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Ms. Amy Leong, SVP, CMO, GM Emerging Growth/M&A, FormFactor Inc., presented on strategy for wafer probe in a chiplet world at the SEMI Northwest Chapter, USA conference on ‘The Future of More Than Moore’.

Wafer probe/test/sort is increasing in importance. Increase is driven by multiple compounding factors. It includes shifting test content from final test to wafer test, die-disaggregation composite yield math is sobering, and it is driving up both test coverage and capability at probe. Historically, packaging at interconnect structures have also served as probe interfaces. It works well at flip-chip pitches, but below that, significant technical and cost challenges emerge.

Ms. Amy Leong.

Customers spend dollars on wafer test to avoid wasted cost of packaging a bad die. Test cost should be lot less than bad-die packaging cost. They can inform an adjustment/trim/change. It serves as an outgoing QC for product title transfer. Wafer test/probe is a key enabler for advanced packaging. Chain of chiplets is no longer its weakest point. Economically viable multi-chiplet products require near-KGD component chiplets. Matching of the component chiplet performance bins is more subtle, but an important factor.

Chiplet-to-chiplet interconnect scaling poses challenges for probe. Current carrying capacity (CCC) is the current a probe can carry before failure. Historically, wafer probe has used packaging interconnects to connect to the die. For a given probe design, geometric scaling results in reduced performance. There is potential advantage in decoupling packaging interconnect from probing contacts/interfaces.

We are optimizing the use of packaging interconnects using the hybrid probe card. Layout of power and ground interconnects are often at larger pitches than high-density fine-pitch I/Os. Higher MTBF from less probe damage/repair is a benefit. HBM tells you not to probe micro-bumps if you don’t have to! HBM DRAM die are sparsely populated with micro-bumps. For high-volume HBM manufacturing, it has become standard probe methodology. More high-speed probe cards are required, as one HBM stack is 8+ DRAM die and one SoC die.

Advanced packaging can pick up the slack from slowing front-end-driven Moore’s Law. Probe is becoming more valuable to the industry.

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