Innovative technologies for sustainable future of semiconductor industry: IRPS 2024
IEEE International Reliability Physics Symposium (IRPS) 2024 was held in Dallas, Texas, USA. Su Jin Ahn, EVP, Advanced Technology Development Office, Samsung Semiconductor R&D Center, presented the plenary on innovative technologies for sustainable future of semiconductor industry.
Semiconductor market growth will be from $224 billion to $350 billion for computing and data storage. Automotive electronics has moved to $150 billion. We are seeing an explosive growth of data and rapid development of AI. Data creation is accelerated by GenAI. We had AlphaGo, developed by London-based DeepMind Technologies, an acquired subsidiary of Google, in 2015.
Today, we are witnessing growth of wafers and semiconductor fabs. Number of fabs using 300mm wafers has increased x3 over last 15 years. There is paradigm shift in computing over the past 80 years. From mainframe era, we have now come hyper-scale connectivity and AI. Moore’s Law-based geometry scaling has been at the heart of all these developments. We have seen evolution of photo-lithograph, multi-patterning, etc. There has been structure and materials innovations as well. There is changing landscape of memory and logic devices in IRPS papers. Reliability issues need to be overcome for new structures and materials.
We are seeing evolution of backend-of-line metals. We have relied on low resistivity and high reliability for performance, speed, and power efficiency of chips. There is evolution of NAND flash memory. It is now entering 3D stack up and WF bonding. Stacking has moved to heterogenous integration. There are mutual thermal, chemical, and stress effects. There are potential reliability issues. Cell-to-cell variations from top to bottom increases due to deep contact hole. There are stress-related problems in wafer bonding.
Technologies in works
We are now in logic scaling trend. CPP scaling has slowed down due to short channel effects, and contact resistance. Cell height scaling slowed down due to rising metal resistance. We have prospects for logic transistor beyond planar TR. We moved from planar TR to FinFeT at 14nm. At 3nm, we have the gate all-around (GAA) MBCFET. At <1nm, we have 3DS FET and CFET.
We have potential reliability issues in GAA transistor. Thin body and process complexity degrade HCI. Structural complexity and increased packing density is vulnerable to heat dissipation. For self-heating, we can maintain temperature at thin nanosheet channels.
We have potential reliability issues in 3DS FET. Accumulation of process damage causes TDDB, and BTI degradation. Complex 3D layout causes Vth variation, and self-heating deteriorates. We also have potential reliability issues in 2D channels. We have to look at material quality, full integration into logic process, defect control, etc.
We have prospects for DRAM cell beyond 10nm. Area scaling continues via vertical channel transistor or vertically-stacked cell array. Potential reliability issues include an undesired hole accumulation in thin floating channel that increases the sub-threshold leakage. Beyond Si-channel, we have deposition-able IGZO channel transistor in vertical channel transistor (VCT). We also have potential reliability issues in IGZO channel. There can be thermal instability in process integration, abnormal PBTI, and ion-Vth trade-off behavior.
Future prospects
In future, we will be transitioning to 3D stack era. We will move to cell array and periphery circuit, and heterogenous integration. We are moving to wafer bonding and advanced packaging. We are seeing the evolution of package technology. We are pursuing fine pitch bonding (<2um) for interconnect density (>2e5/um2) compatible to SoC. We are moving to wafer-to-wafer and multi-chiplets.
There are potential issues in 3D-IC. These include massive bonding interfaces (multi-chiplet, multi-stage HBM) that increases EM risks. Pitch scaling and low temperature process weakens bonding interface stability.
There are several future reliability challenges. They include TDDB, EM, FBE, HCI, BTI, self-heat, etc. Thanks to new semiconductor technologies being developed, we have managed the challenges well, so far. More is expected in future.
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