On the World Telecom Day, 2017, the Broadband India Forum hosted the seminar, “Innovations, Technology & Satcom for Big Data, Broadband and Digital India”, in New Delhi.
Let’s start by looking at the primary growth drivers of communication satellites. According to TV Ramachandran, president, Broadband India Forum (BIF), as of Dec. 31, 2015, there were 1,381 total operational satellites, globally.
India has totally 124 operational satellites, which is only 9 percent of the global satellite population. India, which is the target focus of ‘The next Billion in Broadband has less than 5 percent of the total communication satellites globally (33, compared to ~700 globally). Out of 33 satellites, only 28 are dedicated communication satellites (and predominantly in the less-efficient C and Ku bands).
All this puts India far below the global norms on satellite communications. India needs large private investment to augment satellite capacity for a Digital India.
The top 10 economies use broadband from communication satellites. There are millions of subscribers in USA, Canada, West Europe, Australia, Japan, Brazil, etc. Satellite broadband is delivering 50Mbps speeds with today’s technology. Private satellite companies are set to deliver 1Gbps in near future.
(L to R): TV Ramachandran, president of BIF, Mrs. Aruna Sundarajan, Secretary, MeitY and DoT, Shyamal Ghosh, Chairman emeritus, BIF, N Sivasailam, Addl. Secretary, Telecom, Dept. of Telecom, and Anil Prakash, secretary general, BIF.
Ubiquitous satellite broadband
Satellite broadband is ubiquitous. It eliminates ROW issues which plague wired buildouts. It is available everywhere, even on planes, ships, trains and in homes and villages.
As per ITU, India ranks 131 out of 155 globally on fixed broadband penetration and at 155 out of 187 countries for mobile broadband. It has a huge urban/rural digital divide.
Rural broadband is at only 6 percent against urban broadband at 50 percent.
Terrestrial broadband technologies involve difficult rollout, prohibitive costs and long timeframes to deploy. Satellite broadband can be achieved almost on tap. The use of satellite for broadband becomes absolutely imperative.
India lagging behind in satellite broadband
All communication satellites in India belong only to ISRO. These are built on older, less efficient C and Ku-band technologies. Globally, private companies are investing in communication satellites.
Government and agencies are focusing on space exploration, new space technology, military and defence applications. Commercial communications have been opened to open markets. Built with new Ka-band technology is enabling speeds of up to 100Mbps/1 Gbps.
About $5 billion+ of investment has been committed to communication satellites
globally from Intelsat, Inmarsat, ViaSat, Hughes, SpaceX, OneWeb. India has currently no private investment in communication satellites.
Globally, satcom is competitive to terrestrial technologies for rural and remote areas. However, it lags behind in India due to inadequate capacity /availability, lack of use of new innovations and technologies, as well as higher costs. In India, costs of satellite broadband are much higher than that in the US.
Bringing costs on par with global norms
What can be done to reduce the costs and bring it on par with global norms? Satcoms can offer HTS with Ka-band, so that the cost/Gb could reduce by a factor of 7 along with multiple-fold increase in capacity. There should be relaxation of outdated technical specifications. There is a need to free up the market and allow open competition between international and domestic satellite operators.
There should be an increase in the term period of the contract between the satellite
operators and service providers from three years to at least 10-15 years to enjoy economies of scale. Future new applications and new markets would require at least 100x more capacity than current applications.
What India should do?
So, what does India needs to do? First, commercial communications through satellite needs to be maximised for Digital India and for bridging rural-digital divide. There is a need to facilitate private investment and manufacture in communication satellites. India also need s a direct investment potential of $2 billion+.
There is a need to leverage the expert institutions like DoT and TRAI for managing policies and implementation of the same , as in the case of terrestrial broadband technologies. At least $2-5 billion FDI expected by 2025 if private investment is permitted.
The current policy permits liberalization. Open Sky policy has been there since 2000. However, procedures and processes have to facilitate implementation of Open Sky policy in letter and spirit. Private participation is needed to boost India’s satellite program.
There is a need to approve long-pending proposals/applications for setting up
domestic satellites. As of now, 17 years of liberalized Satcom could have added at least 400 million rural broadband customers today, besides connecting all 250,000
GPs (of Bharat Net ) and given a significant boost to the rural economy.
Use satellites for Internet
In his welcome address, Shyamal Ghosh, IAS (Retd), Emeritus chairman of Broadband India Forum, stated that: “Use of satellite for providing Internet services is perhaps the only way to cover the entire country. Its importance of meeting the objectives of Digital India and for providing ‘Broadband to All’ by 2020 cannot be overstated.”
Ghosh pointed out that while India, through the Department of Space and ISRO has made rapid strides in the areas of manufacture and launch of indigenous satellites and launch vehicles for satellites, we have a long way to go to meet the communication requirements of our country in an affordable, always available and accessible-to-all manner. While the global satellite industry is pegged at around 600 communication satellites, India has only a handful of them – all of which belong to ISRO.
BIF warmly congratulated ISRO for yet another feather in its resplendent cap, and celebrating the launch of the GSAT-9. It is a superb testimony to ISRO’s capabilities in satellite technology.
Mentor Graphics Corp. recently announced the Veloce StratoM emulation platform.
The Veloce Strato platform is Mentor’s third generation data-center friendly emulation platform. It is said to be the only emulation platform with full scalability across both software and hardware. Mentor is also launching the Veloce StratoM high-capacity emulator and Veloce Strato OS enterprise-level operating system.
So, how is the Veloce StratoM platform suitable for data centers than previous version?
According to Montu Makadia, one of the worldwide ATM – Emulation experts at Mentor Graphics ; with the Veloce StratoM emulator, there are no major changes to the lab requirements.
There is the same footprint, lower total power consumption, and lower total cooling requirement (air-cooled, air extraction from top). There is an added flexibility on the door and panel (new in Veloce Strato) that makes system maintenance easier.
The Veloce Strato Platform plans for highest effective capacity (up to 15BG) available. Does it really go up to 15BG? If yes, where are the test results?
According to a Mentor Graphics’ spokesman, as of now, no test results are required. Connecting emulators via a sophisticated connection method is common for Veloce. In this case, the Veloce Strato Link can be used to connect multiple Veloce StratoM emulators to reach 15BG capacity.
“We have installations at companies that will not allow us to talk about them by name. These are large, multinational companies with very advanced verification and validation requirements. The installations have gone extremely well and deployment is underway and happening without issue,” the spokesman added.
Mentor is saying there will be a roadmap to 15BG over five years and beyond? What if others come up with a faster system in between?
The spokesperson said: “We can’t predict what other emulation vendors will do in the next five years. We have done our competitive research and believe that we are uniquely positioned to have, both, the largest capacity available in 2021, as well as the emulation platform with the highest RoI.”
Finally, how is the Veloce Strato OS enterprise-level operating system a step above the earlier OS?
The Veloce Strato OS is the centerpiece of the technology for the overall Veloce architecture. The Veloce operating system basically enables three things: The first is the primary core compiler flow. When you use an emulator, you need to compile the design. You synthesize and partition, and move from an RTL/netlist to something that is mapped to the hardware (P&R).
The Veloce Strato OS delivers an integrated, fully automated, single step compilation flow with about 3x faster compilation time and with a 100 percent compile success rate. The compilation time and a 100 percent compile success is one of the key differentiators compared to an FPGA-based emulator.
The OS enables all the use models of verification with a unified compilation, runtime and debug flow. That includes traditional ICE (physical targets-based stimulus), the other virtual use models (SW device models) and testbench acceleration (SW test benches, UVM, SV, SC, TLM, etc.).
The third unique attribute is advanced debug. In addition to the waveform support, it supports Livestream to view a set of important signals, key register for long emulation runs as tests are progressing and Veloce’s unique ‘save and restore’ replay to restore emulation sessions instantaneously at a specified time point for detailed debug activities without re-running the emulation from the beginning.
Here is the concluding part of my discussion with Dr. Walden C. Rhines, chairman and CEO, Mentor Graphics.
Getting billion-gate design correct
In EDA, is there now some chance of getting a billion-gate design correct on first pass?
Dr. Rhines said: “Absolutely! Today’s methodology is up to the task and customers have already reported “billion gate equivalent” designs, i.e., 4 billion transistor, correct on first pass. Correct logic is a much easier challenge than full production readiness on first pass!
“Achieving targeted power dissipation and timing has been more of a challenge but that’s where recent tool improvements are having their greatest impact. Almost all designs of this size now go through exhaustive verification, including power analysis, using emulation. That change in methodology has increased the cycles of verification by more than three orders of magnitude.
“Beyond simply achieving functional silicon with acceptable power and timing, more and more companies are now using EDA tools to assure a rapid ramp to high yield in production. This requires use of a whole new generation of “design for test” tools directed at defect driven yield analysis.
“By our measures, some of the top semiconductor companies analyze more than 500,000 defective parts every day to identify design and process problems.”
Standardization of SoC verification flow
Next, what is the status of the standardization of SoC verification flow today?
He said that Mentor Graphics has long worked on providing leading functional verification products. “We are doubling down on perfecting tools that are part of an enterprise platform where common testbench stimulus, verification IP, and standard verification languages can be used up and down the tool chain. However, the flow belongs to the customer.
“We do not try to enforce a “standard verification flow”. We are happy to accommodate unique customer needs and trust our customer to know the unique requirements of their own markets.
It would be interesting to know what has been happening regarding the coverage and power across all aspects of verification?
According to Dr. Rhines, power management debug has permeated all aspects of traditional HDL based verification. For large SoCs, debugging power-management related problems is a very difficult task. Power is managed wholly or in part by software. Increasingly, validation of power managed designs, including power estimation, requires hardware accelerated solutions such as emulation and prototypes.
New releases of the UPF standard include lots of new capabilities that help verify power usage but that do require additional effort to analyze. Examples include dynamic power related messages, automatic power specific assertion generation and support for the entire flow from simulation through emulation and prototypes.
In addition, lots of designs now use new tools for power management verification, static analysis, rule based power checks and power-aware logic equivalence checking.
Similarly, what is happening in active power management today?
He said that active power management creates the need for functional verification. Traditionally, power has been managed via clock gating, power gating and dynamic voltage and frequency scaling.
The first two methods (clock and power gating) directly impact functionality necessitating the need for things like isolation with clamp values on inputs or outputs to a power gated block of logic, retention registers and gating logic for clocks, as well as the associated control signals or registers and the state machines, which manage the transitions from one state to another.
Verification of the active power management logic and control states necessitates the need for UPF support in verification solutions. The challenge in debugging power management issues drives the value in dynamic checks to ensure valid power down and up sequences, save/restore or resetting/write-before-read behavior of registers in power domains and proper activation and de-activation of isolation logic values.
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It has always been a great pleasure chatting up with Dr. Walden (Wally) C. Rhines, chairman and CEO of Mentor Graphics. It has been a while since we discussed the global semiconductor industry in such detail, and therefore, the latest experience is even more memorable.
First, I asked Dr. Wally Rhines how is Mentor predicting the global semicon industry to perform in 2017?
He said that the growth of the semiconductor market has averaged anywhere between 3-5 percent throughout the 2000’s. In most recent years, since 2008/2009, IC units have grown consistently at a rate of 6-8 percent,, indicating continued demand for semiconductor technology.
ASPs have been drifting downward for a long time with only a handful of exceptions since 1995. The trend appears to be moderating in the last decade, but the downward pressure in pricing has pushed the overall revenue to 3-5 percent growth rate mentioned earlier.
For 2017, most industry research firms and analysts are expecting a relatively positive year (the average forecast across 10 semiconductor research firms is currently at 5.5 percent). Mentor Graphics expects that number to be very conservative due to changing dynamics in the semiconductor industry and how the market is actually measured.
Dr. Rhines said: “Within the last decade there has been an emergence of systems companies designing chips for internal consumption. Those chips are typically not measured at all, or are only partially measured if they are produced by a foundry company. We see the trend in several important areas like smartphone manufacturers.
“Apple and Samsung have been manufacturing their own application processors for some time. However, there is an ever increasing list of other market leaders following with their own designs.
“We are also seeing a number of companies involved with cloud services or other data center intensive companies designing chips for their internal consumption. Unless something unexpected occurs, 2017 should be a good year for the semiconductor industry with growth above average.”
Next, how has been the growth in EDA for 2016? How will the performance be in 2017? Where does Mentor come in all of this?
According to Dr. Rhines, EDA had a strong year in 2016 with total growth of about 9 percent overall, including SIP. Tools alone had growth of about 7.5 percent. Demand for tools continues to look strong for the industry as there remains a strong focus on the leading-edge driving the need for advanced design technology.
Moore’s law continues to drive the industry into smaller nodes as companies are preparing for 10nm, 7nm and 5nm nodes. Advanced nodes continue to drive EDA tool adoption in manufacturing and design.
Additionally, increased challenges and methodologies in functional verification drive technology adoption in enterprise verification including areas like emulation, which had a resurgence in 2016 after several flat years.
Dr. Rhines elaborated: “We are seeing increased activity in areas like ESL as well with ESL Synthesis having its best year ever. PCB design is also enjoying a resurgence in growth as designs become more complex and new design methodologies like System of Systems design begin to emerge.
“In 2016, Mentor Graphics reported an all-time record of $1.285 billion, an 8.6 percent growth or a full point higher than industry tool growth of 7.5 percent. The proposed merger with Siemens should bring additional resources to Mentor’s R&D and customer support capability so our fourth quarter results suggest that customers are pleased with the outlook.”
Part II of this interview appears in April where I will be discussing standardization of SoC verification flow, billion-gate design, power management, etc.
Thanks are due to Raghu Panicker, country sales director, and Veeresh Shetty, marketing manager – Europe and India, Mentor Graphics.
Gionee has launched its first flagship mobile phone of the year, the A1, in India.
The new model offers longer battery life, 4010 mAh battery, with ultrafast charging capability, and enhanced picture quality to capture great selfies. It has a stunning 16MP front camera, which offers clearer and more beautiful selfies. The A1 is loaded with a faster and safer fingerprint unlock, and Android 7.0 Nougat with Amigo 4.0, amongst a host other innovative features.
Gionee also unveiled #Selfiestan, a world of selfies that celebrates inclusiveness of varied expressions of today’s Hindustani. The unique campaign, #Selfiestan, is targeted at the growing breed of selfie enthusiasts in India. Selfies have undergone a socio cultural shift in the country to be the most powerful tool of inclusive expression.
Arvind R Vohra, country CEO and MD, Gionee India, said: “Today’s generation views the world from their front camera. They live for creating and celebrating experiences out of moments. At Gionee, we want to celebrate this inclusiveness by dissolving boundaries and creating a world of equals where every moment is worth capturing. Through #Selfiestan, Gionee plans to give India a sense of ownership and belonging by creating a world of Hindustan ki selfies. With the new A1, we take our first step towards building #Selfiestan.”
I am really intrigued by this headline! First, SEMI, and now, The Information Network, are making the forecast for China!! However, what has been India doing? Nothing!!
Massive investments in Mainland China are finally showing benefits as the ratio of ICs made in China versus those imported into China increased from 27 percent in 2015 to 29.1 percent in 2016, according to the annual update of The Information Network report entitled “Mainland China’s Semiconductor and Equipment Markets: A Complete Analysis of the Technical, Economic, and Political Issues.” Driving the growth of ICs made in China are a large number of fabs that are in construction and planning production over the next few years, said Robert Castellano, president, The Information Network.
Next, most of the advanced semiconductor packaging is done in China. There are over 150 foreign and domestic packaging companies based in China. Tied to the packaging industry is the need for back-end semiconductor equipment. With its robust IC program, China represents a strong growth area for advanced packages, used to house and protect the ICs. These advanced packages include 3D, TSV (through silicon vias), FOWLP (fan-out wafer level packaging) and flip chip.
According to The Information Network:
* Investments by the Chinese government and foreign semiconductor manufacturers have started having an impact on meeting China’s internal IC semiconductor needs.
* A surge in semiconductor growth in China merely means these same number of chips won’t be made elsewhere — a buying opportunity for semiconductor manufacturer stocks.
* Large equipment companies will benefit from new fabs built but will face increased pricing pressure from new semi manufacturers because their traditional customer base has changed.
* Smaller semiconductor equipment suppliers will benefit from a new customer base that had been traditionally buying from the same vendor.
* Rudolph Technology is an example that benefited last year, positioning itself with its product line and strategic focus on building a sales infrastructure in China.
According to SEMI, USA, China is projected to be the top spending region for fab equipment in 2019 and 2020. Of the 20 more fab projects, SEMI is tracking up to 16 potential 300mm fabs to be constructed or beginning to ramp up throughout the forecast, with the investment targeted for the memory and foundry sectors.
Is India even listening?
India continues to remain cautiously optimistic on business performance as far as the business outlook is concerned. The graying of salary increases in India is a reflection on how India Inc. is coming of age. The macro question remains: if this represents a blip or a trend! These are among the findings of the 21st Annual India Salary Increase Survey by AON Hewitt.
The survey projects a drop in pay increases to an average of 9.5 percent across industries. While the inequity of pay remains a concern, the key reasons cited by the various employees across 1,000+ firms for voluntary attrition are role stagnation and limited growth opportunities.
For almost a decade, manufacturing firms in India are budgeting higher salary Increases than services firms. A lower base and higher expectations has driven this behavior. Although, with increasing pressures on margins and improved salary base, the difference in the budgets has been gradually declining since 2013. Along with high performance – high potential and hot skills remuneration are now gaining acceptance.
The gradual slowing of pay increases and higher emphasis on productivity and performance indicates the ‘graying’ of salary budgets for India. Some industries are impacted more than others – and AON Hewitt sees faster moderation of pay increases in industries such as technology, telecom, consumer etc.
Inspite of lower salary increase budgets, top performers will continue to get lucrative hikes as companies focus on performance and criticality. While attrition was contained at a broader level, key talent attrition takes a hit. Differentiated people and pay practices slowly taking the edge away from compensation for Key Talent Management.
Projections for 2017 include salary increase projections across consumer Internet companies, life sciences, professional services, chemicals, entertainment media, automotive/vehicle manufacturing, and consumer products.
The study, the largest and the most comprehensive of its kind in India, analysed data across 1,000+ companies.
Anandorup Ghose, partner at Aon Hewitt India, said: “Political changes and economic headwinds have had an impact on business performance. However, the trend this year reflects a gradual slowing of pay increases and higher emphasis on productivity and performance – quite literally a ‘graying’ of salary budgets for India.
“The last year has shown organizations take a strong view towards performance differentiation and not only have bell curves become sharper, the pay differentiation between top and average performers has also increased.”