Sanjay Gupta, senior director of R&D, Mentor Emulation Division, Mentor, presented on the design verification trends and role of emulation.
Verification needs are expanding beyond traditional functional verification. SoC power analysis, coverage closure and DFT validations are critical. Vertical market segment focus is crucial as verification needs are different for different verticals. Verification teams are global teams. Veloce platform addresses the modern verification challenges.
Talking about the design trends, ~31 percent of designs use over 800 million gates and ~20 percent use over 500 million gates.Next, 72 percent of designs contain embedded processors, and 49 percent designs contain two or more processers, while 16 percent designs have eight or more processors.
As for ASIC/IC completion to the original schedule, 61 percent designs were behind schedule in 2014, which increased to 69 percent during 2016. The number of required ASIC/IC spins before production had become seven spins or more in 2016.
Regarding verification trends, as for more design engineers vs. verification engineers, design engineers were growing at CAGR 3.6 percent, while verification engineers were growing at CAGR 10.4 percent, from 2007-2016. The ASIC/IC verification engineers were spending 39 percent of their time at debugging, 22 percent each at creating test and running simulation, and testbench development, and 14 percent time in test planning.
SystemVerilog was a clear leader at the ASIC/IC verification language adoption, while Accelera UVM was a clear leader at the ASIC/IC testbench methodology adoption trends.
In power and coverage, 72 percent more designs wre actively managing power in 2016 as against 59 percent in 2007. Among the power intent trends, the UPF 2x was a clear leader among notations used to describe power intent. Functional coverage is just nearly on par with code coverage, followed by assertions and constrained-random simulation, as far as the ASIC/IC dynamic verification trends are concerned.
Challenges for verification include larger, more complex chips, as well as the increasing software content. Transistor count for select ICs will likely reach 15 billion gates by 2022.
Vertical segments are facing constant innovation. In networking, SDN emergence is driving complexity, size, and port count. There is an increased importance of software. Networking is driven by Big Data, cloud and mobility.
Safety is critical verification for automotive design. Veloce delivers the functional safety verification. Emulation has moved to virtualization with Veloce2. Data-center friendliness and enterprise-level usage are prime. Veloce Strato has accelerated and moved on to the application age, and has a vertical market focus.
Crystal chip is the brain of the Veloce emulation platform. A chip is designed exclusively for emulation: fast compile and efficient, full visibility. The chip, system and software are architected together to optimize the emulation capabilities and productivity. The Veloce Strato offers the lowest cost of ownership.
Veloce power app offers low-power verification at SoC level where power controls come from the application software, handles large SoC (RTL/Gate) with full visibility, performs complete verification (e.g. OS boot) and shows accurate power numbers based on real switching activity.
You can also do low power verification with Veloce. There is broad UPF 2.x support and UPF 3.0 support is planned by the end of 2017. Veloce coverage app has comprehensive SVA assertion support, SV functional coverage, code coverage, standard UCDB support and merged with simulation UCDB, and flow to enable XML merge with other platforms.
Anoop Saha, Mentor, did a presentation on Veloce vertical solutions at the Emulation Conference in Bangalore.
Veloce solutions are used across networking, storage, multimedia, mobile, CPU, automotive and military aeronautics. Veloce is structured around verticals to be segment focused, identify and address segment specific challenges, and identify gaps early on.
Veloce solutions are connecting the DUT to the external stimulus. iSolve speed adaptors connect real-life systems with the emulator. The Virtualab peripherals — VirtuaLab is the software representation of a speed adaptor. The Veloce transactor library – Veloce compatible verification IP. Transactors (VTL) to integrate with users UVM testbench and lower the abstraction layer.
In networking, for instance, the network switch is driving complexity. There is shift to SDN driving chip size and high port counts. Next, 5G is also driving new technology
and standards. Veloce for networking is offering solutions on top of core emulation platform. The verification flow is expanding to include Lab system validation. As of now, SDN is said to be creating a methodology shift. Mentor is said to be the only vendor with a complete offering.
Verification can no longer ignore firmware. Emulation enables earlier firmware development. Software debug is done with Codelink. The Veloce power app is used for broad base analysis. Veloce also offers complete solution for multimedia.
There has also been an industry shift from spec to benchmark. Many new apps target benchmarks for mobile devices. Examples are the AnTuTu benchmark, Geekbench for CPU and GPU benchmark, GFXBench, a GPU graphics centric benchmark, Android smartphone and tablet benchmark, etc.
Mentor, A Siemens Business, held a one-day conference on emulation in Bangalore and Hyderabad. I am thankful to my friends, Veeresh Shetty and Montu Makadia, for helping me attend this conference.
Shankar Bhat, Director, Engineering, Qualcomm India Pvt Ltd, in his keynote, titled 5G and Beyond – Emulation Challenges, said that a shrinking time to market, and stringent DPPM requirements drive the future of verification. Verification scope will extend from just hardware verification to software enablement. The emulation footprint in verification will significantly improve.
He added that mobile has been making a leap every 10 years. Today, it is redefining everything by creating the connectivity fabric for everything and bringing new levels of on-device intelligence. The long-term vision is to transform everything through intelligent connected platforms.
There is likely to be $12 trillion worth of 5G-related goods and services in 2035. Mobile is driving technology nodes and innovation. Verification focus has expanded from functionality to coverage to performance, on to power to yield and DPPM (defective parts per million). There is an over 30 percent NRE (non-recurring engineering) cost on design verification and emulation.
Post silicon validation and software testing time has been shirking. The post silicon test content, and software need to be fully validated before silicon arrival. Here, emulation plays a significant role in software readiness.
Regarding the key verification challenges, these are:
* Increased complexity: Test counts have increased, and there are much complex power structure and power domains. Also, there are challenging performance scenarios.
* Long simulation time: Simulator efficiency is not scaled. It is not able to complete all verification before tape out.
* Software enablement: Software expects fully verified design and settings.
* Customer enablement and DPPM reduction.
Emulation has several advantages. It has significantly faster run time, 1000X+ compared to simulation. It mimics hardware and closure to silicon. There is quick test portability between platforms.
Emulation will play significant role in design qualification, in both pre- and post-silicon phases. Software enablement will help achieve faster time-to-market. The challenges faced by emulation are a high NRE cost, limited debug capability, compilation time is still high, there are limited power verification capabilities. There are higher hardware costs as well in gate level verification, as it is difficult to fit the full SoC into the FPGA.
Emulation will play a significant role in hardware and software co-simulation. Tool portability is key. Verification will use multiple tools and flow. There will be the interpretability of tests, and data will be critical. EDA companies need to develop cost-effective emulation platforms.
Earlier, welcoming the audience, Ruchir Dixit, Technical Director-India, Mentor, said that the status quo is uncomfortable. He compared the cost of laying a metro network in Bangalore, which can cost between Rs. 8,000-14,000 crores. For emulation, while, it was expensive, it was about time that developers got used to it.
Mentor Graphics Corp. recently announced the Veloce StratoM emulation platform.
The Veloce Strato platform is Mentor’s third generation data-center friendly emulation platform. It is said to be the only emulation platform with full scalability across both software and hardware. Mentor is also launching the Veloce StratoM high-capacity emulator and Veloce Strato OS enterprise-level operating system.
So, how is the Veloce StratoM platform suitable for data centers than previous version?
According to Montu Makadia, one of the worldwide ATM – Emulation experts at Mentor Graphics ; with the Veloce StratoM emulator, there are no major changes to the lab requirements.
There is the same footprint, lower total power consumption, and lower total cooling requirement (air-cooled, air extraction from top). There is an added flexibility on the door and panel (new in Veloce Strato) that makes system maintenance easier.
The Veloce Strato Platform plans for highest effective capacity (up to 15BG) available. Does it really go up to 15BG? If yes, where are the test results?
According to a Mentor Graphics’ spokesman, as of now, no test results are required. Connecting emulators via a sophisticated connection method is common for Veloce. In this case, the Veloce Strato Link can be used to connect multiple Veloce StratoM emulators to reach 15BG capacity.
“We have installations at companies that will not allow us to talk about them by name. These are large, multinational companies with very advanced verification and validation requirements. The installations have gone extremely well and deployment is underway and happening without issue,” the spokesman added.
Mentor is saying there will be a roadmap to 15BG over five years and beyond? What if others come up with a faster system in between?
The spokesperson said: “We can’t predict what other emulation vendors will do in the next five years. We have done our competitive research and believe that we are uniquely positioned to have, both, the largest capacity available in 2021, as well as the emulation platform with the highest RoI.”
Finally, how is the Veloce Strato OS enterprise-level operating system a step above the earlier OS?
The Veloce Strato OS is the centerpiece of the technology for the overall Veloce architecture. The Veloce operating system basically enables three things: The first is the primary core compiler flow. When you use an emulator, you need to compile the design. You synthesize and partition, and move from an RTL/netlist to something that is mapped to the hardware (P&R).
The Veloce Strato OS delivers an integrated, fully automated, single step compilation flow with about 3x faster compilation time and with a 100 percent compile success rate. The compilation time and a 100 percent compile success is one of the key differentiators compared to an FPGA-based emulator.
The OS enables all the use models of verification with a unified compilation, runtime and debug flow. That includes traditional ICE (physical targets-based stimulus), the other virtual use models (SW device models) and testbench acceleration (SW test benches, UVM, SV, SC, TLM, etc.).
The third unique attribute is advanced debug. In addition to the waveform support, it supports Livestream to view a set of important signals, key register for long emulation runs as tests are progressing and Veloce’s unique ‘save and restore’ replay to restore emulation sessions instantaneously at a specified time point for detailed debug activities without re-running the emulation from the beginning.