At the ongoing ITC 2018 conference, Raja Manickam, founder and CEO, Tessolve, spoke on ‘Always on ERA’?
Every chip is tested. About 10 million++ chips are tested every day. A chip carries millions of data and also does continuous self test. It is expected that the chip is always on. Engineers look at all possible combinations. They try and solve problems quickly.
Design is supposed to be pure genius. However, testing is the necessary evil. There is DFT to probe FT and SLT. We just keep on adding tests.
The players who help drive us are the academia, EDA companies, fabs, and ATEs (they add more instruments, and make it bigger). What matters is that the chip must work in a particular manner, all the time.
Test leadership creates an environment for test strategy and drives it. There must be given flexibility and innovation for test leadership. Focus on the end-user relevancy.
Next-gen BIST provides M-BIST and scan compression engines on separate DFx die. The ATE interface can exist in the DFx die. Base functional die will provide power and clocks.
At any time a machine is running, less than 20 percent of the instruments are used. That’s not the best use of assets.
Factors influencing traditional ATE include loop back testing, ATE need to test deserialized parallel data, miniature MEMS loop back device to improve SI and MEMS RF relay, and the use of FPGAs.
There are adaptive tests and predictive algorithms. The ATE could look like instrumentation and intelligence built in to the load board or hardware. There could be three dimensional handlers. The handler will go vertical. There should be an end-user driven test strategy. The test strategy should be holistic.