ITC India to address design, test, and yield challenges

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The forthcoming International Test Conference (ITC) will be held on July 22nd-24th, 2018, at the Radisson Blu Hotel in Marathalli, Bangalore.

I must thank Navin Bishnoi, General Chair, ITC India, and director, ASIC India Design Center, GLOBALFOUNDRIES, and Veeresh Shetty, senior marketing manager, Mentor, for apprising me of developments.

The second edition of the conference, it is the world’s premier event dedicated to the electronic test of devices, boards and systems. At ITC India, design, test, and yield professionals can confront challenges faced by the industry, and learn how these challenges are being addressed by the combined efforts of academia, design tool and equipment suppliers, designers, and test engineers. The ITC India is being run under the guidance of ITC USA, and is supported by the IEEE Bangalore Section and IESA.

NavinLet’s look at the test challenges that the conference seeks to address. Navin Bishnoi said:  “DFT, test and reliability domains are seeing a huge focus with the need of standard test practices for a variety of applications across communication, automotive, computing and industrial.

“In addition, the cost of implementation and testing continues to be challenged, asking designers to look at innovative ways to optimize test, without impacting quality. ITC India brings the best minds from academia, research and industry to share best practices to enable the standard DFT/Test practices for variety of applications with reduced cost and high quality.

“The conference covers sessions on emerging test needs for topics such as: artificial intelligence, automotive and IoT, hardware security, system test, analog and mixed signal test, yield learning, test analytics, test methodology, benchmarks, test standards, memory and 3D test, diagnosis, DFT architectures, functional- and software-based tests.”

Next, what is the focus on DFT architecture and DFT strategy in automotive and other devices with low-cost testing requirements?

He added: “Today’s automotive safety-critical chips need multiple in-system self-test modes, such as power-on self-test and repair, periodic in-field self-test during mission mode, advanced error correction solutions, redundancy, etc. The conference has numerous presentations on summarizing the implications of automotive test, reliability and functional safety on all aspects of the SoC lifecycle, while accelerating the time-to-market for automotive SoCs.

“There is a strong focus on understanding the increasing use of system-level tests to screen smartphone and notebook processors for manufacturing defects by taking an in-depth look at the limitations of state-of-the-art scan test methodology. In addition, there is continuous study in the fields of DFT, diagnosis, yield learning, and root cause analysis, which use machine learning algorithms for solving various problems.”

Trends in modelling
Let us also look at the the trends in modelling and the simulation of defects in analog circuits and their applications that the conference seeks to address.

Bishnoi said that digital circuits have now evolved to standardize fault modeling and simulation. However, analog circuits have work in progress to look at new methods for modeling and simulating different types of faults using a mixed-signal fault injection methodology.

“Modeling defects in analog circuit use transient analyses that leverage different methods to inject faults. This is critical for today’s use case applications, like automotive, sensors, and industrial, which has significant analog components in the SoC. One of the trends that will be addressed in the conference is the layout-based fault modelling that is in fact a statistical analysis of process defects.

Now, to the directions made in advanced packaging technology. What’s the road ahead?

Bishnoi added: “Packaging technology has exploded with complexity in recent times for need of stacked dies, which involves change in processes, materials, equipment, as well as in the SoC implementation and sign-off. Advanced packaging enables small form-factor chips, with high-speed functionality for consumer market.

And, how are challenges in analog loopback testing for RF transceivers being addressed?

He said: “The main challenge in the implementation of loopback testing for RF transceivers is distinguishing the non-linearity effects of Rx and Tx, performance of channels during parallel testing, as well as coupling effects. Various test solutions will be discussed during the conference to address the challenges of an analog loopback testing of RF transceivers. Solutions employing the BiST techniques to have a quick TAT during manufacturing test will also be discussed.”

For those unaware, BiST or the built-in self-test, is a design technique in which parts of a circuit are used to test the circuit itself.

Finally, which version of the conference is this? Are we going to see regular ones? Bishnoi noted: “This is the second edition of the conference. We went through rigorous analysis and discussions with global leaders about the frequency and venue of the conference. It was decided to keep it annually (with the amount of growth in test/reliability space), as well as to keep it in Bangalore for the first 5 years, before we review it again to check if we should take it to other cities in India.

“The conference includes four keynotes from visionary leaders from Synopsys, Tessolve, Intel and Mentor Graphics, an exciting panel discussion on Fault Tolerance or Fault In-tolerance, as well as a variety of technical sessions and exhibits/demos from sponsors. It also has a dedicated day (on Sunday) for tutorials on six topics covering automotive, analog test, IEEE standards, machine learning in-test, system-level test and security.”

I will be present at ITC India 2018 in Bangalore, and look forward to meeting many of you, the attendees, as well! 🙂

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