Semiconductor industry performance a pleasant surprise: Dr. Wally Rhines

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The year 2018 is nearly upon us! And, who better than Dr. Walden C. Rhines, CEO and chairman of the Board of Directors of Mentor, a Siemens business, a leading industry personality, to provide us with an outlook for the global semiconductor industry!

Dr. Wally Rhines and I chatted about the global semiconductor and EDA industries, the Accellera Portable Stimulus Standard (PSS), and a host of other issues.

Semicon industry in 2018
First, how is Mentor predicting the global semiconductor industry to perform in 2018?

Dr. Rhines said: “The semiconductor industry performance for 2017 has been a pleasant surprise for most industry observers. The year is finally winding down, with the expectations for growth in the low 20s on the average – nearly 3-4 times as much as most observers had predicted only one year ago.

“Unit growth has consistently been 7-9 percent in recent years since the great recession. However, ASPs have been pretty consistently declining until 2017, when they were driven up mostly by memory prices for DRAMs and FLASH. Memory, once again, is behind the 2017 boom cycle. However, the rest of the IC business has also been relatively strong with growth in the higher single digits (7-8 percent), which is stronger than we have experienced in recent years.

“Memory prices are expected to soften as additional capacity comes on-line in 2018, especially as the year continues into the second half. However, the remainder of the non-memory semiconductor market should continue to have strong performance similar to 2017 (~7-8 percent) as the market fundamentals remain strong.

“Over the last several years, the semiconductor industry has experienced a wave of consolidations. I believe that we are between major waves of growth that are typical of the semiconductor industry. Historically, new semiconductor growth is ushered in by new applications that become possible when the cost per function, or some other new capability, makes the new application possible.

“In recent years, the cost per transistor for semiconductors has decreased more than 35 percent per year, just as it has, on average, for most of the last 60 years. It’s likely that continuation of this trend will, in fact, enable future waves of new semiconductor applications.

“Packaging, as well as package/chip simulation, continue to be important issues. Next generation simulation, verification, and analysis for multi-chip packaging configurations is now available. Now, designers of chips can intelligently analyze the packaging and pin-out configurations that will be most effective for cost and performance, based on a steady flow of data between the packaging engineer and the chip designer.”

EDA segment in 2018
And, how is the EDA segment looking in 2018?

According to Dr. Rhines, the EDA License and Maintenance is having a strong year in 2017. The annual growth is over 9 percent through the most recent four quarters with available data (Q3 2016 – Q2 2017).

He said: “The Semiconductor IP component of EDA achieved growth of nearly 17 percent overall, over the same period, as would be expected since Semiconductor IP is an important part of the supply chain for the broader semiconductor market.

“With expectations for the world economy and the overall semiconductor industry remaining strong, I expect semiconductor investment into design to also remain strong. EDA License and Maintenance is accounted for within the semiconductor company R&D expense budgets. Those budgets have a strong correlation to EDA License and Maintenance revenue. Therefore, I expect similarly strong growth in 2018.

Advanced nodes driving EDA tool adoption
How are advanced nodes continuing to drive EDA tool adoption in manufacturing and design?

Dr. Rhines said: “In a way, we are blessed to have the demands of Moore’s Law and the ongoing migration to more demanding nodes, as the fundamental physics tends to break tools and demand more on a routine basis, thus driving a constant drum beat of innovation.

“The industry continues its march down the IC nodes, with 10/7nm in production at the leading edge designs. The challenges are multifaceted: low power, lower manufacturing costs, and performance are some of the larger concerns at these nodes. EDA is addressing all these with new technologies and solutions.

Extreme Ultra Violet (EUV) photolithography has not yet become mainstream, resulting in the manufacturing and design community adopting techniques for more double/triple and even quadruple patterning. There have now been sufficient tape-outs that things seem to be stabilizing, and the number of 10nm and 7nm designs is accelerating along with announcements of schedules for 5nm and 3nm generations.”

Functional verification driving technology adoption
And, how are the increased challenges and methodologies in functional verification driving technology adoption?

“Aside from the growing complexity and increased integration challenges one would expect with the introduction of every new technology node, over the past 10 years our industry has witnessed an explosion of new layers of requirements for verification.

“For example, beyond the requirements to verify the traditional functional domain issues, we have added clock domains, power domains, mixed-signal domains, security domains, safety, software, and then obviously overall performance requirements. This is driving the need for multiple focused solutions and technology optimized for specific verification concerns.

“Examples of these focused solutions include formal apps, used to verify security features within a design, and power apps used to provide complete RTL power exploration and accurate gate-level power analysis within emulation.

“We are also seeing a need for greater convergence across multiple verification engines (e.g., simulation, emulation, and FPGA prototyping). This is necessary to improve productivity. Our industry is addressing these concerns through the development of the new Accellera Portable Stimulus Standard (PSS), which will help facilitate this convergence and foster the introduction of new verification solutions and technology.”

The concluding part continues on Dec. 14th, 2017.


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