Month: December 2017
Here is the concluding part of my discussion with Dr. Walden Rhines, chairman and CEO, Mentor, A Siemens Company.
Has the PSS been formally released? What are its implications?
Dr. Rhines said: “Accellera released an Early Adopter spec for public review at DAC in June, 2017 and is currently working on completing our work in preparation for a 1.0 release in 2018. Accellera plans to have a “1.0 Preview” version available in February, 2018 (@DVCon US) for another 30-day public review period. Then, they will do one more cleanup pass, and submit to the Accellera Board for approval in May 2018.
“The expectation is that the Board will approve the Portable Stimulus Standard 1.0 version in June, 2018, prior to the DAC. Mentor plans to have Questa inFact fully updated by then, to fully support the new standard when it comes out.
“As for the implications, we expect the Portable Stimulus standard to be the next advancement in abstraction and productivity for SoC verification. It is not expected to replace UVM, but rather be complementary to UVM to improve coverage closure, verification efficiency, and effectiveness at the block level.
“The ability to re-use the verification intent expressed in PSS from a block-level UVM environment to a software-driven, embedded-processor SoC environment, on multiple platforms (simulation, emulation, FPGA prototyping, etc.), will provide a quantum leap in productivity.
“Since the Portable Stimulus specifications are declarative, tools can fully analyze the verification-intent description at the system level and generate multiple correct-by-construction implementations of use case tests, on multiple platforms, from a single specification without requiring the verification team to rewrite the tests in UVM for the blocks and C for the system.
By the way, are the semiconductor/EDA companies re-looking at designs, rather than analyze more than 500,000 defective parts every day to identify design and process problems? If yes, how?
He said: “With today’s increased design complexity – they do both – re-look at designs before manufacturing and analyze afterwards. The complexity of today’s designs and manufacturing process requires multiple approaches to achieve high yields in each new node that is rolled out.
“Design for manufacturing and for yield are a must. However, the knowledge of the specific design practices that need to be followed for a new node is developed in multiple stages: in pre-silicon, test chips, first production design and when chips reach high production volume.
* Pre-silicon: Simulation models are used for initial design rules. Many assumptions are made and care must be taken to balance the benefit with potential overdesign for a process that will mature over time.
* Test chips: Early test chips try to mimic the major features of a real design, however, limited complexity and volume means some design rules can’t be discovered at this stage.
* First production design: Additional complexity of a real design and increased volumes expose more issues that need to be fed back to design for future revisions or the next design on a node.
* High production volume and additional designs introduced: High production volume and each subsequent design can benefit from the learnings at the previous stages. Many issues during this phase are resolved with process improvements, but continuous learning still remains key.
“The challenge is not eliminating the later learning phases, as this will never go away. Rather, the challenge is for the industry to maximize the learning at each phase and establish a continuous improvement cycle in design to take advantage of the knowledge gained. This is the foundational idea in closed-loop DFM, which is a process to maximize the design for manufacturing benefit throughout all phases.
Let’s also look at verification. What is the latest regarding coverage and power across all the aspects of verification?
Dr. Rhines added: “Actually, the recent trends have expanded to multiple concerns that cut across all aspects of verification, beyond coverage and power, such as security and safety. One driving force behind these trends is the convergence of computing, networking, and communications technologies. This is driving new markets, such as the Internet-of-things (IoT) ecosystem and automotive.
“A common theme across these emerging systems is the need for security, safety, and low power–whether you are talking about IoT edge devices or high-availability systems in the cloud. These new challenges have opened innovation opportunities, enabling us to rethink the way we approach verification. For example, concerning coverage, new statistical metrics have emerged providing deep system-level analysis capabilities that leverage data analytics techniques. This insight has become essential for system-level performance analysis.
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The year 2018 is nearly upon us! And, who better than Dr. Walden C. Rhines, CEO and chairman of the Board of Directors of Mentor, a Siemens business, a leading industry personality, to provide us with an outlook for the global semiconductor industry!
Dr. Wally Rhines and I chatted about the global semiconductor and EDA industries, the Accellera Portable Stimulus Standard (PSS), and a host of other issues.
Semicon industry in 2018
First, how is Mentor predicting the global semiconductor industry to perform in 2018?
Dr. Rhines said: “The semiconductor industry performance for 2017 has been a pleasant surprise for most industry observers. The year is finally winding down, with the expectations for growth in the low 20s on the average – nearly 3-4 times as much as most observers had predicted only one year ago.
“Unit growth has consistently been 7-9 percent in recent years since the great recession. However, ASPs have been pretty consistently declining until 2017, when they were driven up mostly by memory prices for DRAMs and FLASH. Memory, once again, is behind the 2017 boom cycle. However, the rest of the IC business has also been relatively strong with growth in the higher single digits (7-8 percent), which is stronger than we have experienced in recent years.
“Memory prices are expected to soften as additional capacity comes on-line in 2018, especially as the year continues into the second half. However, the remainder of the non-memory semiconductor market should continue to have strong performance similar to 2017 (~7-8 percent) as the market fundamentals remain strong.
“Over the last several years, the semiconductor industry has experienced a wave of consolidations. I believe that we are between major waves of growth that are typical of the semiconductor industry. Historically, new semiconductor growth is ushered in by new applications that become possible when the cost per function, or some other new capability, makes the new application possible.
“In recent years, the cost per transistor for semiconductors has decreased more than 35 percent per year, just as it has, on average, for most of the last 60 years. It’s likely that continuation of this trend will, in fact, enable future waves of new semiconductor applications.
“Packaging, as well as package/chip simulation, continue to be important issues. Next generation simulation, verification, and analysis for multi-chip packaging configurations is now available. Now, designers of chips can intelligently analyze the packaging and pin-out configurations that will be most effective for cost and performance, based on a steady flow of data between the packaging engineer and the chip designer.”
EDA segment in 2018
And, how is the EDA segment looking in 2018?
According to Dr. Rhines, the EDA License and Maintenance is having a strong year in 2017. The annual growth is over 9 percent through the most recent four quarters with available data (Q3 2016 – Q2 2017).
He said: “The Semiconductor IP component of EDA achieved growth of nearly 17 percent overall, over the same period, as would be expected since Semiconductor IP is an important part of the supply chain for the broader semiconductor market.
“With expectations for the world economy and the overall semiconductor industry remaining strong, I expect semiconductor investment into design to also remain strong. EDA License and Maintenance is accounted for within the semiconductor company R&D expense budgets. Those budgets have a strong correlation to EDA License and Maintenance revenue. Therefore, I expect similarly strong growth in 2018.
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What’s with names and numbers? It all started when a friend casually asked me whether I was destined to win so many awards! Now, I don’t even know why I have won so many awards for my blogs. Actually, it was 17 at last count, 16 international and one national. We did a numerology report. A table is given here for those interested.
First, my full name. PRADEEP CHAKRABORTY.
PRADEEP = 7+9+1+4+5+5+7 = 38/2
CHAKRABORTY = 3+8+1+2+9+1+2+6+9+2+7 = 50
So, PRADEEP CHAKRABORTY, added together is 38+50 = 88+8 = 16. And, 1+6=7.
Now, my favourite subject: SEMICONDUCTORS.
SEMICONDUCTORS = 1+5+4+9+3+6+5+4+3+3+2+6+9+1 = 61 – 6+1 = 7.
ELECTRONICS = 5+3+5+3+2+9+6+5+9+3+1 = 51 = 5+1 = 6.
ELECTRONIC = 5+3+5+3+2+9+6+5+9+3 = 50 = 5+0 = 5
COMPONENTS = 3+6+4+7+6+5+5+5+2+1 = 44 = 4+4 = 8. Total” 5+8 = 13/4.
TELECOMMUNICATIONS: 2+5+3+5+3+6+4+ 4+3+5+9+3+1+2+9+6+5+1 = 76 = 7+6 = 4.
Three things are very clear! One, semiconductors has ALWAYS been my favorite for a number of reasons. The first reason is very simple – my name and the subject — 7 and 7, match! Two, electronics comes very close, and it also, somehow, runs the world. Three, so does the electronic components, but as the number 4 suggests, it is a subject difficult to grasp. The same applies to telecoms, as well.
Don’t agree with me? Well, as a question: please ask your friend: what does your phone do? He/she will come up with a long list. If you rephrase the question as to: what node is the platform (for a device) based on, the answer will be ‘silence‘! 😉
Okay, this is getting a bit boring! 🙂 Let’s have some fun with sports, eh?
ATHLETICS: 1+2+8+3+5+2+9+3+1 = 34/7. Difficult, but very entertaining. To excel, you need to work very hard.
BADMINTON: 2+1+4+4+9+5+2+6+5 = 38/2. A game favoured by romantics. Elegant to watch. Smash it! 😉
BASKETBALL: 2+1+1+2+5+2+2+1+3+3 = 22/4 – Fast paced. You need to be fast paced too!
BOXING: 2+6+6+9+5+7 = 35/8. This is a game for tough men and women who can take a pounding.
CHESS: 3+8+5+1+1 = 18/9. Played by few. Understood by few.
CRICKET: 3+9+9+3+2+5+2 = 33/6. A game for the masses. Interesting, that there are a handful of test teams in the world. Mostly, former British colonies.
FOOTBALL: 6+6+6+2+2+1+3+3 = 29/2. Very popular, but rough game, for the masses.
JUDO: 1+3+4+6 = 14/5 = Again, for the masses. Few practitioners in India, though
GYMNASTICS: 7+7+4+5+1+1+2+9+3+1 = 40/4. This one’s tough, but makes for great watching.
SWIMMING: 1+5+9+4+4+9+5+7 = 44/8. A tough game. Prefers folks who are very fit!
TAE-KWAN-DO: 2+1+5+2+5+1+5+4+6 = 31/4. Same as above.
TABLE TENNIS: 2+1+2+3+5+2+5+5+5+9+1 = 40/4. Fast paced! Same as above.
TENNIS: 2+5+5+5+9+1 = 27/9. A sport for the masses, featuring gladiators.
VOLLEYBALL: 4+6+3+3+5+7+2+1+9+9 = 49/4. This one’s needs tremendous agility. Well, which game doesn’t?
WEIGHTLIFTING: 5+5+9+7+8+2+3+9+6+2+9+5+7 = 77/5. For supermen and women.
Let’s look at sports. SPORTS: 1+7+6+9+2+1 = 26/8.
Sports itself, is a difficult discipline. So, how can anyone excel in any one among these sports, or well, in life? Simple. By doing hard work! 🙂 It all comes to those individuals who work hard nearly all their life.
Friends, I encourage all of you to try out your full name and full date of birth, (eg. 01-02-2011) separately, and respectively, to see where you stand in life! 🙂
Be aware! Numbers DO NOT make any man or woman. Only HARD WORK does! 🙂 You need to be agile, have the necessary skills, and speed, to excel in any field!
AGILE: 1+7+9+3+5 = 25/7.
SKILLS: 1+2+9+3+3+1 = 19/1.
SPEED: 1+7+5+5+4 = 22/4.
HARD WORK: 8+1+9+4+5+6+9+2 = 43/7.
Finally, in case I’ve made any mistakes, while adding up the numbers, kindly forgive me. I am NOT an astrologer. 🙂