Month: April 2017

Mentor unveils Veloce Strato emulation platform with highest RoI

Posted on Updated on

Mentor Graphics Corp. recently announced the Veloce StratoM emulation platform.

The Veloce Strato platform is Mentor’s third generation data-center friendly emulation platform. It is said to be the only emulation platform with full scalability across both software and hardware. Mentor is also launching the Veloce StratoM high-capacity emulator and Veloce Strato OS enterprise-level operating system.

So, how is the Veloce StratoM platform suitable for data centers than previous version?

According to Montu Makadia, one of the worldwide ATM – Emulation experts at Mentor Graphics ; with the Veloce StratoM emulator, there are no major changes to the lab requirements.

There is the same footprint, lower total power consumption, and lower total cooling requirement (air-cooled, air extraction from top). There is an added flexibility on the door and panel (new in Veloce Strato) that makes system maintenance easier.

The Veloce Strato Platform plans for highest effective capacity (up to 15BG) available. Does it really go up to 15BG? If yes, where are the test results?

According to a Mentor Graphics’ spokesman, as of now, no test results are required. Connecting emulators via a sophisticated connection method is common for Veloce. In this case, the Veloce Strato Link can be used to connect multiple Veloce StratoM emulators to reach 15BG capacity.

“We have installations at companies that will not allow us to talk about them by name. These are large, multinational companies with very advanced verification and validation requirements. The installations have gone extremely well and deployment is underway and happening without issue,” the spokesman added.

Mentor is saying there will be a roadmap to 15BG over five years and beyond? What if others come up with a faster system in between?

The spokesperson said: “We can’t predict what other emulation vendors will do in the next five years. We have done our competitive research and believe that we are uniquely positioned to have, both, the largest capacity available in 2021, as well as the emulation platform with the highest RoI.”

Finally, how is the Veloce Strato OS enterprise-level operating system a step above the earlier OS?

The Veloce Strato OS is the centerpiece of the technology for the overall Veloce architecture. The Veloce operating system basically enables three things: The first is the primary core compiler flow. When you use an emulator, you need to compile the design. You synthesize and partition, and move from an RTL/netlist to something that is mapped to the hardware (P&R).

The Veloce Strato OS delivers an integrated, fully automated, single step compilation flow with about 3x faster compilation time and with a 100 percent compile success rate. The compilation time and a 100 percent compile success is one of the key differentiators compared to an FPGA-based emulator.


The OS enables all the use models of verification with a unified compilation, runtime and debug flow. That includes traditional ICE (physical targets-based stimulus), the other virtual use models (SW device models) and testbench acceleration (SW test benches, UVM, SV, SC, TLM, etc.).

The third unique attribute is advanced debug. In addition to the waveform support, it supports Livestream to view a set of important signals, key register for long emulation runs as tests are progressing and Veloce’s unique ‘save and restore’ replay to restore emulation sessions instantaneously at a specified time point for detailed debug activities without re-running the emulation from the beginning.

Move to emulation continues to gather momentum: Dr. Wally Rhines

Posted on Updated on

Here is the concluding part of my discussion with Dr. Walden C. Rhines, chairman and CEO, Mentor Graphics.

Getting billion-gate design correct
In EDA, is there now some chance of getting a billion-gate design correct on first pass?

Dr. Rhines said: “Absolutely! Today’s methodology is up to the task and customers have already reported “billion gate equivalent” designs, i.e., 4 billion transistor, correct on first pass. Correct logic is a much easier challenge than full production readiness on first pass!

Rhines“Achieving targeted power dissipation and timing has been more of a challenge but that’s where recent tool improvements are having their greatest impact. Almost all designs of this size now go through exhaustive verification, including power analysis, using emulation. That change in methodology has increased the cycles of verification by more than three orders of magnitude.

“Beyond simply achieving functional silicon with acceptable power and timing, more and more companies are now using EDA tools to assure a rapid ramp to high yield in production. This requires use of a whole new generation of “design for test” tools directed at defect driven yield analysis.

“By our measures, some of the top semiconductor companies analyze more than 500,000 defective parts every day to identify design and process problems.”

Standardization of SoC verification flow
Next, what is the status of the standardization of SoC verification flow today?

He said that Mentor Graphics has long worked on providing leading functional verification products. “We are doubling down on perfecting tools that are part of an enterprise platform where common testbench stimulus, verification IP, and standard verification languages can be used up and down the tool chain. However, the flow belongs to the customer.

“We do not try to enforce a “standard verification flow”. We are happy to accommodate unique customer needs and trust our customer to know the unique requirements of their own markets.

It would be interesting to know what has been happening regarding the coverage and power across all aspects of verification?

According to Dr. Rhines, power management debug has permeated all aspects of traditional HDL based verification. For large SoCs, debugging power-management related problems is a very difficult task. Power is managed wholly or in part by software. Increasingly, validation of power managed designs, including power estimation, requires hardware accelerated solutions such as emulation and prototypes.

New releases of the UPF standard include lots of new capabilities that help verify power usage but that do require additional effort to analyze. Examples include dynamic power related messages, automatic power specific assertion generation and support for the entire flow from simulation through emulation and prototypes.

In addition, lots of designs now use new tools for power management verification, static analysis, rule based power checks and power-aware logic equivalence checking.

Similarly, what is happening in active power management today?

He said that active power management creates the need for functional verification. Traditionally, power has been managed via clock gating, power gating and dynamic voltage and frequency scaling.

The first two methods (clock and power gating) directly impact functionality necessitating the need for things like isolation with clamp values on inputs or outputs to a power gated block of logic, retention registers and gating logic for clocks, as well as the associated control signals or registers and the state machines, which manage the transitions from one state to another.

Verification of the active power management logic and control states necessitates the need for UPF support in verification solutions. The challenge in debugging power management issues drives the value in dynamic checks to ensure valid power down and up sequences, save/restore or resetting/write-before-read behavior of registers in power domains and proper activation and de-activation of isolation logic values.
Read the rest of this entry »